Re: [dpdk-dev] [PATCH] mempool/octeontx2: optimize for L1D cache architecture

2020-01-31 Thread Jerin Jacob
On Fri, Jan 31, 2020 at 6:21 PM wrote: > > From: Pavan Nikhilesh > > OCTEON TX2 has 8 sets, 41 ways L1D cache, VA<9:7> bits dictate > the set selection. > Add additional padding to ensure that the element size always > occupies odd number of cachelines to ensure even distribution > of elements am

[dpdk-dev] [PATCH] mempool/octeontx2: optimize for L1D cache architecture

2020-01-31 Thread pbhagavatula
From: Pavan Nikhilesh OCTEON TX2 has 8 sets, 41 ways L1D cache, VA<9:7> bits dictate the set selection. Add additional padding to ensure that the element size always occupies odd number of cachelines to ensure even distribution of elements among L1D cache sets. Signed-off-by: Pavan Nikhilesh Si