[dpdk-dev] [PATCH] ixgbe: fix bad shift operation in ixgbe_set_pool_rx

2016-04-22 Thread Kulasek, TomaszX
> -Original Message- > From: Richardson, Bruce > Sent: Thursday, April 21, 2016 17:28 > To: Kulasek, TomaszX > Cc: dev at dpdk.org; Zhang, Helin ; Ananyev, > Konstantin > Subject: Re: [dpdk-dev] [PATCH] ixgbe: fix bad shift operation in > ixgbe_set_pool_rx >

[dpdk-dev] [PATCH] ixgbe: fix bad shift operation in ixgbe_set_pool_rx

2016-04-21 Thread Bruce Richardson
tantin > > Subject: Re: [dpdk-dev] [PATCH] ixgbe: fix bad shift operation in > > ixgbe_set_pool_rx > > > > On Fri, Apr 15, 2016 at 03:39:09PM +0200, Tomasz Kulasek wrote: > > > CID 13193 (#1 of 1): Bad bit shift operation (BAD_SHIFT) > > > large_shift: In e

[dpdk-dev] [PATCH] ixgbe: fix bad shift operation in ixgbe_set_pool_rx

2016-04-21 Thread Bruce Richardson
On Fri, Apr 15, 2016 at 03:39:09PM +0200, Tomasz Kulasek wrote: > CID 13193 (#1 of 1): Bad bit shift operation (BAD_SHIFT) > large_shift: In expression 1 << pool, left shifting by more than 31 bits > has undefined behavior. The shift amount, pool, is at least 32. > > This patch limits mask shift t

[dpdk-dev] [PATCH] ixgbe: fix bad shift operation in ixgbe_set_pool_rx

2016-04-21 Thread Kulasek, TomaszX
> -Original Message- > From: Richardson, Bruce > Sent: Thursday, April 21, 2016 15:52 > To: Kulasek, TomaszX > Cc: dev at dpdk.org; Zhang, Helin ; Ananyev, > Konstantin > Subject: Re: [dpdk-dev] [PATCH] ixgbe: fix bad shift operation in > ixgbe_set_pool_rx >

[dpdk-dev] [PATCH] ixgbe: fix bad shift operation in ixgbe_set_pool_rx

2016-04-18 Thread Lu, Wenzhuo
Hi Tomasz, > -Original Message- > From: dev [mailto:dev-bounces at dpdk.org] On Behalf Of Tomasz Kulasek > Sent: Friday, April 15, 2016 9:39 PM > To: dev at dpdk.org > Cc: Zhang, Helin; Ananyev, Konstantin > Subject: [dpdk-dev] [PATCH] ixgbe: fix bad

[dpdk-dev] [PATCH] ixgbe: fix bad shift operation in ixgbe_set_pool_rx

2016-04-15 Thread Tomasz Kulasek
CID 13193 (#1 of 1): Bad bit shift operation (BAD_SHIFT) large_shift: In expression 1 << pool, left shifting by more than 31 bits has undefined behavior. The shift amount, pool, is at least 32. This patch limits mask shift to be in range of 32 bit PFVFRE[1] register, for pool > 31. Fixes: fe3a45f