Re: [dpdk-dev] [EXT] Default cacheline size for ARM

2019-02-01 Thread Jerin Jacob Kollanukkaran
On Thu, 2019-01-31 at 18:09 +, Honnappa Nagarahalli wrote: > + Phil and Hemant > > > > > > > > > Yes, we need to be inline with any other package. My > > > > > > understanding is that the image will be same for v8,v9,v10 > > > > > > (any > > > > > > input from distro engineers will help here

Re: [dpdk-dev] [EXT] Default cacheline size for ARM

2019-01-31 Thread Honnappa Nagarahalli
+ Phil and Hemant > > > > > Yes, we need to be inline with any other package. My > > > > > understanding is that the image will be same for v8,v9,v10 (any > > > > > input from distro engineers will help here). So, my question is, > > > > > should the config file/name used by distros contain anyt

Re: [dpdk-dev] [EXT] Default cacheline size for ARM

2019-01-28 Thread Jerin Jacob Kollanukkaran
On Wed, 2019-01-23 at 16:28 +, Honnappa Nagarahalli wrote: > > On Fri, 2019-01-18 at 05:50 +, Honnappa Nagarahalli wrote: > > > > > > > > > > Hi, > > > > > > > > > > > > > > > > > > > > The cacheline size (RTE_CACHE_LINE_SIZE) for ARM > > > > > > > > > > CPUs is > > > > > > > > > > set to

Re: [dpdk-dev] [EXT] Default cacheline size for ARM

2019-01-23 Thread Honnappa Nagarahalli
> On Fri, 2019-01-18 at 05:50 +, Honnappa Nagarahalli wrote: > > > > > > > > > Hi, > > > > > > > > > > > > > > > > > > The cacheline size (RTE_CACHE_LINE_SIZE) for ARM CPUs is > > > > > > > > > set to be 128B by default. Mellanox's BlueField is an > > > > > > > > > ARM CPU having > > > > > > >

Re: [dpdk-dev] [EXT] Default cacheline size for ARM

2019-01-23 Thread Jerin Jacob Kollanukkaran
On Fri, 2019-01-18 at 05:50 +, Honnappa Nagarahalli wrote: > > > > > > > > Hi, > > > > > > > > > > > > > > > > The cacheline size (RTE_CACHE_LINE_SIZE) for ARM CPUs > > > > > > > > is set > > > > > > > > to be 128B by default. Mellanox's BlueField is an ARM > > > > > > > > CPU > > > > > > > >

Re: [dpdk-dev] [EXT] Default cacheline size for ARM

2019-01-17 Thread Honnappa Nagarahalli
> > > > > > > Hi, > > > > > > > > > > > > > > The cacheline size (RTE_CACHE_LINE_SIZE) for ARM CPUs is set > > > > > > > to be 128B by default. Mellanox's BlueField is an ARM CPU > > > > > > > having > > > > > > > Cortex-A72 > > > > > > > and its CL size is 64B. > > > > > Just wondering how many de

Re: [dpdk-dev] [EXT] Default cacheline size for ARM

2019-01-15 Thread Honnappa Nagarahalli
> > > > > > Hi, > > > > > > > > > > > > The cacheline size (RTE_CACHE_LINE_SIZE) for ARM CPUs is set > > > > > > to be 128B by default. Mellanox's BlueField is an ARM CPU > > > > > > having > > > > > > Cortex-A72 > > > > > > and its CL size is 64B. > > > > Just wondering how many devices are out th

Re: [dpdk-dev] [EXT] Default cacheline size for ARM

2019-01-14 Thread Jerin Jacob Kollanukkaran
On Mon, 2019-01-14 at 07:47 +, Honnappa Nagarahalli wrote: > > On Sat, 2019-01-05 at 22:47 +, Honnappa Nagarahalli wrote: > > > > On Fri, 2019-01-04 at 19:59 +, Yongseok Koh wrote: > > > > > --- > > > > > > > > > > > > >

Re: [dpdk-dev] [EXT] Default cacheline size for ARM

2019-01-13 Thread Honnappa Nagarahalli
> On Sat, 2019-01-05 at 22:47 +, Honnappa Nagarahalli wrote: > > > On Fri, 2019-01-04 at 19:59 +, Yongseok Koh wrote: > > > > --- > > > > > > > > --- > > > > Hi, > > > > > > > > The cacheline size (RTE_CACHE_LINE_SIZE) for ARM

Re: [dpdk-dev] [EXT] Default cacheline size for ARM

2019-01-05 Thread Jerin Jacob Kollanukkaran
On Sat, 2019-01-05 at 22:47 +, Honnappa Nagarahalli wrote: > > On Fri, 2019-01-04 at 19:59 +, Yongseok Koh wrote: > > > --- > > > > > > --- > > > Hi, > > > > > > The cacheline size (RTE_CACHE_LINE_SIZE) for ARM CPUs is set to

Re: [dpdk-dev] [EXT] Default cacheline size for ARM

2019-01-05 Thread Honnappa Nagarahalli
> > On Fri, 2019-01-04 at 19:59 +, Yongseok Koh wrote: > > --- > > --- > > Hi, > > > > The cacheline size (RTE_CACHE_LINE_SIZE) for ARM CPUs is set to be > > 128B by default. Mellanox's BlueField is an ARM CPU having Cortex-A72 >

Re: [dpdk-dev] [EXT] Default cacheline size for ARM

2019-01-04 Thread Jerin Jacob Kollanukkaran
On Fri, 2019-01-04 at 19:59 +, Yongseok Koh wrote: > --- > --- > Hi, > > The cacheline size (RTE_CACHE_LINE_SIZE) for ARM CPUs is set to be > 128B by > default. Mellanox's BlueField is an ARM CPU having Cortex-A72 and its > CL siz