Snipped
> > >
> > > I recall from the Cache Stashing community call... There is some
> > > ACPI
> > function to
> > > get the (opaque) "location IDs" of various parts in the system, to
> > > be
> > used for setting
> > > the Cache Stashing hints.
> > > Is there only one "ACPI location ID" (I don't
> > > > > > Does the API need to be prepared for L4 cache?
> > > > > > https://www.anandtech.com/show/16924/did-ibm-just-preview-
> the-
> > > future
> > > > > > -
> > > > > of-caches
> > > > > Thank you for the pointer, yes initial patch was considering L4
> > > cache
> > > > > too. But I was not
Snipped
>
>
> > > > > Does the API need to be prepared for L4 cache?
> > > > > https://www.anandtech.com/show/16924/did-ibm-just-preview-the-
> > future
> > > > > -
> > > > of-caches
> > > > Thank you for the pointer, yes initial patch was considering L4
> > cache
> > > > too. But I was not able
> > > > Does the API need to be prepared for L4 cache?
> > > > https://www.anandtech.com/show/16924/did-ibm-just-preview-the-
> future
> > > > -
> > > of-caches
> > > Thank you for the pointer, yes initial patch was considering L4
> cache
> > > too. But I was not able to get hold of system or get s
Snipped
>
> > > Does the API need to be prepared for L4 cache?
> > > https://www.anandtech.com/show/16924/did-ibm-just-preview-the-future
> > > -
> > of-caches
> > Thank you for the pointer, yes initial patch was considering L4 cache
> > too. But I was not able to get hold of system or get someo
> > Does the API need to be prepared for L4 cache?
> > https://www.anandtech.com/show/16924/did-ibm-just-preview-the-future-
> of-caches
> Thank you for the pointer, yes initial patch was considering L4 cache
> too. But I was not able to get hold of system or get someone to test
> this with L4.
> H
Snipped
>
> Does the API need to be prepared for L4 cache?
> https://www.anandtech.com/show/16924/did-ibm-just-preview-the-future-of-caches
Thank you for the pointer, yes initial patch was considering L4 cache too. But
I was not able to get hold of system or get someone to test this with L4.
Hen
On 2024-10-30 16:44, Stephen Hemminger wrote:
On Wed, 30 Oct 2024 11:11:31 +0530
Vipin Varghese wrote:
+ if (topo_cnfg.io) {
+ free(topo_cnfg.io);
+ topo_cnfg.io = NULL;
+ }
No need to check for NULL before calling free.
If you do need to check for N
> From: Vipin Varghese [mailto:vipin.vargh...@amd.com]
> Sent: Wednesday, 30 October 2024 06.42
>
> Introduce topology aware lcore mapping into lcore API.
> With higher core density, more and more cores are categorized
> into various chiplets based on IO (memory and PCIe) and
> Last Level Cache (m
Snipped
>
> > +struct topology_config {
> > +#ifdef RTE_EAL_HWLOC_TOPOLOGY_PROBE
> > + hwloc_topology_t topology;
> > +#endif
> > +
> > + /* domain count */
> > + uint16_t l1_count;
> > + uint16_t l2_count;
> > + uint8_t l3_count;
> > + uint8_t io_count;
> > +
> > + /*
Snipped
>
> > + /* domain count */
> > + uint16_t l1_count;
> > + uint16_t l2_count;
> > + uint8_t l3_count;
> > + uint8_t io_count;
>
> Make them all uint16_t, the space is there already.
Thank you, fixing this in v4
Snipped
>
> On Wed, 30 Oct 2024 11:11:31 +0530
> Vipin Varghese wrote:
>
> > + if (topo_cnfg.io) {
> > + free(topo_cnfg.io);
> > + topo_cnfg.io = NULL;
> > + }
>
> No need to check for NULL before calling free.
Thank you Stepehen on this, the reason why we speci
Snipped
>
> On Wed, 30 Oct 2024 11:11:31 +0530
> Vipin Varghese wrote:
>
> > topo_cnfg.l3[j] = (struct core_domain_mapping *)
> > + malloc(sizeof(struct
> > core_domain_mapping));
>
> Minor nit, no need to cast return value from malloc
Introduce topology aware lcore mapping into lcore API.
With higher core density, more and more cores are categorized
into various chiplets based on IO (memory and PCIe) and
Last Level Cache (mainly L3).
Using hwloc library, the dpdk available lcores can be grouped
into various groups nameley L1, L
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