On Thu, 9 Nov 2023 11:45:46 +0100
Morten Brørup wrote:
> +TO: Andrew, mempool maintainer
>
> > From: Morten Brørup [mailto:m...@smartsharesystems.com]
> > Sent: Monday, 6 November 2023 11.29
> >
> > > From: Bruce Richardson [mailto:bruce.richard...@intel.com]
> > > Sent: Monday, 6 November 20
+TO: Andrew, mempool maintainer
> From: Morten Brørup [mailto:m...@smartsharesystems.com]
> Sent: Monday, 6 November 2023 11.29
>
> > From: Bruce Richardson [mailto:bruce.richard...@intel.com]
> > Sent: Monday, 6 November 2023 10.45
> >
> > On Sat, Nov 04, 2023 at 06:29:40PM +0100, Morten Brørup
> From: Bruce Richardson [mailto:bruce.richard...@intel.com]
> Sent: Monday, 6 November 2023 10.45
>
> On Sat, Nov 04, 2023 at 06:29:40PM +0100, Morten Brørup wrote:
> > I tried a little experiment, which gave a 25 % improvement in mempool
> > perf tests for long bursts (n_get_bulk=32 n_put_bulk=3
On Sat, Nov 04, 2023 at 06:29:40PM +0100, Morten Brørup wrote:
> I tried a little experiment, which gave a 25 % improvement in mempool
> perf tests for long bursts (n_get_bulk=32 n_put_bulk=32 n_keep=512
> constant_n=0) on a Xeon E5-2620 v4 based system.
>
> This is the concept:
>
> If all access
I tried a little experiment, which gave a 25 % improvement in mempool
perf tests for long bursts (n_get_bulk=32 n_put_bulk=32 n_keep=512
constant_n=0) on a Xeon E5-2620 v4 based system.
This is the concept:
If all accesses to the mempool driver goes through the mempool cache,
we can ensure that t
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