[PATCH v2 3/3] riscv: override machine_args only when default

From: sunyuechi Support using -Dcpu_instruction_set=rv64gcv to enable V extension. Signed-off-by: sunyuechi --- config/riscv/meson.build | 2 ++ 1 file changed, 2 insertions(+) diff --git a/config/riscv/meson.build b/config/riscv/meson.build index e3694cf2e6..1036a86d05 100644 --- a/config/ri

[PATCH v2 3/3] riscv: override machine_args only when default

From: sunyuechi Support using -Dcpu_instruction_set=rv64gcv to enable V extension. Signed-off-by: sunyuechi --- config/riscv/meson.build | 2 ++ 1 file changed, 2 insertions(+) diff --git a/config/riscv/meson.build b/config/riscv/meson.build index e3694cf2e6..1036a86d05 100644 --- a/config/ri

[PATCH v2 3/3] riscv: override machine_args only when default

From: sunyuechi Support using -Dcpu_instruction_set=rv64gcv to enable V extension. Signed-off-by: sunyuechi --- config/riscv/meson.build | 2 ++ 1 file changed, 2 insertions(+) diff --git a/config/riscv/meson.build b/config/riscv/meson.build index e3694cf2e6..1036a86d05 100644 --- a/config/ri