On Tue, Jun 18, 2024 at 01:12:13PM +0100, Bruce Richardson wrote:
> On Mon, May 27, 2024 at 07:19:21PM +0300, Igor Gutorov wrote:
> > According to the Intel X710/XXV710/XL710 Datasheet, the maximum receive
> > queue descriptor length is 0x1FE0 (8160 in base 10). This is specified
> > as QLEN in tab
On Mon, May 27, 2024 at 07:19:21PM +0300, Igor Gutorov wrote:
> According to the Intel X710/XXV710/XL710 Datasheet, the maximum receive
> queue descriptor length is 0x1FE0 (8160 in base 10). This is specified
> as QLEN in table 8-12, page 1083.
>
> I've tested this change with an XXV710 NIC and it
> From: Igor Gutorov [mailto:igooto...@gmail.com]
> Sent: Wednesday, 5 June 2024 12.47
>
> On Mon, Jun 3, 2024 at 1:41 PM Igor Gutorov wrote:
> >
> > On Mon, May 27, 2024 at 7:20 PM Igor Gutorov wrote:
> > >
> > > According to the Intel X710/XXV710/XL710 Datasheet, the maximum receive
> > > queu
On Mon, Jun 3, 2024 at 1:41 PM Igor Gutorov wrote:
>
> On Mon, May 27, 2024 at 7:20 PM Igor Gutorov wrote:
> >
> > According to the Intel X710/XXV710/XL710 Datasheet, the maximum receive
> > queue descriptor length is 0x1FE0 (8160 in base 10). This is specified
> > as QLEN in table 8-12, page 108
On Mon, May 27, 2024 at 7:20 PM Igor Gutorov wrote:
>
> According to the Intel X710/XXV710/XL710 Datasheet, the maximum receive
> queue descriptor length is 0x1FE0 (8160 in base 10). This is specified
> as QLEN in table 8-12, page 1083.
>
> I've tested this change with an XXV710 NIC and it has pos
According to the Intel X710/XXV710/XL710 Datasheet, the maximum receive
queue descriptor length is 0x1FE0 (8160 in base 10). This is specified
as QLEN in table 8-12, page 1083.
I've tested this change with an XXV710 NIC and it has positive effect on
performance under high load scenarios. Where pre
6 matches
Mail list logo
