11/10/2023 18:55, Morten Brørup:
> > From: Thomas Monjalon [mailto:tho...@monjalon.net]
> > Sent: Wednesday, 11 October 2023 18.08
> >
> > TLS is an alternative solution proposed by Stephen.
> > What do you think?
>
> I think we went down a rabbit hole - which I admit to enjoy. :-)
There is no r
On 2023-10-11 18:07, Thomas Monjalon wrote:
TLS is an alternative solution proposed by Stephen.
What do you think?
I've expressed my views on this topic in two threads already.
I'm happy to continue that discussion, but I would suggest it would be
under the banner of "what should the standar
> From: Thomas Monjalon [mailto:tho...@monjalon.net]
> Sent: Wednesday, 11 October 2023 18.08
>
> TLS is an alternative solution proposed by Stephen.
> What do you think?
I think we went down a rabbit hole - which I admit to enjoy. :-)
My simple patch should be applied, with the description impr
TLS is an alternative solution proposed by Stephen.
What do you think?
06/09/2023 18:25, Stephen Hemminger:
> On Mon, 4 Sep 2023 13:57:19 +0200
> Mattias Rönnblom wrote:
>
> > On 2023-09-04 11:26, Morten Brørup wrote:
> > > The per-lcore random state is frequently updated by their individual
>
PING for review.
Stephen, the discussion took quite a few turns, but didn't seem to reach a
better solution. If you don't object to this simple patch, could you please
also ack/review it, so it can be applied.
> From: Mattias Rönnblom [mailto:hof...@lysator.liu.se]
> Sent: Monday, 4 September 2
On Mon, 4 Sep 2023 13:57:19 +0200
Mattias Rönnblom wrote:
> On 2023-09-04 11:26, Morten Brørup wrote:
> > The per-lcore random state is frequently updated by their individual
> > lcores, so add a cache guard to prevent CPU cache thrashing.
> >
>
> "to prevent false sharing in case the CPU emp
On 2023-09-04 11:26, Morten Brørup wrote:
The per-lcore random state is frequently updated by their individual
lcores, so add a cache guard to prevent CPU cache thrashing.
"to prevent false sharing in case the CPU employs a next-N-lines (or
similar) hardware prefetcher"
In my world, cache t
The per-lcore random state is frequently updated by their individual
lcores, so add a cache guard to prevent CPU cache thrashing.
Depends-on: series-29415 ("clarify purpose of empty cache lines")
Signed-off-by: Morten Brørup
---
lib/eal/common/rte_random.c | 1 +
1 file changed, 1 insertion(+)
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