> Sent: Monday, December 13, 2021 7:06 PM
> > > > To: jer...@marvell.com; Jan Viktorin ; Ruifeng
> > > > Wang ; Bruce Richardson
> > > >
> > > > Cc: dev@dpdk.org; Pavan Nikhilesh
> > > > Subject: [PATCH] config/cn10k: align mempool
.@marvell.com; Jan Viktorin ; Ruifeng
> > > Wang ; Bruce Richardson
> > >
> > > Cc: dev@dpdk.org; Pavan Nikhilesh
> > > Subject: [PATCH] config/cn10k: align mempool elements to 128 bytes
> > >
> > > From: Pavan Nikhilesh
> > >
> > &
> > Cc: dev@dpdk.org; Pavan Nikhilesh
> > Subject: [PATCH] config/cn10k: align mempool elements to 128 bytes
> >
> > From: Pavan Nikhilesh
> >
> > Mempool elements are by default aligned to CACHELINE_SIZE.
> > In CN10K cacheline size is 64B but the RoC requires buf
On 13/12/2021 11:06, pbhagavat...@marvell.com wrote:
From: Pavan Nikhilesh
Mempool elements are by default aligned to CACHELINE_SIZE.
In CN10K cacheline size is 64B but the RoC requires buffers to be
aligned to 128B.
It would be good to say what the implication is in the commit message.
Set
> -Original Message-
> From: pbhagavat...@marvell.com
> Sent: Monday, December 13, 2021 7:06 PM
> To: jer...@marvell.com; Jan Viktorin ; Ruifeng
> Wang ; Bruce Richardson
>
> Cc: dev@dpdk.org; Pavan Nikhilesh
> Subject: [PATCH] config/cn10k: align mempool element
From: Pavan Nikhilesh
Mempool elements are by default aligned to CACHELINE_SIZE.
In CN10K cacheline size is 64B but the RoC requires buffers to be
aligned to 128B.
Set RTE_MEMPOOL_ALIGN to 128 to force mempool buffers to be aligned
128 bytes.
Signed-off-by: Pavan Nikhilesh
---
config/arm/meson
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