> From: Thomas Monjalon [mailto:tho...@monjalon.net]
> Sent: Thursday, 12 October 2023 01.44
>
> 04/09/2023 10:43, Morten Brørup:
> > /** Force minimum cache line alignment. */
> > #define __rte_cache_min_aligned __rte_aligned(RTE_CACHE_LINE_MIN_SIZE)
> >
> > +#define _RTE_CACHE_GUARD_HELPER2(un
Morten Brørup would like to recall the message, "[PATCH] clarify purpose of
empty cache lines".
> From: Thomas Monjalon [mailto:tho...@monjalon.net]
> Sent: Thursday, 12 October 2023 01.44
>
> 04/09/2023 10:43, Morten Brørup:
> > /** Force minimum cache line alignment. */
> > #define __rte_cache_min_aligned __rte_aligned(RTE_CACHE_LINE_MIN_SIZE)
> >
> > +#define _RTE_CACHE_GUARD_HELPER2(un
04/09/2023 10:43, Morten Brørup:
> /** Force minimum cache line alignment. */
> #define __rte_cache_min_aligned __rte_aligned(RTE_CACHE_LINE_MIN_SIZE)
>
> +#define _RTE_CACHE_GUARD_HELPER2(unique) \
> + char cache_guard_ ## unique[RTE_CACHE_LINE_SIZE *
> RTE_CACHE_GUARD_LINES] \
>
04/09/2023 11:12, Bruce Richardson:
> On Mon, Sep 04, 2023 at 10:43:49AM +0200, Morten Brørup wrote:
> > This patch introduces the generic RTE_CACHE_GUARD macro into the EAL, and
> > replaces vaguely described empty cache lines in the rte_ring structure
> > with this macro.
> >
> > Although the im
> From: Morten Brørup [mailto:m...@smartsharesystems.com]
> Sent: Monday, 4 September 2023 10.44
>
> This patch introduces the generic RTE_CACHE_GUARD macro into the EAL, and
> replaces vaguely described empty cache lines in the rte_ring structure
> with this macro.
>
> Although the implementatio
On Mon, Sep 04, 2023 at 10:43:49AM +0200, Morten Brørup wrote:
> This patch introduces the generic RTE_CACHE_GUARD macro into the EAL, and
> replaces vaguely described empty cache lines in the rte_ring structure
> with this macro.
>
> Although the implementation of the rte_ring structure assumes t
This patch introduces the generic RTE_CACHE_GUARD macro into the EAL, and
replaces vaguely described empty cache lines in the rte_ring structure
with this macro.
Although the implementation of the rte_ring structure assumes that the
hardware speculatively prefetches 1 cache line, this number can b
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