Re: [PATCH] bus/pci: check if 5-level paging is enabled when testing IOMMU address width

2023-06-09 Thread Stephen Hemminger
This patch is no long relevant since the current DPDK code no longer depends on VA width. It should be rejected.

Re: [dpdk-dev] [PATCH] bus/pci: check if 5-level paging is enabled when testing IOMMU address width

2018-08-10 Thread Burakov, Anatoly
On 10-Aug-18 9:35 AM, Drocula wrote: First, thanks for your suggestions. When using the MAP_FIXED flag, mmap will return an MMAP_FAILED if 0xf0 is not available. In this case, I want mmap to return an address near 0xf0. I will submit v2. How can we be sure there's not

Re: [dpdk-dev] [PATCH] bus/pci: check if 5-level paging is enabled when testing IOMMU address width

2018-08-10 Thread Drocula
First, thanks for your suggestions. When using the MAP_FIXED flag, mmap will return an MMAP_FAILED if 0xf0 is not available. In this case, I want mmap to return an address near 0xf0. I will submit v2. On Fri, Aug 10, 2018, 01:03 Stephen Hemminger wrote: > Thanks for th

Re: [dpdk-dev] [PATCH] bus/pci: check if 5-level paging is enabled when testing IOMMU address width

2018-08-10 Thread Drocula
Thanks, will refine in v2. On Thu, Aug 9, 2018, 18:49 Burakov, Anatoly wrote: > On 05-Aug-18 7:41 PM, Drocula wrote: > > The kernel version 4.14 released with the support of 5-level paging. > > When PML5 enabled, user-space virtual addresses uses up to 56 bits. > > see kernel's Documentation/x86

Re: [dpdk-dev] [PATCH] bus/pci: check if 5-level paging is enabled when testing IOMMU address width

2018-08-09 Thread Stephen Hemminger
Thanks for the patch, there are some minor style/cleanups that could be done. > #if defined(RTE_ARCH_X86) Isn't this going to apply to 64 bit only? > +/* > + * Try to detect whether the system uses 5-level page table. > + */ > +static bool > +system_uses_PML5(void) > +{ > + void *page_4k,

Re: [dpdk-dev] [PATCH] bus/pci: check if 5-level paging is enabled when testing IOMMU address width

2018-08-09 Thread Burakov, Anatoly
On 05-Aug-18 7:41 PM, Drocula wrote: The kernel version 4.14 released with the support of 5-level paging. When PML5 enabled, user-space virtual addresses uses up to 56 bits. see kernel's Documentation/x86/x86_64/mm.txt. Signed-off-by: Drocula --- drivers/bus/pci/linux/pci.c | 27 +

[dpdk-dev] [PATCH] bus/pci: check if 5-level paging is enabled when testing IOMMU address width

2018-08-05 Thread Drocula
The kernel version 4.14 released with the support of 5-level paging. When PML5 enabled, user-space virtual addresses uses up to 56 bits. see kernel's Documentation/x86/x86_64/mm.txt. Signed-off-by: Drocula --- drivers/bus/pci/linux/pci.c | 27 +-- 1 file changed, 25 inser