From: Shweta Choudaha
Hello,
This patch fixes an issue where GO_LINKD bit is incorrectly set/cleared even
when PHY reset is blocked
and is updated to fix the checkpatch warning
Fixes f34dec0b41 ("igb: force phy power up/down")
Thanks,
Shweta
Shweta Choudaha (1):
net/e1000:
From: Shweta Choudaha
When PHY reset is blocked as is the case when BMC is connected via NC-SI
do not set GO_LINKD bit in PHY power management register in dev_stop as
this will disconnect the PHY. Also, in dev_close clear the GO_LINKD
bit only if PHY reset is not blocked
Fixes: 3af34dec0b41
From: Shweta Choudaha
When PHY reset is blocked as is the case when BMC is connected via NC-SI
do not set GO_LINKD bit in PHY power management register in dev_stop as
this will disconnect the PHY. Also, in dev_close clear the GO_LINKD
bit only if PHY reset is not blocked
Fixes: 3af34dec0b41
From: Shweta Choudaha
Hello,
This fixes an issue where GO_LINKD bit is incorrectly set/cleared even when
PHY reset is blocked.
Fixes f34dec0b41 ("igb: force phy power up/down")
Thanks,
Shweta
Shweta Choudaha (1):
net/e1000: set/clear GO_LINKD bit only if PHY reset is not blocked
Hi Helin, Qi, Wenzhuo,
Any update for this patch.
Anything else needed or can this be merged ?
Thanks,
Shweta
On Thu, Apr 26, 2018 at 11:56 AM, Ferruh Yigit
wrote:
> On 4/26/2018 11:20 AM, Shweta Choudaha wrote:
> > Hi Ferruh/ Helin,
> >
> > Anything else
Hi Ferruh/ Helin,
Anything else needed for this patch
http://dpdk.org/dev/patchwork/patch/37802/
Or can this be now acked - Have addressed all comments so far.
Thanks,
Shweta
On Tue, Apr 10, 2018 at 4:58 PM, Shweta Choudaha
wrote:
> Thanks for the review.
> I have sent an updated
Hi Qi,
I have addressed your comments and sent a v4 patchset.
Thanks,
Shweta
On Fri, Apr 13, 2018 at 3:37 AM, Zhang, Qi Z wrote:
> Hi Choudaha:
>
> > -Original Message-
> > From: dev [mailto:dev-boun...@dpdk.org] On Behalf Of Shweta Choudaha
> > Sent: Wedn
From: Shweta Choudaha
Add ixgbe MDIO lock/unlock and access APIs to read and write registers
using specific device address. This provides MDIO access to any devices
that are not associated with the autoprobed PHY.Export these APIs via
the map file
Signed-off-by: Shweta Choudaha
Reviewed-by
Thanks for the review.
I have sent an updated patch.
regards,
Shweta
On Wed, Apr 4, 2018 at 3:15 AM, Lu, Wenzhuo wrote:
> Hi Shweta,
>
> > -Original Message-
> > From: Shweta Choudaha [mailto:shweta.choud...@gmail.com]
> > Sent: Thursday, March 22, 2018 1:36
From: Shweta Choudaha
Add ixgbe MDIO lock/unlock and access APIs to read and write registers
using specific device address. This provides MDIO access to any devices
that are not associated with the autoprobed PHY.Export these APIs via
the map file
Signed-off-by: Shweta Choudaha
Reviewed-by
> > On 4/4/2018 3:25 AM, Lu, Wenzhuo wrote:
> > > Hi Shweta,
> > >
> > >
> > >> -Original Message-
> > >> From: dev [mailto:dev-boun...@dpdk.org] On Behalf Of Shweta Choudaha
> > >> Sent: Friday, February 23, 2018 7:5
From: Shweta Choudaha
Add ixgbe API to enable SBP bit in FCTRL register
to allow receiving packets that may otherwise be
considered length errors by ixgbe and dropped
Signed-off-by: Shweta Choudaha
Reviewed-by: Chas Williams
Reviewed-by: Luca Boccassi
---
drivers/net/ixgbe/rte_pmd_ixgbe.c
From: Shweta Choudaha
Add ixgbe MDIO lock/unlock and access APIs to read and write registers
using specific device address. This provides MDIO access to any devices
that are not associated with the autoprobed PHY.Export these APIs via
the map file
Signed-off-by: Shweta Choudaha
Reviewed-by
From: Shweta Choudaha
Hi,
I am updating this patch to separate MDIO access APIs and MDIO
locking APIs. This is done so that calling function can batch MDIO
access at a higher level as taking MDIO lock can be expensive.
Thanks,
Shweta
Shweta Choudaha (1):
net/ixgbe: Add access and
From: Shweta Choudaha
Add ixgbe MDIO access APIs to read and write registers using specific
device address. This provides MDIO access to any devices that are
not associated with the autoprobed PHY.Export these APIs via the map file
Signed-off-by: Shweta Choudaha
Reviewed-by: Chas Williams
more generically for all adapters, the other approach
can be to allocate a bit in ‘struct rte_eth_rxmode’ to disable
rx_length_checking on the port. Please let me know if that is preferred or
if more info is needed
Thanks,
Shweta
On Fri, Feb 23, 2018 at 11:59 AM, Shweta Choudaha wrote:
> F
From: Shweta Choudaha
Add ixgbe API to enable SBP bit in FCTRL register
to allow receiving packets that may otherwise be
considered length errors by ixgbe and dropped
Signed-off-by: Shweta Choudaha
Reviewed-by: Chas Williams
Reviewed-by: Luca Boccassi
---
drivers/net/ixgbe/rte_pmd_ixgbe.c
From: Shweta Choudaha
--
2.11.0
th this patch set.
> 1. test cases in testpmd.
> 2. documentation in release notes, testpmd doc, and others if needed.
>
> Regards,
> Helin
>
> > -Original Message-
> > From: dev [mailto:dev-boun...@dpdk.org] On Behalf Of Shweta Choudaha
> > Sent: Monda
From: Shweta Choudaha
Initialize and implement MDIO read/write functions
for backplane port (IXGBE_DEV_ID_X550EM_A_KR_L) to
enable read/write registers via MDIO
Signed-off-by: Shweta Choudaha
Reviewed-by: Chas Williams
Reviewed-by: Luca Boccassi
---
drivers/net/ixgbe/base/ixgbe_x550.c | 54
From: Shweta Choudaha
Add ixgbe MDIO access APIs to read and write PHY registers
when being used as a backplane port. Export these APIs via the map file
Signed-off-by: Shweta Choudaha
Reviewed-by: Chas Williams
Reviewed-by: Luca Boccassi
---
drivers/net/ixgbe/rte_pmd_ixgbe.c | 53
for review.
Thanks,
Shweta
On Wed, Jan 10, 2018 at 3:17 AM, Zhang, Helin wrote:
>
>
> > -Original Message-
> > From: dev [mailto:dev-boun...@dpdk.org] On Behalf Of Shweta Choudaha
> > Sent: Monday, November 6, 2017 10:25 PM
> > To: dev@dpdk.org
> > Cc:
From: Shweta Choudaha
Initialize MDIO read/write functions for backplan port
(IXGBE_DEV_ID_X550EM_A_KR_L) to enable read/write
registers via MDIO
Signed-off-by: Shweta Choudaha
Reviewed-by: Chas Williams
Reviewed-by: Luca Boccassi
---
drivers/net/ixgbe/base/ixgbe_x550.c | 1 +
1 file
From: Shweta Choudaha
Add ixgbe MDIO access APIs to read and write PHY registers when
being used as a backplane port. Export these APIs via the map file
Signed-off-by: Shweta Choudaha
Reviewed-by: Chas Williams
Reviewed-by: Luca Boccassi
---
drivers/net/ixgbe/rte_pmd_ixgbe.c | 53
Add ixgbe MDIO access APIs to read and write PHY registers when
being used as a backplane port. Export these APIs via the map file
Signed-off-by: Shweta Choudaha
Reviewed-by: Chas Williams
Reviewed-by: Luca Boccassi
---
drivers/net/ixgbe/rte_pmd_ixgbe.c | 53
Initialize MDIO read/write functions for backplan port
(IXGBE_DEV_ID_X550EM_A_KR_L) to enable read/write
registers via MDIO
Signed-off-by: Shweta Choudaha
Reviewed-by: Chas Williams
Reviewed-by: Luca Boccassi
---
drivers/net/ixgbe/base/ixgbe_x550.c | 1 +
1 file changed, 1 insertion(+)
diff
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