Team,
Does setting mtu using rte_eth_dev_set_mtu limit the maximum size of the
packet received on the dpdk port to the configured mtu size?
On an intel machine with ixgbe port, with mtu set to 1500, no rx-offloads
enabled, ixgbe dpdk port is able to receive packets greater than 1500 size
and even
Thanks Stephen.
On Fri, Oct 18, 2024 at 10:13 PM Stephen Hemminger <
step...@networkplumber.org> wrote:
> On Fri, 18 Oct 2024 22:05:24 +0530
> Rajasekhar Pulluru wrote:
>
> > Team,
> > Does setting mtu using rte_eth_dev_set_mtu limit the maximum size of the
> >
Hi Team,
Unable to attach ConnectX-3 mlx4 interfaces(uio_hv_generic) in DPDK.
testpmd application reports below errors. mlx4_ib is loaded. Not sure if I
am missing anything here. Appreciate any help to resolve this.
*EAL: Detected CPU lcores: 8EAL: Detected NUMA node
> Please take a look at the rte_power_monitor() and dpdk-l3fwd-power
> application example to see if it works for you. What platform do you use?
> It is only supported on recent Intel CPUs and ARMs.
>
>
>
> Regards,
>
> Alex
>
>
>
> *From:* Rajasekhar Pullu
Hi Team,
Would like to know if dpdk has a select(fd)/epoll(fd) like mechanism to
wake-up the application (say rx-pthread) asynchronously upon packet
reception without enabling rxq interrupts?
I can't afford to lose a cpu-core polling continuously to check for packets
using rte_eth_rx_burst.And I
kplumber.org> wrote:
> On Wed, 8 Mar 2023 22:54:12 +0530
> Rajasekhar Pulluru wrote:
>
> > No Honnappa.
> >
> > Thanks & Regards,
> > Rajasekhar
> >
> > On Wed, Mar 8, 2023 at 5:49 AM Honnappa Nagarahalli <
> > honnappa.nagaraha...@a
No Honnappa.
Thanks & Regards,
Rajasekhar
On Wed, Mar 8, 2023 at 5:49 AM Honnappa Nagarahalli <
honnappa.nagaraha...@arm.com> wrote:
>
>
> From: Rajasekhar Pulluru
> Sent: Tuesday, March 7, 2023 12:52 PM
> To: dev@dpdk.org
> Subject: ixgbe rxq interrupt not working
7-edge
vfio-msix[1](:02:00.0)
#>>>>> igb port irq counter is non-zero (likely to be rxq), where-as the
same for ixgbe is 0.
Thanks & Regards,
Rajasekhar
On Wed, Mar 8, 2023 at 3:12 AM Stephen Hemminger
wrote:
> On Wed, 8 Mar 2023 00:22:10 +0530
> Rajasekhar Pull
Hi Team,
Bringing-up dpdk-22.07 on an intel machine with 8 ports, 4 of them driven
by igb and the rest of the 4 ports driven by ixgbe.
I am following the below sequence to initialize these ports:
dev_conf.intr_conf.lsc = 1; //Enable link state change interrupt
dev_conf.intr_conf.rxq = 1; //Enabl
ote:
> On Fri, Feb 17, 2023 at 11:30:14AM +0530, Rajasekhar Pulluru wrote:
> >Ok Stephen, thanks for the information, I can try that.
> >One of the problems I see with single Tx Queue mode is that Ixia
> >reports packet drops, though I confirmed with the help of coun
9:56 PM Stephen Hemminger <
step...@networkplumber.org> wrote:
> On Fri, 17 Feb 2023 11:30:14 +0530
> Rajasekhar Pulluru wrote:
>
> > Ok Stephen, thanks for the information, I can try that.
> >
> > One of the problems I see with single Tx Queue mode is that Ixia r
ps in TX.
Is there a mechanism in DPDK to debug this?
Thanks & Regards,
Rajasekhar
On Fri, Feb 17, 2023 at 1:21 AM Stephen Hemminger <
step...@networkplumber.org> wrote:
> On Thu, 16 Feb 2023 23:40:27 +0530
> Rajasekhar Pulluru wrote:
>
> > Hi Team,
> >
> > I
Hi Team,
I am trying to set-up 8 Tx-Queues (but only 1 Rx-Queue) and burst traffic
out of different Tx-Queues from the same cpu core on an ixgbe nic (10G).
Although transmitted packets reach the peer, reading the statistics
indicates only the Tx-q[0] has non-zero packets and bytes count, the rest
Dear Group members,
I have been trying to understand the dpdk code and have got two queries.
1. descriptor rings and packet buffer allocation
Looking at the linux native e1000 kernel driver,
Memory for NIC's tx and rx descriptor rings are allocated using
dma_alloc_coherent.
Memory for rx packet
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