Hi Vamsi,
Could you please tell us more about usecases for this feature?
Thanks!
On 7/10/2025 9:51 AM, Vamsi Krishna wrote:
From: Vamsi Attunuru
Modern DMA hardware supports data transfer between multiple
DMA devices, enabling data communication across isolated domains or
containers. To faci
Acked-by: Vladimir Medvedkin
On 7/8/2025 1:28 PM, David Marchand wrote:
Caught by UBSan:
../lib/hash/rte_thash.c:421:8: runtime error: load of misaligned address
0x0001816c2da3 for type 'uint32_t' (aka 'unsigned int'),
which requires 4 byte alignment
Fixes: 28ebff11c2dc ("hash
Hi Morten,
On 7/7/2025 11:00 PM, Morten Brørup wrote:
*From:*Vladimir Medvedkin [mailto:medvedk...@gmail.com]
*Sent:* Monday, 7 July 2025 22.10
That's not quite correct.
There are 2 valid usecases, that may bring some ambiguity:
1. Some vendors may support mixing dual/single tagged p
Hi Sun,
You did not address my previous comments regarding commit message. You
can put everything you've wrote in this commit as a note and add
meaningful description about what commit generally does, like (please
correct if needed):
"Implement LPM lookupx4 routine for RISC-V architecture us
Acked-by: Vladimir Medvedkin
On 27/03/2025 16:28, Bruce Richardson wrote:
Remove obsolete, and generally not followed, advice in the coding
standards doc, around local variables.
Signed-off-by: Bruce Richardson
---
doc/guides/contributing/coding_style.rst | 4
1 file changed, 4 deleti
Hi all,
Please find answers inline
On 03/06/2025 06:54, Nitin Saxena wrote:
Hi Morten,
Let me take a stab regarding the VRF question.
Please find answers inline
Thanks,
Nitin
On Mon, Jun 2, 2025 at 2:12 PM Morten Brørup wrote:
+TO: Robin Jarry, might have relevant feedback for such a node
to include this idea (v2).
I'm not talking about adopting the FIB approach to the LPM. Instead, I
suggested keeping LPM code consistent and leaving your implementation as
a static inline function. And if you want to have runtime CPU flags
check - you're welcome to do so in the
Hi Sunyuechi,
On 28/05/2025 18:00, u...@foxmail.com wrote:
From: sunyuechi
bpi-f3:
scalar: 5.7 cycles
rvv:2.4 cycles
Maybe runtime detection in LPM should be added for all architectures,
but this commit is only about the RVV part.
Iwouldadviseyouto lookintothe FIBlibrary,ithas
Acked-by: Vladimir Medvedkin
On 24/02/2025 15:26, Bruce Richardson wrote:
Document the additional step necessary to create large VFs for iavf when
using ice kernel driver v1.13.7 or later.
Signed-off-by: Bruce Richardson
---
doc/guides/nics/intel_vf.rst | 5 +
1 file changed, 5 inserti
Acked-by: Vladimir Medvedkin
On 24/02/2025 15:26, Bruce Richardson wrote:
When describing the iavf driver, there was a lot of text in a single
note block which could be clarified by splitting it up into separate
sections and appropriate bulletted lists.
Signed-off-by: Bruce Richardson
---
d
Acked-by: Vladimir Medvedkin
On 24/02/2025 15:26, Bruce Richardson wrote:
The Intel VF section in the NIC guide document had descriptions of the
various drivers at a very deep level of the document hierarchy. Improve
the structure of the doc by giving those per-driver subsections their
own top-
Hi Ankur,
On 15/04/2025 13:10, Ankur Dwivedi wrote:
Adds the process callback function for ip4_lookup_fib node.
Signed-off-by: Ankur Dwivedi
---
lib/node/ip4_lookup_fib.c | 164 ++
1 file changed, 164 insertions(+)
diff --git a/lib/node/ip4_lookup_fib.c
Hi Ankur,
On 15/04/2025 13:10, Ankur Dwivedi wrote:
Adds a lookup FIB node for IP4.
Signed-off-by: Ankur Dwivedi
---
lib/node/ip4_lookup_fib.c | 127 ++
lib/node/meson.build | 3 +-
2 files changed, 129 insertions(+), 1 deletion(-)
create mode 1
Acked-by: Vladimir Medvedkin
On 21/03/2025 17:12, Bruce Richardson wrote:
A number of places in the ixgbe code check for a virtual function, but
these checks were missing the identifier for the E610 VF. Add them into
the conditionals.
Fixes: f678f3dea8fd ("net/ixgbe: fix missing VF PCI ID")
Cc
Acked-by: Vladimir Medvedkin
On 10/03/2025 13:11, Bruce Richardson wrote:
When registering interrupts, there was no check if the registration of
the interrupt succeeded. Add in such a check, and go to fallback path
if the check fails. This prevents errors on FreeBSD due to missed
admin queue me
Acked-by: Vladimir Medvedkin
On 10/03/2025 13:11, Bruce Richardson wrote:
With the fallback interrupt path now enabled on FreeBSD there are
segmentation faults on app exit, due to the alarm interrupt trying to
access invalid pointers. Add checks for null to fix these crashes.
Fixes: cd3b12495
Acked-by: Vladimir Medvedkin
On 11/03/2025 21:40, Matthew Smith wrote:
While adding a vsi for an ice PF, set the ICE_AQ_VSI_SW_FLAG_LOCAL_LB
flag. This will prevent packets from being dropped when using a virtual
MAC address with VRRP.
Also set the ICE_AQ_VSI_SW_FLAG_SRC_PRUNE flag to prevent
Acked-by: Vladimir Medvedkin
On 07/03/2025 16:07, Bruce Richardson wrote:
When creating a common pkt reassembly function for common driver Rx
re-use, not all original copies of the function were removed. Fix this
omission.
Fixes: 82fbc4a4479c ("net/intel: create common packet reassembly")
Sig
Hi Andre,
On 05/03/2025 14:45, Andre Muezerie wrote:
On Wed, Mar 05, 2025 at 10:08:33AM +, Bruce Richardson wrote:
On Wed, Dec 18, 2024 at 07:21:26AM -0800, Andre Muezerie wrote:
Test lpm6_perf_autotest was hitting a stack overflow on Windows
with both MSVC and Clang.
The fix is to move s
Acked-by: Vladimir Medvedkin
On 04/01/2025 22:09, Andre Muezerie wrote:
Removed a few includes which were not needed and included
rte_os_shim.h to handle strtok_r which does not exist on
Windows with that exact name.
Signed-off-by: Andre Muezerie
---
app/test-fib/main.c | 8 ++--
Acked-by: Vladimir Medvedkin
On 21/02/2025 08:25, Mingjin Ye wrote:
The pf has enabled the ACL filter, so uninit is no longer limited
to the DCF.
Fixes: a9d612291c2d ("net/ice: support IPv4 fragments in ACL filters")
Signed-off-by: Mingjin Ye
---
drivers/net/intel/ice/ice_acl_filter.c | 48
Acked-by: Vladimir Medvedkin
On 17/02/2025 13:54, Anatoly Burakov wrote:
Currently, the architecture of IXGBE base driver is such that it uses
function pointers internally. These are not guaranteed to be valid in
secondary processes, which can lead to crashes. This patch prevents IXGBE
ethdev d
Hi Bruce,
On 30/01/2025 17:54, Bruce Richardson wrote:
On Thu, Jan 30, 2025 at 04:14:42PM +, Vladimir Medvedkin wrote:
Currently ICE PMD uses group attribute to select the appropriate HW engine
to offload the flow. This behavior violates the rte_flow API, existing
documentation/examples, an
Acked-by: Vladimir Medvedkin
On 28/11/2024 01:53, Andre Muezerie wrote:
MSVC issues the warnings below:
1) ../lib/hash/rte_thash_gf2_poly_math.c(128): warning C4334: '<<':
result of 32-bit shift implicitly converted to 64 bits
(was 64-bit shift intended?)
The code would be better of
On 13/12/2024 14:33, Bruce Richardson wrote:
The iavf driver only contains a single Tx prepare function, so when
selecting the Tx path, there is no need to reset and reassign the
function pointer in the ethdev structure. This fixes an issue where the
pointer was reset to NULL, but never assigned
Hi,
I think using rte_malloc(rte_calloc) here would be a better choice because:
- As Andre mentioned allocation happens outside of the performance
measurement section
- Due to relatively large size of the memory allocated for
ip_batch/next_hops some CPUs may experience TLB cache pressure, wh
Hi Andre,
On 13/12/2024 02:39, Andre Muezerie wrote:
Test lpm6_perf_autotest was hitting a stack overflow on Windows
with both MSVC and Clang.
The fix is to move some of the data from the stack to the heap.
Signed-off-by: Andre Muezerie
---
app/test/test_lpm6_perf.c | 11 +--
1 fil
Robin Jarry
Sent: Friday, November 22, 2024 4:15 PM
To: Vladimir Medvedkin ; Stephen Hemminger
Cc: Morten Brørup ; Medvedkin, Vladimir
; dev@dpdk.org; Richardson, Bruce
; Marchand, David ;
Thomas Monjalon ; Konstantin Ananyev
Subject: Re: rte_fib network order bug
Vladimir Medvedkin, Nov 17
Hi Bruce,
On 02/12/2024 11:24, Bruce Richardson wrote:
Merge in additional fields used by the ixgbe driver and then convert it
over to using the common Tx queue structure.
Signed-off-by: Bruce Richardson
---
drivers/net/_common_intel/tx.h| 14 +++-
drivers/net/ixgbe/ixgbe_eth
Hi Andre,
On 20/11/2024 03:13, Andre Muezerie wrote:
From: Konstantin Ananyev
1) ./lib/hash/rte_thash.c:774:9
: warning: ISO C90 forbids variable length array ‘tmp_tuple’
From my understanding, tuple size here should never exceed
sizeof(union rte_thash_tuple), so it should be safe to rep
Hi Andre,
On 20/11/2024 03:13, Andre Muezerie wrote:
MSVC does not support VLAs, replace VLAs with standard C arrays.
Signed-off-by: Andre Muezerie
---
lib/hash/rte_thash_gf2_poly_math.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/lib/hash/rte_thash_gf2_poly_ma
Acked-by: Vladimir Medvedkin
On 20/11/2024 03:13, Andre Muezerie wrote:
From: Konstantin Ananyev
1) ./lib/hash/rte_cuckoo_hash.c:2362:9
: warning: ISO C90 forbids variable length array ‘positions’
2) ../lib/hash/rte_cuckoo_hash.c:2478:9
: warning: ISO C90 forbids variable length arr
o byteswap on the fast path.
Why do you think this would discourage users?
-Original Message-
From: Robin Jarry
Sent: Wednesday, November 13, 2024 1:27 PM
To: Medvedkin, Vladimir ; dev@dpdk.org
Subject: Re: rte_fib network order bug
Medvedkin, Vladimir, Nov 13, 2024 at 11:42:
> Hi
Hi Robin,
It should not. Here is documentation says regarding this flag:
/** If set, fib lookup is expecting IPv4 address in network byte order */
#define RTE_FIB_F_NETWORK_ORDER 1
As stated above lookups will be performed while expecting addresses to
be in BE byte order. Control plane API
Acked-by: Vladimir Medvedkin
On 11/11/2024 16:42, Bruce Richardson wrote:
In the Tx prep function, the metadata checks were only checking the
packet length and ignoring the data length. For single-buffer packets we
can quickly check that the data length is the packet length.
Fixes: 19ee91c6bd9
Hi David,
On 07/11/2024 13:00, David Marchand wrote:
On Wed, Oct 16, 2024 at 8:42 PM Vladimir Medvedkin
wrote:
@@ -445,7 +454,7 @@ test_invalid_rcu(void)
rcu_cfg.v = qsv2;
rcu_cfg.mode = RTE_FIB_QSBR_MODE_SYNC;
status = rte_fib_rcu_qsbr_add(fib, &rcu_cfg);
- RT
Acked-by: Vladimir Medvedkin
On 29/10/2024 17:01, Bruce Richardson wrote:
Increase the flexibility of the Tx scheduler hierarchy support in the
driver. If the HW/firmware allows it, allow creating up to 2k child
nodes per scheduler node. Also expand the number of supported layers to
the max ava
Acked-by: Vladimir Medvedkin
On 29/10/2024 17:01, Bruce Richardson wrote:
The DDP package file being loaded at init time may contain an
alternative Tx Scheduler topology in it. Add driver option to load this
topology at init time.
Signed-off-by: Bruce Richardson
---
doc/guides/nics/ice.rst
Acked-by: Vladimir Medvedkin
On 23/10/2024 17:55, Bruce Richardson wrote:
In order to help with backward compatibility for applications, which may
expect the ice driver tx scheduler (accessed via tm apis) to only have 3
layers, add in a devarg to allow the user to explicitly limit the
number of
Acked-by: Vladimir Medvedkin
On 23/10/2024 17:55, Bruce Richardson wrote:
The rte_tm topology commit requires the port to be stopped on apply.
Rather than just returning an error when the port is already started, we
can stop the port, apply the topology to it and then restart it.
Signed-off-by
Hi Bruce,
On 23/10/2024 17:55, Bruce Richardson wrote:
Increase the flexibility of the Tx scheduler hierarchy support in the
driver. If the HW/firmware allows it, allow creating up to 2k child
nodes per scheduler node. Also expand the number of supported layers to
the max available, rather than
Acked-by: Vladimir Medvedkin
On 23/10/2024 17:55, Bruce Richardson wrote:
The function "ice_alloc_lan_q_ctx" will be needed by the driver code, so
make it non-static.
Signed-off-by: Bruce Richardson
---
drivers/net/ice/base/ice_sched.c | 2 +-
drivers/net/ice/base/ice_sched.h | 3 +++
2 f
Hi Bruce,
On 23/10/2024 17:55, Bruce Richardson wrote:
The DDP package file being loaded at init time may contain an
alternative Tx Scheduler topology in it. Add driver option to load this
topology at init time.
Signed-off-by: Bruce Richardson
---
doc/guides/nics/ice.rst| 15 +
Hi Stephen,
On 17/10/2024 04:23, Stephen Hemminger wrote:
On Wed, 16 Oct 2024 17:28:17 +0100
"Medvedkin, Vladimir" wrote:
Hi Stephen,
On 15/10/2024 23:29, Stephen Hemminger wrote:
On Fri, 11 Oct 2024 18:17:00 +
Vladimir Medvedkin wrote:
+
+uint32_t
+rte_thash_get
On 16/10/2024 18:07, Stephen Hemminger wrote:
On Wed, 16 Oct 2024 16:48:12 +0100
"Medvedkin, Vladimir" wrote:
Hi Stephen,
Thanks for introducing this hash function.
I have just a few nits:
On 01/08/2024 16:31, Stephen Hemminger wrote:
The existing hash functions in DP
Hi Stephen,
On 15/10/2024 23:29, Stephen Hemminger wrote:
On Fri, 11 Oct 2024 18:17:00 +
Vladimir Medvedkin wrote:
+
+uint32_t
+rte_thash_get_rand_poly(uint32_t poly_degree)
+{
+ uint32_t ret_poly;
+
+ if (poly_degree > 32)
+ return 0;
+
+ do
+
Hi Stephen,
On 16/10/2024 06:29, Stephen Hemminger wrote:
On Tue, 15 Oct 2024 17:11:43 +
Vladimir Medvedkin wrote:
Fixes the behavior of the rte_fib_rcu_qsbr_add() function regarding its
return value to align with the existing rte_fib API.
Fixes: 96c3d06a3547 ("fib: implement RCU rule re
Hi Stephen,
Thanks for introducing this hash function.
I have just a few nits:
On 01/08/2024 16:31, Stephen Hemminger wrote:
The existing hash functions in DPDK are not cryptographically
secure and can be subject to carefully crafted packets causing
DoS attack.
Currently in DPDK we have 3 hash
Hi Bruce,
Series-acked-by: Vladimir Medvedkin
On 14/10/2024 12:02, Bruce Richardson wrote:
A number of small fixes and other changes to enable Tx scheduler
enhancements to our DPDK driver have been added to the base code.
Upstream these changes for 24.11 RC2. Most have previously been
submitte
Hi Stephen,
Thanks for the review.
No particular reason, will change it to uint32_t in v2.
On 09/09/2024 01:11, Stephen Hemminger wrote:
On Fri, 6 Sep 2024 16:53:16 +
Vladimir Medvedkin wrote:
+struct divisors {
+ int n; /* number of divisors */
+ int div_arr[MAX_DIVISORS];
Hi Stephen,
Thanks for the review, I'll address your comments in v3
On 08/10/2024 19:28, Stephen Hemminger wrote:
On Tue, 8 Oct 2024 17:55:23 +
Vladimir Medvedkin wrote:
+ if ((tbl8_idx == -ENOSPC) && dp->dq != NULL) {
Better to either drop the parenthesis here, or put it on both
Hi David,
On 09/10/2024 11:56, David Marchand wrote:
On Wed, Oct 9, 2024 at 11:51 AM David Marchand
wrote:
Hi Vladimir,
On Tue, Oct 8, 2024 at 7:16 PM Vladimir Medvedkin
wrote:
diff --git a/lib/fib/dir24_8_avx512.c b/lib/fib/dir24_8_avx512.c
index 43dba28cfb..edd802abe4 100644
--- a/lib/fib
Acked-by: Vladimir Medvedkin
On 04/09/2024 14:57, Bruce Richardson wrote:
To simplify building 32-bit binaries on 64-bit system, we can supply a
cross-compilation file which provides the relevant compiler flags and
settings needed - '-m32' compile/link flag, and appropriate
PKG_CONFIG_LIBDIR va
Acked-by: Vladimir Medvedkin
On 26/07/2024 15:54, Niall Meade wrote:
Separated name, entries and key_len parameter checks in
rte_hash_create(). Also made the error messages more
informative/verbose to help with debugging. Also added myself to the
mailing list.
Signed-off-by: Niall Meade
---
I am not aware of such plans.
From: rajesh goel
Sent: Wednesday, August 28, 2024 11:22 AM
To: Medvedkin, Vladimir
Cc: Ferruh Yigit ; Wang, Yipeng1
; Gobriel, Sameh ; Richardson,
Bruce ; dev@dpdk.org
Subject: Re: Bihash Support in DPDK
Thanks Vladimir for the confirmation.
Is there any plan
Hi Rajesh,
rte_hash does not support per bucket locks, instead it uses global rwlock.
But you can try lock free mode (see documentation, in particular
RTE_HASH_EXTRA_FLAGS_RW_CONCURRENCY_LF flag)
From: rajesh goel
Sent: Tuesday, August 27, 2024 4:57 PM
To: Medvedkin, Vladimir
Cc: Ferruh
: rajesh goel
Sent: Tuesday, August 27, 2024 7:04 AM
To: Ferruh Yigit
Cc: Wang, Yipeng1 ; Gobriel, Sameh
; Richardson, Bruce ;
Medvedkin, Vladimir ; dev@dpdk.org
Subject: Re: Bihash Support in DPDK
Hi All,
Can we get some reply.
Thanks
Rajesh
On Thu, Aug 22, 2024 at 9:32 PM Ferruh Yigit
Hi Robin,
On 31/07/2024 16:04, Robin Jarry wrote:
Hi Vladimir,
I noticed that the fib/rib APIs (both IPv4 and IPv6) require the next
hops to be represented as integer indexes. Reading the code, I noticed
that they are stored as uint64_t with the MSB used for internal purposes.
I believe yo
Acked-by: Vladimir Medvedkin
On 23/07/2024 09:27, Robin Jarry wrote:
In 24.11, all IPv6 public APIs will be modified to use a structure
instead of fixed size arrays.
Signed-off-by: Robin Jarry
Acked-by: Morten Brørup
---
Notes:
v2: updated with the exhaustive list of symbols
doc/gui
Hi Robin,
Apologies for the delayed response
On 19/03/2024 20:38, Robin Jarry wrote:
Hi Vladimir,
Medvedkin, Vladimir, Mar 19, 2024 at 18:16:
> 2) Is it OK/safe to modify a fib from a control thread (read/write)
> while it is used by data path threads (read only)?
This part is
Hi all,
This patch breaks ipsec tests with ipsec-secgw:
./examples/ipsec-secgw/test/run_test.sh -4 trs_aesctr_sha1
...
ERROR: ./examples/ipsec-secgw/test/linux_test.sh failed for dst=192.168.31.14,
sz=1
test IPv4 trs_aesctr_sha1 finished with status 1
ERROR test trs_aesctr_sha1 FAILED
On 03
-Original Message-
From: Richardson, Bruce
Sent: Monday, July 22, 2024 12:25 PM
To: Medvedkin, Vladimir
Cc: dev@dpdk.org
Subject: Re: [PATCH v4 2/3] net/ice: refactor raw pattern parsing function
On Mon, Jul 22, 2024 at 10:59:49AM +, Vladimir Medvedkin wrote:
> Replace str
-Original Message-
From: Richardson, Bruce
Sent: Monday, July 22, 2024 11:42 AM
To: Medvedkin, Vladimir
Cc: dev@dpdk.org; sta...@dpdk.org; Stolarchuk, Michael
Subject: Re: [PATCH v3 1/3] net/ice: fix possible memory leak
On Mon, Jul 22, 2024 at 08:28:34AM +, Vladimir Medvedkin
Hi Morten,
On 19/07/2024 10:12, Morten Brørup wrote:
From: Robin Jarry [mailto:rja...@redhat.com]
Vladimir Medvedkin, Jul 18, 2024 at 23:25:
I think alignment should be 1 since in FIB6 users usually don't copy
IPv6
address and just provide a pointer to the memory inside the packet.
How can
Hi Bruce,
Sure, will submit v2.
Thanks!
-Original Message-
From: Richardson, Bruce
Sent: Thursday, July 11, 2024 6:05 PM
To: Medvedkin, Vladimir
Cc: dev@dpdk.org; ting...@intel.com; Stolarchuk, Michael
Subject: Re: [PATCH] net/ice: fix possible memory leak
On Thu, Jul 11, 2024 at
Acked-by: Vladimir Medvedkin
On 04/07/2024 07:50, Mingjin Ye wrote:
This patch enable three Forward Error Correction(FEC) related ops
in ice driver. As no speed information can get from HW, this patch
only show FEC capability.
Signed-off-by: Qiming Yang
Signed-off-by: Mingjin Ye
---
v3: opt
Hi Minjin,
- please update release notes
- see comments inline
On 02/07/2024 09:02, Mingjin Ye wrote:
This patch enable three Forward Error Correction(FEC) related ops
in ice driver. As no speed information can get from HW, this patch
only show FEC capability.
Signed-off-by: Qiming Yang
Signe
Acked-by: Vladimir Medvedkin
On 02/07/2024 09:40, Zhichao Zeng wrote:
This patch enabled querying Forward Error Correction(FEC) capabilities,
set FEC mode and get current FEC mode functions.
Signed-off-by: Zhichao Zeng
---
v6: fix some judgments
v5: fix some judgments
v4: fix some logic
v3:
Hi Zhichao,
On 11/04/2024 10:29, Zhichao Zeng wrote:
This patch enabled querying Forward Error Correction(FEC) capabilities,
set FEC mode and get current FEC mode functions.
Signed-off-by: Qiming Yang
Signed-off-by: Zhichao Zeng
---
v5: fix some judgments
v4: fix some logic
v3: optimize code
Hi Mingjin,
On 11/04/2024 10:45, Mingjin Ye wrote:
This patch enable three Forward Error Correction(FEC) related ops
in ice driver. As no speed information can get from HW, this patch
only show FEC capability.
Signed-off-by: Mingjin Ye
---
doc/guides/nics/features/ice.ini | 1 +
doc/guides
Hi Robin,
On 19/03/2024 08:30, Robin Jarry wrote:
Hi Vladimir,
I have been using rte_fib for a while and stumbled upon a few quirks.
I was wondering if you would answer some questions:
1) Is it OK/safe to share the same fib to perform route lookups from
multiple lcores in parallel? So far
Hi Zhichao,
On 12/03/2024 08:44, Zeng, ZhichaoX wrote:
Hi Vladimir:
Thanks for your comments, some responses and questions are inline.
From: Medvedkin, Vladimir
Sent: Monday, March 11, 2024 11:59 PM
To: Zeng, ZhichaoX ; dev@dpdk.org
Cc: Cui, KaixinX ; Yang, Qiming ;
Zhang, Yuying
Subject
Hi Zhicha,
It would be good to reflect FEC feature here:
https://doc.dpdk.org/guides/nics/overview.html
in "/Table 1.1 //Features availability in networking drivers/"
please find the rest comments inline
On 06/03/2024 10:41, Zhichao Zeng wrote:
This patch enabled querying Forward Error Corre
Acked-by: Vladimir Medvedkin
On 06/03/2024 20:13, Tyler Retzlaff wrote:
Zero length arrays are GNU extension. Replace with
standard flex array.
Signed-off-by: Tyler Retzlaff
Reviewed-by: Morten Brørup
---
lib/lpm/rte_lpm6.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Acked-by: Vladimir Medvedkin
On 06/03/2024 20:13, Tyler Retzlaff wrote:
Zero length arrays are GNU extension. Replace with
standard flex array.
Signed-off-by: Tyler Retzlaff
Reviewed-by: Morten Brørup
Acked-by: Stephen Hemminger
---
lib/fib/dir24_8.h | 2 +-
lib/fib/trie.h| 2 +-
2
Acked-by: Vladimir Medvedkin
On 06/03/2024 20:13, Tyler Retzlaff wrote:
Zero length arrays are GNU extension. Replace with
standard flex array.
Signed-off-by: Tyler Retzlaff
Reviewed-by: Honnappa Nagarahalli
Reviewed-by: Morten Brørup
Acked-by: Chengwen Feng
Acked-by: Stephen Hemminger
--
Acked-by: Vladimir Medvedkin
On 28/02/2024 18:47, Tyler Retzlaff wrote:
Use newly added __rte_pure macro from rte_common.h instead of directly
using __attribute__((pure)).
Signed-off-by: Tyler Retzlaff
Reviewed-by: Morten Brørup
---
lib/lpm/rte_lpm.c | 4 ++--
lib/lpm/rte_lpm6.c | 2 +-
Hi Beilei,
Just a one nit below, besides that LGTM
Acked-by: Vladimir Medvedkin
On 22/12/2023 16:51, beilei.x...@intel.com wrote:
From: Beilei Xing
Since the response of virtual channel virtchnl2_get_ptype_info is
changed on IMC side, driver needs to be updated when requiring
the virtual ch
On 15/02/2024 13:31, edwin.brosse...@6wind.com wrote:
From: Edwin Brossette
Different Intel nics with the igxbe pmd do not handle RSS in the same
way when working with virtualization. While some nics like Intel 82599ES
only have a single RSS table in the device and leave all rss features to
b
On 30/01/2024 10:00, Kevin Traynor wrote:
When vf issues a reset to pf there is a 50 msec wait plus an additional
max of 1 msec for the pf to indicate the reset is complete before
timeout.
In some cases, it is seen that the reset is timing out, in which case
the reset does not complete and an er
Hi Abdullah,
Could you please tell more about use cases where this API may be useful?
a new API to get the hidden key count in the hash table if the rcu qsbr is
enabled
Here in commit message and down below in doxygen comments, I think this
statement should be more specific because rcu can
Hi Wenjing,
Please find comments inlined
On 05/01/2024 08:16, wenjing.q...@intel.com wrote:
From: Wenjing Qiao
Add TDI implementation to a flow engine.
Signed-off-by: Wenjing Qiao
---
--- /dev/null
+++ b/drivers/net/cpfl/cpfl_tdi.c
@@ -0,0 +1,1282 @@
+/* SPDX-License-Identifier: BSD-3-Clau
Hi Wenjing,
Please find comments inlined
On 05/01/2024 08:16, wenjing.q...@intel.com wrote:
From: Wenjing Qiao
To supporting P4-programmed network controller, reuse devargs
"flow_parser" to specify the path of a p4 context JSON configure
file. The cpfl PMD use the JSON configuration file to t
Hi Jeffrey,
Have you tried FIB library? This problem has been solved there for a
long time, and it also has a number of other improvements.
Thanks!
On 10/11/2023 14:08, Warrington, Jeffrey wrote:
On 11/10/23, 2:42 AM, "David Marchand" mailto:david.march...@redhat.com>> wrote:
On Fri, Nov 1
Hi Satananda, Anoob, Chengwen, Jerin, all,
After a number of internal discussions we have decided that we're going
to postpone this feature/patchset till next release.
>[Satananda] Have you considered extending rte_dma_port_param and
rte_dma_vchan_conf to represent interdomain memory transfe
Acked-by: Vladimir Medvedkin
On 10/07/2023 22:59, Bili Dong wrote:
An XOR32 hash is needed in the Software Switch (SWX) Pipeline for its
use case in P4. We implement it in this patch so it could be easily
registered in the pipeline later.
Signed-off-by: Bili Dong
--
Regards,
Vladimir
Hi David,
Yes, I sent them separately because the bugfix in mentioned patch should be
backported unlike adding a new test.
-Original Message-
From: David Marchand
Sent: Thursday, June 29, 2023 2:00 PM
To: Medvedkin, Vladimir
Cc: dev@dpdk.org; konstantin.v.anan...@yandex.ru
Subject
Hi Bili,
Please find just one nit below inlined
Apart from it LGTM
Acked-by: Vladimir Medvedkin
On 20/06/2023 20:12, Bili Dong wrote:
An XOR32 hash is needed in the Software Switch (SWX) Pipeline for its
use case in P4. We implement it in this patch so it could be easily
registered in the pi
Hi Bill,
On 15/02/2023 11:06, Bili Dong wrote:
An XOR32 hash is needed in the Software Switch (SWX) Pipeline for its
use case in P4. We implement it in this patch so it could be easily
registered in the pipeline later.
Signed-off-by: Bili Dong
---
+static inline uint32_t
+rte_hash_xor(const vo
Hi Stepthen,
There is a problem with the build on a machine that supports GFNI:
../lib/hash/rte_thash_gfni.c:15:1: error: redefinition of ‘rte_thash_gfni’
15 | rte_thash_gfni(const uint64_t *mtrx __rte_unused,
| ^~
In file included from ../lib/hash/rte_thash_gfni.h:13,
Hi Stephen,
On 03/11/2022 18:33, Stephen Hemminger wrote:
On Thu, 3 Nov 2022 18:13:38 +
Vladimir Medvedkin wrote:
+ if (ret != 0) {
+ printf("rte_hash_lookup_with_hash_bulk"
+
Acked-by: Vladimir Medvedkin
On 30/09/2022 13:40, Radu Nicolau wrote:
Fix a typo in computing port mask for Tx checksum offload capability.
Fixes: 4edcee19fc20 ("examples/ipsec-secgw: use Tx checksum offload
conditionally")
Cc: ndabilpu...@marvell.com
Signed-off-by: Radu Nicolau
---
examp
Acked-by: Vladimir Medvedkin
On 07/09/2022 12:33, Sean Morrissey wrote:
This patch fixes a core dump which occurs on 32-bit-builds
after sending a matched packet due to overrunning an array.
Fixes: 6de0ea50e9b9 ("examples/l3fwd: merge l3fwd-acl example")
Cc: sean.morris...@intel.com
Cc: sta...
Tested-by: Vladimir Medvedkin
On 30/06/2022 12:45, Radu Nicolau wrote:
Fix fallback session create for inline sessions.
Fixes: a8ade12123c3 ("examples/ipsec-secgw: create lookaside sessions at init")
Cc: vfia...@marvell.com
Signed-off-by: Radu Nicolau
---
v2: create the session rather than j
Acked-by: Vladimir Medvedkin
On 22/06/2022 21:41, Stephen Hemminger wrote:
The comments in rte_rib6 were cut-and-pasted from rte_rib
and because of that some references to rte_rib_node were
not updated.
Signed-off-by: Stephen Hemminger
---
lib/rib/rte_rib6.h | 6 +++---
1 file changed, 3 i
On 17/06/2022 13:06, David Marchand wrote:
On Thu, Jun 16, 2022 at 11:33 AM David Marchand
wrote:
GCC 12 raises the following warning:
In function ‘_mm256_loadu_si256’,
inlined from ‘rte_mov32’ at
../lib/eal/x86/include/rte_memcpy.h:319:9,
inlined from ‘rte_mov128’ at
Hi David,
On 03/06/2022 10:41, David Marchand wrote:
On Fri, Jun 3, 2022 at 9:56 AM Bruce Richardson
wrote:
On Fri, Jun 03, 2022 at 09:45:45AM +0200, David Marchand wrote:
Hello Vladimir,
On Thu, Jun 2, 2022 at 8:42 PM Medvedkin, Vladimir
wrote:
if (!dst
Hi David,
On 18/05/2022 11:16, David Marchand wrote:
GCC 12 raises the following warning:
In function ‘_mm256_loadu_si256’,
inlined from ‘rte_mov32’ at
../lib/eal/x86/include/rte_memcpy.h:319:9,
inlined from ‘rte_mov128’ at
../lib/eal/x86/include/rte_memcpy.h:344:2,
On 01/06/2022 12:15, Stanislaw Kardach wrote:
From: Michal Mazurek
Add an implementation of the rte_lpm_lookupx4() function for platforms
without support for vector operations.
This will be useful in the upcoming RISC-V port as well as any platform
which may want to start with a basic level
Hi Stanislaw,
On 30/05/2022 19:24, Stanislaw Kardach wrote:
From: Michal Mazurek
Add an implementation of the rte_lpm_lookupx4() function for platforms
without support for vector operations.
This will be useful in the upcoming RISC-V port as well as any platform
which may want to start with
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