Including rte_byteorder.h may fail for ARM builds with 'Platform must
be built with RTE_FORCE_INTRINSICS' if rte_config.h is not included
before. Include rte_config.h from rte_byteorder.h to solve the issue.
Fixes: de966ccdcd7f ("eal/arm: add byte order operations for ARM")
Cc: ko...@rehivetech.co
Hi Lingyu, comments in line.
> -Original Message-
> From: Liu, Lingyu
> Sent: Monday, June 7, 2021 20:51
> To: dev@dpdk.org; Zhang, Qi Z ; Xing, Beilei
> ; Wu, Jingjing
> Cc: Guo, Junfeng ; Liu, Lingyu
>
> Subject: [PATCH v4 4/4] net/iavf: support AVF RSS for GTPoGRE packet
>
> Support
Including rte_byteorder.h may fail for ARM builds with 'Platform must
be built with RTE_FORCE_INTRINSICS' if rte_config.h is not included
before. Include rte_config.h from rte_byteorder.h to solve the issue.
Fixes: de966ccdcd7f ("eal/arm: add byte order operations for ARM")
Cc: ko...@rehivetech.co
Support AVF RSS for inner most header of GTPoGRE packet. It supports
RSS based on inner most IP src + dst address and TCP/UDP src + dst
port.
Signed-off-by: Lingyu Liu
---
drivers/net/iavf/iavf_hash.c | 63 +---
1 file changed, 58 insertions(+), 5 deletions(-)
di
Support AVF FDIR for inner header of GTPoGRE tunnel packet.
++---+
|Pattern |Input Set |
++---+
|eth/ipv4/gre/ipv4/gtpu/(
Add a virtchnl protocol header type to support AVF FDIR and RSS for GRE.
Signed-off-by: Lingyu Liu
---
drivers/common/iavf/virtchnl.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/common/iavf/virtchnl.h b/drivers/common/iavf/virtchnl.h
index 3a60faff93..197edce8a1 100644
--- a/driv
Add GTPoGRE pattern support for AVF FDIR and RSS.
Signed-off-by: Lingyu Liu
---
drivers/net/iavf/iavf_generic_flow.c | 600 +++
drivers/net/iavf/iavf_generic_flow.h | 80
2 files changed, 680 insertions(+)
diff --git a/drivers/net/iavf/iavf_generic_flow.c
b/driver
Support AVF RSS and FDIR for GTPoGRE packet.
Lingyu Liu (4):
net/iavf: support flow pattern for GTPoGRE
common/iavf: add header types for GRE
net/iavf: support AVF FDIR for GTPoGRE tunnel packet
net/iavf: support AVF RSS for GTPoGRE packet
---
V4 change:
- add RTE_FLOW_ITEM_TYPE_GRE in
> -Original Message-
> From: Wu, Jingjing
> Sent: Tuesday, June 1, 2021 2:02 PM
> To: Xing, Beilei ; Zhang, Qi Z
> Cc: dev@dpdk.org; sta...@dpdk.org
> Subject: RE: [PATCH] net/iavf: fix Rx issue for scalar Rx functions
>
>
> > -Original Message-
> > From: Xing, Beilei
> > Se
> -Original Message-
> From: dev On Behalf Of dapengx...@intel.com
> Sent: Friday, June 4, 2021 10:02 AM
> To: Xing, Beilei
> Cc: dev@dpdk.org; Yu, DapengX ; sta...@dpdk.org
> Subject: [dpdk-dev] [PATCH] net/i40e: fix using heap pointer after free
>
> From: Dapeng Yu
>
> The origina
> -Original Message-
> From: Xu, Ting
> Sent: Wednesday, June 2, 2021 4:21 PM
> To: dev@dpdk.org
> Cc: Zhang, Qi Z ; Yang, Qiming
> ; Xu, Ting ; sta...@dpdk.org
> Subject: [PATCH v1] net/ice: fix wrong FDIR flow type for IPv4 fragment
>
> When creating FDIR rule and parsing the pattern
On Tue, Jun 1, 2021 at 1:27 PM Ruifeng Wang wrote:
>
> Number of rx queue and number of rx port in lcore config are constants
> during the period of l3 forward application running. But compiler has
> no this information.
>
> Copied values from lcore config to local variables and used the local
> v
On Tue, Jun 1, 2021 at 1:27 PM Ruifeng Wang wrote:
>
> Moved rfc1812 process prior to NEON registers store.
> On N1SDP, this reorganization mitigates CPU frontend stall and backend
> stall when forwarding.
>
> On N1SDP with MLX5 40G NIC, this change showed 10.2% performance gain
> in single port s
> >
> > Add the logic to determine how many DD bits have been set for
> > contiguous packets, for removing the SMP barrier while reading descs.
>
> I didn't understand this.
> The current logic already guarantee the read out DD bits are from continue
> packets, as it read Rx descriptor in a reve
On Fri, Jun 4, 2021 at 5:18 PM Michael Pfeiffer
wrote:
>
> Including rte_byteorder.h may fail for ARM builds with 'Platform must
> be built with RTE_FORCE_INTRINSICS' if rte_config.h is not included
> before. Include rte_config.h from rte_byteorder.h to solve the issue.
>
> Signed-off-by: Michael
The IO barrier is not required as cqe->op_own is read once. The
checks done on the local variable and the memory is not read again.
Fixes: 88c0733535d6 ("net/mlx5: extend Rx completion with error handling")
Cc: ma...@mellanox.com
Cc: sta...@dpdk.org
Signed-off-by: Honnappa Nagarahalli
Reviewed-b
> -Original Message-
> From: Joyce Kong
> Sent: Friday, June 4, 2021 3:34 PM
> To: Xing, Beilei ; Zhang, Qi Z ;
> ruifeng.w...@arm.com; honnappa.nagaraha...@arm.com
> Cc: dev@dpdk.org; n...@arm.com
> Subject: [PATCH v1] net/i40e: remove the SMP barrier in HW scanning func
>
> Add the l
Hi Shiri,
> -Original Message-
> From: Shiri Kuzin
> Sent: Monday, May 31, 2021 2:46 PM
> To: dev@dpdk.org
> Cc: Matan Azrad ; Raslan Darawsheh
> ; Slava Ovsiienko
> Subject: [PATCH] net/mlx5: update GENEVE TLV option exist bit
>
> The GENEVE TLV option matching is done using a flex par
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