Calculating hash for data of variable length is more efficient
when that data is sliced into 8-byte pieces. The rest part of data
is hashed using CRC32 functions with either 8 and 4 byte operands.
Signed-off-by: Yerden Zhumabekov
---
lib/librte_hash/rte_hash_crc.h | 33
Initially, SSE4.2 support is detected via CPUID instruction.
Added rte_hash_crc_set_alg() function to detect and set CRC32
implementation if necessary. SSE4.2 is allowed by default. If it's
not available, fall back to sw implementation.
Signed-off-by: Yerden Zhumabekov
---
lib/librte_hash/rte_h
SSE4.2 provides _mm_crc32_u64 intrinsic with 8-byte operand.
Signed-off-by: Yerden Zhumabekov
---
lib/librte_hash/rte_hash_crc.h | 16
1 file changed, 16 insertions(+)
diff --git a/lib/librte_hash/rte_hash_crc.h b/lib/librte_hash/rte_hash_crc.h
index 3c368c5..74e2d92 100644
-
Add lookup table for CRC32 algorithm, crc32c_1word() and
crc32c_2words() functions returning hash of 32-bit and
64-bit operand.
Signed-off-by: Yerden Zhumabekov
---
lib/librte_hash/rte_hash_crc.h | 105
1 file changed, 105 insertions(+)
diff --git a/lib
This is a rework of my previous patches improving performance of rte_hash_crc.
In addition, this revision brings a fallback mechanism to ensure that CRC32
hash is calculated regardless of hardware support from CPU (i.e. SSE4.2
intrinsics).
Summary of changes:
* added CRC32 software implementati
IBM Power architecture has different memory architecture with x86. When
the physical memory address is in ascending order, the mmaped virtual
address is in descending order. This patch modified the memory segment
detection code to make it work for Power. This patch also added a
commond ARCH_PPC_64
IBM Power architecture has different huge page sizes (16MB, 16GB) than
x86.This patch defines RTE_PGSIZE_16M and RTE_PGSIZE_16G in the
rte_page_sizes enum variable and adds huge page size support of DPDK
for IBM Power architecture.
Signed-off-by: Chao Zhu
---
app/test/test_memzone.c
IBM Power architecture has different cache line size (128 bytes) than
x86 (64 bytes). This patch defines CACHE_LINE_SIZE to 128 bytes to
override the default value 64 bytes to support IBM Power Architecture.
Signed-off-by: Chao Zhu
---
app/test/test_malloc.c |8
mk/arch/ppc_64/r
iopl() call is mostly for the i386 architecture. In Power and other
architecture, it doesn't exist. This patch modified rte_eal_iopl_init()
and make it return -1 for Power and other architecture. Thus
rte_config.flags will not contain EAL_FLG_HIGH_IOPL flag for other
architecture.
Signed-off-by: C
IBM Power processor doesn't have CPU flag hardware registers. This patch
uses aux vector software register to get CPU flags and add CPU flag
checking support for IBM Power architecture.
Signed-off-by: Chao Zhu
---
app/test/test_cpuflags.c | 35
.../common/include
The SSE based memory copy in DPDK only support x86. This patch adds
altivec based memory copy functions for IBM Power architecture.
Signed-off-by: Chao Zhu
---
.../common/include/arch/ppc_64/rte_memcpy.h| 223
1 files changed, 223 insertions(+), 0 deletions(-)
crea
This patch adds spinlock operations for IBM Power architecture.
Signed-off-by: Chao Zhu
---
.../common/include/arch/ppc_64/rte_spinlock.h | 73
1 files changed, 73 insertions(+), 0 deletions(-)
create mode 100644 lib/librte_eal/common/include/arch/ppc_64/rte_spinlock
This patch add architecture specific prefetch operations for IBM Power
architecture.
Signed-off-by: Chao Zhu
---
.../common/include/arch/ppc_64/rte_prefetch.h | 61
1 files changed, 61 insertions(+), 0 deletions(-)
create mode 100644 lib/librte_eal/common/include/arc
IBM Power architecture doesn't have TSC register to get CPU cycles. This
patch implements the time base register read instead of TSC register of
x86 on IBM Power architecture.
Signed-off-by: Chao Zhu
---
.../common/include/arch/ppc_64/rte_cycles.h| 86
1 files chan
This patch adds architecture specific byte order operations for IBM Power
architecture. Power architecture support both big endian and little
endian. This patch also adds a RTE_ARCH_BIG_ENDIAN micro.
Signed-off-by: Chao Zhu
---
config/defconfig_ppc_64-power8-linuxapp-gcc|1 +
.../com
This patch adds architecture specific atomic operation file for IBM
Power architecture CPU.
Signed-off-by: Chao Zhu
---
.../common/include/arch/ppc_64/rte_atomic.h| 415
1 files changed, 415 insertions(+), 0 deletions(-)
create mode 100644 lib/librte_eal/common/inc
To make DPDK run on IBM Power architecture, configuration files for
Power architecuture are added. Also, the compiling related .mk files are
added.
Signed-off-by: Chao Zhu
---
config/common_linuxapp_powerpc | 394 +++
config/defconfig_ppc_64-power8-linuxapp-
The set of patches add IBM Power architecture to the DPDK. It adds the required
support to the
EAL library. This set of patches doesn't support full DPDK function on Power
processors. Many
functions are turned off in configuratidon file. More patches will be added
continuesly.
Chao Zhu (12):
2014-11-14 08:44, Pattan, Reshma:
> From: Thomas Monjalon [mailto:thomas.monjalon at 6wind.com]
> > > > From: Reshma Pattan
> > > >
> > > > A new sample app that shows the usage of the distributor library.
> > > > This app works as follows:
> > > >
> > > > * An RX thread runs which pulls packets f
Hi All,
Can someone please provide comments on queries in below mail?
Regards,
Satish Babu
On Mon, Nov 10, 2014 at 4:24 PM, satish wrote:
> Hi,
> I need comments on performance impact with DPDK-QoS.
>
> We are working on developing a application based on DPDK.
> Our application supports IPv4 fo
From: Nicol?s Pernas Maradei
Virtual and physical devices are now treated the same in terms of
white/black listing. Virtual devices can be defined using --vdev as
before and also whitelisted (using -w vdev_name) or blacklisted (using -b
vdev_name). This allows the user to have only a virtual devi
On 10/11/14 08:13, Olivier MATZ wrote:
> What about using the --no-pci option ?
>
> It would blacklist all physical devices (as PCI devices are the only
> ones supported today).
Hi Olivier,
Your idea does work for me. Although it's more a workaround than a real
solution. I'll be submitting a pa
Hi,
I'm working with a VMware SRIOV with intel 10G nics.
I'm using two virtual functions per VM, mainly because I need loopback
(the LLE(PFVMTXSW[n])
register is not allowing loopback on a VF by default).
After adding a second VF to the VM's I often see issues where no traffic is
passing between t
15.11.2014 0:41, Neil Horman ?:
> On Fri, Nov 14, 2014 at 10:43:39PM +0600, Yerden Zhumabekov wrote:
>> 14.11.2014 19:53, Neil Horman ?:
>>>
>>> Well, its possible you'll get lucky. crc is such a common operation, its
>>> entirely possible that the gcc intrinsic emits software based crc
Hi, Bruce and Neil,
Do you indicate that to add one program arg, such as "--mem-only", to let the
rte_eal_init()only to do those memory initializing things? I am worrying that
this would make rte_eal_init() more complex due to the "--mem-only" should be
judged here and there, even in some sub-fu
Support of updating/querying redirection table has been added for VF.
Signed-off-by: Helin Zhang
---
lib/librte_pmd_i40e/i40e_ethdev_vf.c | 99 ++--
1 file changed, 94 insertions(+), 5 deletions(-)
v2 changes:
* Add support of updating/querying i40e reta of VF.
As 40G NIC supports different sizes (128/512/64 entries) of
redirection table from that (128 entries) of 1G and 10G NICs,
support of multiple sizes of redirection table is needed.
It includes,
* Redefine 'struct rte_eth_rss_reta' in ethdev.
- To 'struct rte_eth_rss_reta_entry64' which contains 64
Returning redirection table size has been supported in ops of
'dev_infos_get' for both PF and VF. Default RX/TX configurations
of VF can be returned in ops of 'dev_infos_get', while it was
missed before.
Signed-off-by: Helin Zhang
---
lib/librte_pmd_i40e/i40e_ethdev.c| 15 +++
li
As more and more information are different between PF and VF, ops
of 'dev_infos_get' has been implemented respectively. In addition,
returning redirection table size has been supported in it.
Signed-off-by: Helin Zhang
---
lib/librte_pmd_ixgbe/ixgbe_ethdev.c | 90 +---
As more and more information are different between PF and VF,
ops of 'dev_infos_get' has been implemented respectively. In
addition, new field of 'reta_size' has been added in
'struct rte_eth_dev_info' for returning redirection table size.
Signed-off-by: Helin Zhang
---
lib/librte_ether/rte_ethd
Add support of setting hash lookup table size according
to the hardawre capability.
Signed-off-by: Helin Zhang
---
lib/librte_ether/rte_ethdev.h | 9 -
lib/librte_pmd_i40e/i40e_ethdev.c | 14 +-
lib/librte_pmd_i40e/i40e_ethdev.h | 1 +
3 files changed, 22 insertions(+),
Fix of several code style issues.
Signed-off-by: Helin Zhang
---
lib/librte_pmd_i40e/i40e_ethdev_vf.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/lib/librte_pmd_i40e/i40e_ethdev_vf.c
b/lib/librte_pmd_i40e/i40e_ethdev_vf.c
index 554d9d7..11f25cc 100644
--- a/
Fix of several code style issues.
Signed-off-by: Helin Zhang
---
app/test-pmd/cmdline.c | 28 +++-
app/test-pmd/config.c | 2 +-
2 files changed, 16 insertions(+), 14 deletions(-)
diff --git a/app/test-pmd/cmdline.c b/app/test-pmd/cmdline.c
index 4c3fc76..daba286 10064
As e1000, ixgbe and i40e hardware use different sizes of redirection
table in PF or VF, ethdev and PMDs need to be reworked to support
multiple sizes of that table. In addition, commands in testpmd also
need to be reworked to support these changes.
v2 changes:
* Reorganized the patches.
* Added co
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