64-bit Registers?

What would it take to get 64-bit registers like RAX, RBX, RCX, ... defined as identifiers? Thanks, JC

Re: Array Operations

Jonathan Crapuchettes wrote: Michael Parrott wrote: Jonathan Crapuchettes Wrote: I followed the example in issue #30: http://bitbucket.org/goshawk/gdc/issue/30/d_inlineasm-updates DFLAGS='-O2 -g -frelease -march=pentium3' ../configure --enable-languages=d --disable-multilib --disa

Re: Array Operations

Michael Parrott wrote: Jonathan Crapuchettes Wrote: I followed the example in issue #30: http://bitbucket.org/goshawk/gdc/issue/30/d_inlineasm-updates DFLAGS='-O2 -g -frelease -march=pentium3' ../configure --enable-languages=d --disable-multilib --disable-shared Is this wrong? J

Re: Array Operations

I followed the example in issue #30: http://bitbucket.org/goshawk/gdc/issue/30/d_inlineasm-updates DFLAGS='-O2 -g -frelease -march=pentium3' ../configure --enable-languages=d --disable-multilib --disable-shared Is this wrong? JC Michael Parrott wrote: Jonathan Crapuchettes Wrote

Array Operations

I have been trying to add the SSE2 array operation code to the compilation, but it seems like the DFLAGS variable isn't being used. Can you offer any suggestions? Thank you, JC