https://github.com/dtcxzyw approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/102022
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@@ -378,6 +378,32 @@ def SYNTACORE_SCR4_RV64 :
RISCVProcessorModel<"syntacore-scr4-rv64",
FeatureStdExtC],
[TuneNoDefaultUnroll,
FeaturePostRAScheduler]>;
+def SYNTACORE_SCR5_RV32 :
dtcxzyw wrote:
It looks like a toy project :( The RTL design is not frozen.
https://github.com/llvm/llvm-project/pull/102452
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https://github.com/dtcxzyw created
https://github.com/llvm/llvm-project/pull/104741
This patch extends [D34590](https://reviews.llvm.org/D34590) to check
assumption violations.
>From e2ce302a0d3649594ff1a6b94420f815d0e1acde Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Mon, 19 Aug 2024
@@ -1054,6 +1054,19 @@ def FeatureStdExtSupm
: RISCVExperimentalExtension<"supm", 1, 0,
"'Supm' (Indicates User-mode Pointer
Masking)">;
+def FeatureStdExtSmctr
+: RISCVExperimentalExtension<"smctr", 1, 0,
+
@@ -839,6 +839,14 @@ def HLV_D : HLoad_r<0b0110110, 0b0, "hlv.d">,
Sched<[]>;
def HSV_D : HStore_rr<0b0110111, "hsv.d">, Sched<[]>;
}
+let Predicates = [HasStdExtSmctrOrSsctr] in {
+def SCTRCLR : Priv<"sctrclr", 0b0001000>, Sched<[]> {
dtcxzyw wrote:
@@ -1054,6 +1054,19 @@ def FeatureStdExtSupm
: RISCVExperimentalExtension<"supm", 1, 0,
"'Supm' (Indicates User-mode Pointer
Masking)">;
+def FeatureStdExtSmctr
+: RISCVExperimentalExtension<"smctr", 1, 0,
+
https://github.com/dtcxzyw approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/105148
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https://github.com/dtcxzyw approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/105476
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dtcxzyw wrote:
Reverse ping :)
https://github.com/llvm/llvm-project/pull/97762
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https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/94352
>From ff839bef048a65760f4cd0e9abafe11cfebd9362 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Tue, 4 Jun 2024 21:08:27 +0800
Subject: [PATCH 1/5] [RISCV] Add support for getHostCPUFeatures using hwprobe
Co-a
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/94352
>From ff839bef048a65760f4cd0e9abafe11cfebd9362 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Tue, 4 Jun 2024 21:08:27 +0800
Subject: [PATCH 1/6] [RISCV] Add support for getHostCPUFeatures using hwprobe
Co-a
dtcxzyw wrote:
I have no idea about why it corrupts StringMap. Sad :(
https://github.com/llvm/llvm-project/pull/94352
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@@ -1571,7 +1571,9 @@ StringRef sys::getHostCPUName() {
#if defined(__linux__)
std::unique_ptr P = getProcCpuinfoContent();
StringRef Content = P ? P->getBuffer() : "";
- return detail::getHostCPUNameForRISCV(Content);
+ StringRef Name = detail::getHostCPUNameForRISCV(Con
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/94352
>From ff839bef048a65760f4cd0e9abafe11cfebd9362 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Tue, 4 Jun 2024 21:08:27 +0800
Subject: [PATCH 1/7] [RISCV] Add support for getHostCPUFeatures using hwprobe
Co-a
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/94352
>From ff839bef048a65760f4cd0e9abafe11cfebd9362 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Tue, 4 Jun 2024 21:08:27 +0800
Subject: [PATCH 1/8] [RISCV] Add support for getHostCPUFeatures using hwprobe
Co-a
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/94352
>From ff839bef048a65760f4cd0e9abafe11cfebd9362 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Tue, 4 Jun 2024 21:08:27 +0800
Subject: [PATCH 1/9] [RISCV] Add support for getHostCPUFeatures using hwprobe
Co-a
dtcxzyw wrote:
> > I have no idea about why it corrupts StringMap. Sad :(
> > ![image](https://private-user-images.githubusercontent.com/15650457/341986439-fd427068-6ca0-4ecb-a340-48c51e5629a6.png?jwt=eyJhbGciOiJIUzI1NiIsInR5cCI6IkpXVCJ9.eyJpc3MiOiJnaXRodWIuY29tIiwiYXVkIjoicmF3LmdpdGh1YnVzZXJjb25
https://github.com/dtcxzyw created
https://github.com/llvm/llvm-project/pull/96465
Ztso 1.0 was ratified in January 2023.
Documentation:
https://github.com/riscv/riscv-isa-manual/blob/main/src/ztso-st-ext.adoc
>From 34670ab55ccecb1a2c7d92f809c9cae0df4150c6 Mon Sep 17 00:00:00 2001
From: Yingw
dtcxzyw wrote:
See https://github.com/llvm/llvm-project/pull/96465
https://github.com/llvm/llvm-project/pull/94352
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@@ -365,24 +365,30 @@
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZFHMIN %s
// RV32-ZFHMIN: "-target-feature" "+zfhmin"
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32iztso -### %s \
+// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izalasr
https://github.com/dtcxzyw closed
https://github.com/llvm/llvm-project/pull/96465
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https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/94352
>From ff839bef048a65760f4cd0e9abafe11cfebd9362 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Tue, 4 Jun 2024 21:08:27 +0800
Subject: [PATCH 01/10] [RISCV] Add support for getHostCPUFeatures using
hwprobe
C
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/94352
>From ff839bef048a65760f4cd0e9abafe11cfebd9362 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Tue, 4 Jun 2024 21:08:27 +0800
Subject: [PATCH 01/11] [RISCV] Add support for getHostCPUFeatures using
hwprobe
C
@@ -2002,6 +2003,76 @@ bool sys::getHostCPUFeatures(StringMap &Features) {
return true;
}
+#elif defined(__linux__) && defined(__riscv)
+// struct riscv_hwprobe
+struct RISCVHwProbe {
+ int64_t Key;
+ uint64_t Value;
+};
+bool sys::getHostCPUFeatures(StringMap &Features) {
https://github.com/dtcxzyw edited
https://github.com/llvm/llvm-project/pull/94352
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@@ -2002,6 +2003,76 @@ bool sys::getHostCPUFeatures(StringMap &Features) {
return true;
}
+#elif defined(__linux__) && defined(__riscv)
+// struct riscv_hwprobe
+struct RISCVHwProbe {
+ int64_t Key;
+ uint64_t Value;
+};
+bool sys::getHostCPUFeatures(StringMap &Features) {
@@ -2002,6 +2003,76 @@ bool sys::getHostCPUFeatures(StringMap &Features) {
return true;
}
+#elif defined(__linux__) && defined(__riscv)
+// struct riscv_hwprobe
+struct RISCVHwProbe {
+ int64_t Key;
+ uint64_t Value;
+};
+bool sys::getHostCPUFeatures(StringMap &Features) {
dtcxzyw wrote:
Any thoughts? Hopefully I can catch up with the 19 release :)
https://github.com/llvm/llvm-project/pull/94352
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@@ -2002,6 +2003,76 @@ bool sys::getHostCPUFeatures(StringMap &Features) {
return true;
}
+#elif defined(__linux__) && defined(__riscv)
+// struct riscv_hwprobe
+struct RISCVHwProbe {
+ int64_t Key;
+ uint64_t Value;
+};
+bool sys::getHostCPUFeatures(StringMap &Features) {
@@ -83,8 +83,14 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const
llvm::Triple &Triple,
// and other features (ex. mirco architecture feature) from mcpu
if (Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) {
StringRef CPU = A->getValue();
-if (CPU == "nat
dtcxzyw wrote:
> This patch causes some significant performance regressions on llvm-test-suite
> (rv64gc-O3-thinlto):
>
> Name Before After Ratio
> SingleSource/Benchmarks/Shootout/Shootout-random 2.150161677
> 3.300161641 + 53.5%
> SingleSource/Benchmarks/Polybench/linear-alg
dtcxzyw wrote:
> Does that mean it has a negative net effect, or its neutral
It is neutral.
> (in which case the original motivating case should be enough).
But this patch may have an impact on compile time.
https://github.com/llvm/llvm-project/pull/96620
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https://github.com/llvm/llvm-project/pull/94352
>From ff839bef048a65760f4cd0e9abafe11cfebd9362 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Tue, 4 Jun 2024 21:08:27 +0800
Subject: [PATCH 01/12] [RISCV] Add support for getHostCPUFeatures using
hwprobe
C
@@ -83,8 +83,14 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const
llvm::Triple &Triple,
// and other features (ex. mirco architecture feature) from mcpu
if (Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) {
StringRef CPU = A->getValue();
-if (CPU == "nat
@@ -83,8 +83,14 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const
llvm::Triple &Triple,
// and other features (ex. mirco architecture feature) from mcpu
if (Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) {
StringRef CPU = A->getValue();
-if (CPU == "nat
@@ -290,8 +290,24 @@ StringRef riscv::getRISCVArch(const llvm::opt::ArgList
&Args,
// 2. Get march (isa string) based on `-mcpu=`
if (const Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) {
StringRef CPU = A->getValue();
-if (CPU == "native")
+if (CPU == "nativ
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/94352
>From ff839bef048a65760f4cd0e9abafe11cfebd9362 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Tue, 4 Jun 2024 21:08:27 +0800
Subject: [PATCH 01/13] [RISCV] Add support for getHostCPUFeatures using
hwprobe
C
@@ -502,3 +502,28 @@
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr5-rv64 |
FileCheck -check-prefix=MTUNE-SYNTACORE-SCR5-RV64 %s
// MTUNE-SYNTACORE-SCR5-RV64: "-tune-cpu" "syntacore-scr5-rv64"
+
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=synt
https://github.com/dtcxzyw approved this pull request.
LG
https://github.com/llvm/llvm-project/pull/108406
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dtcxzyw wrote:
> TBH I am wondering if we should revert this rename. I don't think it's a good
> idea to reuse getDeclaration with substantially different semantics, and if
> we're not reusing it, then there's not much point to rename...
>
> Instead of having getOrInsertDeclaration + getDeclar
dtcxzyw wrote:
> Failed Tests (2):
Clang :: Driver/print-supported-extensions-riscv.c
Clang :: Preprocessor/riscv-target-features.c
https://github.com/llvm/llvm-project/pull/111837
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dtcxzyw wrote:
> > > > Personally I don't like to add a privileged extension if it doesn't
> > > > introduce new CSRs/instructions.
> > >
> > >
> > > I'd actually put that on the
> > > [agenda](https://docs.google.com/document/d/1G3ocHm2zE6AYTS2N3_3w2UxFnSEyKkcF57siLWe-NVs/edit?tab=t.0)
> > >
@@ -3096,6 +3096,15 @@ Instruction
*InstCombinerImpl::visitGetElementPtrInst(GetElementPtrInst &GEP) {
}
}
+ // nusw + nneg -> nuw
+ if (GEP.hasNoUnsignedSignedWrap() && !GEP.hasNoUnsignedWrap() &&
+ all_of(GEP.indices(), [&](Value *Idx) {
+return isKnown
https://github.com/dtcxzyw commented:
Personally I don't like to add a privileged extension if it doesn't introduce
new CSRs/instructions.
https://github.com/llvm/llvm-project/pull/111837
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https://github.com/dtcxzyw commented:
Middle-end/CodeGen/RISC-V changes LGTM.
https://github.com/llvm/llvm-project/pull/80309
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dtcxzyw wrote:
`APInt::getAllOnes` will assert if `BitWidth == 0`.
```
[--] 6 tests from APFloatTest
[ RUN ] APFloatTest.MinimumNumber
[ OK ] APFloatTest.MinimumNumber (0 ms)
[ RUN ] APFloatTest.Float8E8M0FNUValues
ADTTests:
/home/dtcxzyw/WorkSpace/Projects/compilers/llvm
dtcxzyw wrote:
@T-Tie
Can you fill in the PR description? Then I will merge this patch :)
https://github.com/llvm/llvm-project/pull/111837
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dtcxzyw wrote:
cc @cyyself
https://github.com/llvm/llvm-project/pull/115981
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https://github.com/dtcxzyw requested changes to this pull request.
Reproducer:
```
; bin/opt -passes=inline reduced.ll -S
target datalayout =
"e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
define i64 @caller(ptr %p1,
dtcxzyw wrote:
https://github.com/llvm/llvm-project/blob/62f737f7409b5d2b33c746158c62f14e5bb78aed/llvm/lib/Transforms/Utils/SimplifyCFG.cpp#L6516
We should allow truncations here.
```
; bin/opt -passes='simplifycfg' reduced.ll -S
target datalayout =
"e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:6
@@ -486,3 +486,15 @@ bool RISCVTargetInfo::validateCpuSupports(StringRef
Feature) const {
bool RISCVTargetInfo::isValidFeatureName(StringRef Name) const {
return llvm::RISCVISAInfo::isSupportedExtensionFeature(Name);
}
+
+bool RISCVTargetInfo::validateGlobalRegisterVariable(
https://github.com/dtcxzyw edited
https://github.com/llvm/llvm-project/pull/109596
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https://github.com/dtcxzyw approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/109596
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https://github.com/dtcxzyw approved this pull request.
Nice catch!
https://github.com/llvm/llvm-project/pull/109277
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dtcxzyw wrote:
> -fsanitize=address,fuzzer
I think it is not related to this patch. It only works with
`-fsanitize=builtin` or `-fsanitize=undefined`.
https://github.com/llvm/llvm-project/pull/104741
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https://github.com/dtcxzyw closed
https://github.com/llvm/llvm-project/pull/109088
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https://github.com/dtcxzyw closed
https://github.com/llvm/llvm-project/pull/104741
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https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/104741
>From fdadb0fdc2288b18d4dfe4f4510d057a7552ee39 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Mon, 19 Aug 2024 15:22:39 +0800
Subject: [PATCH 1/3] [UBSan] Diagnose assumption violation
---
clang/lib/CodeGe
https://github.com/dtcxzyw approved this pull request.
LGTM. Thank you!
https://github.com/llvm/llvm-project/pull/99620
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dtcxzyw wrote:
Missing fold: https://alive2.llvm.org/ce/z/2rmc3h
See
https://github.com/dtcxzyw/llvm-opt-benchmark/pull/1342#discussion_r1767033125
https://github.com/llvm/llvm-project/pull/99620
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https://github.com/llvm/llvm-project/pull/104741
>From fdadb0fdc2288b18d4dfe4f4510d057a7552ee39 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Mon, 19 Aug 2024 15:22:39 +0800
Subject: [PATCH 1/4] [UBSan] Diagnose assumption violation
---
clang/lib/CodeGe
https://github.com/dtcxzyw closed
https://github.com/llvm/llvm-project/pull/111837
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@@ -1898,6 +1882,56 @@ static Instruction *foldSelectICmpEq(SelectInst &SI,
ICmpInst *ICI,
return nullptr;
}
+/// Fold `X Pred C2 ? X BOp C1 : C2 BOp C1` to `min/max(X, C2) BOp C1`.
+/// This allows for better canonicalization.
+static Value *foldSelectWithConstOpToBinOp(IC
@@ -1898,6 +1882,56 @@ static Instruction *foldSelectICmpEq(SelectInst &SI,
ICmpInst *ICI,
return nullptr;
}
+/// Fold `X Pred C2 ? X BOp C1 : C2 BOp C1` to `min/max(X, C2) BOp C1`.
+/// This allows for better canonicalization.
+static Value *foldSelectWithConstOpToBinOp(IC
@@ -2011,8 +2011,9 @@ const StringMap sys::getHostCPUFeatures() {
const StringMap sys::getHostCPUFeatures() {
unsigned long hwcap = getauxval(AT_HWCAP);
bool HasFPU = hwcap & (1UL << 3); // HWCAP_LOONGARCH_FPU
- uint32_t cpucfg2 = 0x2;
+ const uint32_t cpucfg2 = 0x2, cpuc
https://github.com/dtcxzyw created
https://github.com/llvm/llvm-project/pull/109088
This patch removes unneeded enum `BuiltinCheckKind` and fixes a copy-paste
mistake in `__ubsan_handle_invalid_builtin`.
Address comment
https://github.com/llvm/llvm-project/pull/104741#discussion_r1764323722.
@@ -1875,13 +1873,17 @@ Instruction *InstCombinerImpl::visitFPTrunc(FPTruncInst
&FPT) {
// fptrunc (select Cond, (fpext X), Y --> select Cond, X, (fptrunc Y)
Value *NarrowY = Builder.CreateFPTrunc(Y, Ty);
Value *Sel = Builder.CreateSelect(Cond, X, NarrowY, "n
@@ -1875,13 +1873,17 @@ Instruction *InstCombinerImpl::visitFPTrunc(FPTruncInst
&FPT) {
// fptrunc (select Cond, (fpext X), Y --> select Cond, X, (fptrunc Y)
Value *NarrowY = Builder.CreateFPTrunc(Y, Ty);
Value *Sel = Builder.CreateSelect(Cond, X, NarrowY, "n
@@ -1898,6 +1882,55 @@ static Instruction *foldSelectICmpEq(SelectInst &SI,
ICmpInst *ICI,
return nullptr;
}
+// Turn select (Cmp X C1) (BOp X C2) C3
+// -> BOp (min/max X C1) C2
+// iff C3 == BOp C1 C2
+// Fold `select` with a const operand to a binary operation.
+// Thi
@@ -1182,6 +1182,10 @@ SelectPatternResult matchDecomposedSelectPattern(
/// minimum/maximum flavor.
CmpInst::Predicate getMinMaxPred(SelectPatternFlavor SPF, bool Ordered =
false);
+/// Convert given `SPF` to equivalent min/max intrinsic.
+/// Caller must ensure `SPF` is a m
@@ -1793,10 +1793,9 @@ define i32 @not_uadd_sat(i32 %x, i32 %y) {
define i32 @not_uadd_sat2(i32 %x, i32 %y) {
; CHECK-LABEL: @not_uadd_sat2(
-; CHECK-NEXT:[[A:%.*]] = add i32 [[X:%.*]], -2
-; CHECK-NEXT:[[C:%.*]] = icmp ugt i32 [[X]], 1
-; CHECK-NEXT:[[R:%.*]] = se
https://github.com/dtcxzyw edited
https://github.com/llvm/llvm-project/pull/116888
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@@ -1898,6 +1882,55 @@ static Instruction *foldSelectICmpEq(SelectInst &SI,
ICmpInst *ICI,
return nullptr;
}
+// Turn select (Cmp X C1) (BOp X C2) C3
dtcxzyw wrote:
```suggestion
/// Turn select (Cmp X C1) (BOp X C2) C3
```
Use `///` for header comments.
https://github.com/dtcxzyw approved this pull request.
LGTM. Thank you!
Please wait for additional approval from other reviewers :)
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https://github.com/dtcxzyw approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/119214
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@@ -1520,15 +1520,72 @@ ConstantRange ConstantRange::binaryNot() const {
return ConstantRange(APInt::getAllOnes(getBitWidth())).sub(*this);
}
+/// Estimate the 'bit-masked AND' operation's lower bound.
+///
+/// E.g., given two ranges as follows (single quotes are separators
@@ -1520,15 +1520,72 @@ ConstantRange ConstantRange::binaryNot() const {
return ConstantRange(APInt::getAllOnes(getBitWidth())).sub(*this);
}
+/// Estimate the 'bit-masked AND' operation's lower bound.
+///
+/// E.g., given two ranges as follows (single quotes are separators
@@ -1520,15 +1520,72 @@ ConstantRange ConstantRange::binaryNot() const {
return ConstantRange(APInt::getAllOnes(getBitWidth())).sub(*this);
}
+/// Estimate the 'bit-masked AND' operation's lower bound.
+///
+/// E.g., given two ranges as follows (single quotes are separators
https://github.com/dtcxzyw edited
https://github.com/llvm/llvm-project/pull/120352
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https://github.com/dtcxzyw approved this pull request.
LGTM. Thank you!
Please update the PR description and wait for additional approval from other
reviewers.
https://github.com/llvm/llvm-project/pull/120352
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@@ -1520,15 +1520,72 @@ ConstantRange ConstantRange::binaryNot() const {
return ConstantRange(APInt::getAllOnes(getBitWidth())).sub(*this);
}
+/// Estimate the 'bit-masked AND' operation's lower bound.
+///
+/// E.g., given two ranges as follows (single quotes are separators
https://github.com/dtcxzyw edited
https://github.com/llvm/llvm-project/pull/120712
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https://github.com/dtcxzyw approved this pull request.
LGTM. Thank you!
Please wait for additional approval from other reviewers :)
https://github.com/llvm/llvm-project/pull/120712
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@@ -0,0 +1,500 @@
+//===-- RISCVSchedGenericOOO.td - Generic O3 Processor -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,500 @@
+//===-- RISCVSchedGenericOOO.td - Generic O3 Processor -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/121958
>From c67349c8d79333d574a753d7afb10489cafb008d Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Tue, 7 Jan 2025 23:48:53 +0800
Subject: [PATCH 1/4] [InstCombine] Add pre-commit tests. NFC.
---
llvm/test/Tran
https://github.com/dtcxzyw approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/119225
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dtcxzyw wrote:
> Seems that this change causes Segment Fault on multiple targets including
> aarch64, loongarch64 and riscv64.
>
> This is detected by a LoongArch
> [buildbot](https://lab.llvm.org/staging/#/builders/20/builds/6282) and
> manually checked on aarch64 and riscv64 QEMUs.
>
> I w
dtcxzyw wrote:
> huffbench.c:319:10: runtime error: left shift of negative value -93
SUMMARY: UndefinedBehaviorSanitizer: undefined-behavior huffbench.c:319:10
https://github.com/llvm/llvm-project/pull/119225
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https://github.com/dtcxzyw edited
https://github.com/llvm/llvm-project/pull/120352
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@@ -1520,15 +1520,102 @@ ConstantRange ConstantRange::binaryNot() const {
return ConstantRange(APInt::getAllOnes(getBitWidth())).sub(*this);
}
+/// Estimate the 'bit-masked AND' operation's lower bound.
+///
+/// E.g., given two ranges as follows (single quotes are separator
@@ -1520,15 +1520,102 @@ ConstantRange ConstantRange::binaryNot() const {
return ConstantRange(APInt::getAllOnes(getBitWidth())).sub(*this);
}
+/// Estimate the 'bit-masked AND' operation's lower bound.
+///
+/// E.g., given two ranges as follows (single quotes are separator
@@ -1520,15 +1520,102 @@ ConstantRange ConstantRange::binaryNot() const {
return ConstantRange(APInt::getAllOnes(getBitWidth())).sub(*this);
}
+/// Estimate the 'bit-masked AND' operation's lower bound.
+///
+/// E.g., given two ranges as follows (single quotes are separator
https://github.com/dtcxzyw commented:
Please give me more time to understand the implementation...
https://github.com/llvm/llvm-project/pull/120352
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@@ -1520,15 +1520,102 @@ ConstantRange ConstantRange::binaryNot() const {
return ConstantRange(APInt::getAllOnes(getBitWidth())).sub(*this);
}
+/// Estimate the 'bit-masked AND' operation's lower bound.
+///
+/// E.g., given two ranges as follows (single quotes are separator
@@ -1520,15 +1520,102 @@ ConstantRange ConstantRange::binaryNot() const {
return ConstantRange(APInt::getAllOnes(getBitWidth())).sub(*this);
}
+/// Estimate the 'bit-masked AND' operation's lower bound.
+///
+/// E.g., given two ranges as follows (single quotes are separator
dtcxzyw wrote:
> I'd have expected the simplest case to be solved suboptimally with a few
> range intersections in ValueTracking, but this seems like a nice extension,
> if that's the appropriate direction and compile-time acceptable.
This patch increases the compile time by ~0.02%. It should
@@ -1520,15 +1520,101 @@ ConstantRange ConstantRange::binaryNot() const {
return ConstantRange(APInt::getAllOnes(getBitWidth())).sub(*this);
}
+/// Estimate the 'bit-masked AND' operation's lower bound.
+///
+/// E.g., given two ranges as follows (single quotes are separator
dtcxzyw wrote:
> I'm thinking if I need to add a new test mode to test the optimal lower
> (upper) bound only for AND (OR).
If you cannot make it optimal for all non-wrapped cases, please just add some
special cases (e.g., `[7, 14) & [-1, 0) = [7, 14)`) before
`TestBinaryOpExhaustive`.
htt
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