@@ -1612,6 +1613,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-SUPM-EXT %s
// CHECK-SUPM-EXT: __riscv_supm 8000{{$}}
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_ssqosid1p0 -E -dM %s \
+// RUN: -o - | FileCheck --check-p
dtcxzyw wrote:
Ping?
https://github.com/llvm/llvm-project/pull/68882
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dtcxzyw wrote:
> I guess Zaamo + Zacas is technically a way one could implement atomics
> without LR/SC?
The Zacas extension depends upon the A extension.
https://github.com/llvm/llvm-project/pull/77424
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@@ -6411,6 +6411,41 @@ static Value *simplifyBinaryIntrinsic(Function *F, Value
*Op0, Value *Op1,
return Constant::getNullValue(ReturnType);
break;
}
+ case Intrinsic::ptrmask: {
+if (isa(Op0) || isa(Op1))
+ return PoisonValue::get(Op0->getType());
+
+
dtcxzyw wrote:
Ping.
https://github.com/llvm/llvm-project/pull/67917
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dtcxzyw wrote:
Ping.
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dtcxzyw wrote:
@nikic Any comments about this PR?
https://github.com/llvm/llvm-project/pull/67917
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dtcxzyw wrote:
@nikic Any comments about this PR?
https://github.com/llvm/llvm-project/pull/67917
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https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/69252
>From 8f0ebe5b5cfed069c8274c0761559d6595d4dea8 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Tue, 17 Oct 2023 05:17:17 +0800
Subject: [PATCH 1/3] [Clang] Add pre-commit tests for PR69218. NFC.
---
clang/te
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/69252
>From 8f0ebe5b5cfed069c8274c0761559d6595d4dea8 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Tue, 17 Oct 2023 05:17:17 +0800
Subject: [PATCH 1/3] [Clang] Add pre-commit tests for PR69218. NFC.
---
clang/te
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/69252
>From 6e34e74e8e8046aaa086869e8a8aecb781dd3b3b Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Tue, 17 Oct 2023 05:17:17 +0800
Subject: [PATCH 1/3] [Clang] Add pre-commit tests for PR69218. NFC.
---
clang/te
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https://github.com/dtcxzyw created
https://github.com/llvm/llvm-project/pull/70232
[XiangShan](https://github.com/OpenXiangShan/XiangShan) is an open-source
high-performance RISC-V processor.
This PR adds the schedule model for XiangShan-NanHu, the 2nd Gen core of the
XiangShan processor seri
@@ -302,7 +302,7 @@ def FSW : FPStore_r<0b010, "fsw", FPR32, WriteFST32>;
} // Predicates = [HasStdExtF]
foreach Ext = FExts in {
- let SchedRW = [WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32] in {
+ let SchedRW = [WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32Addend] in {
-
https://github.com/dtcxzyw created
https://github.com/llvm/llvm-project/pull/70294
This PR adds the processor definition for XiangShan-NanHu, an open-source
high-performance RISC-V processor.
According to the official
[documentation](https://xiangshan-doc.readthedocs.io/zh-cn/latest/arch/), N
dtcxzyw wrote:
> Can you separate out the basic processor definition (using NoSchedModel), and
> a patch which adds the scheduling model? We can at least get the processor
> definition landed while we iterate on the scheduling related pieces.
>
> edit: For clarity, I'm requesting that the basi
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/70294
>From a4e46c81c5235754bf7b4e0b3dd3ff8805b3e56d Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Thu, 26 Oct 2023 13:47:39 +0800
Subject: [PATCH 1/2] [RISCV] Add processor definition for XiangShan-NanHu
Co-auth
@@ -20,6 +20,17 @@
// MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+zicsr" "-target-feature"
"+zifencei"
// MCPU-SYNTACORE-SCR1-MAX: "-target-abi" "ilp32"
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=xiangshan-nanhu |
FileCheck -check-prefix=MCPU-XIANGSHAN-NANHU %s
dtcxzyw wrote:
> LGTM in general, except one question: will zicbom and zicboz be in the final
> RTL?
You can find the full implementation of `zicbom` and `zicboz` here:
https://github.com/OpenXiangShan/XiangShan/commit/ca18a0b47b0e4089fd0dd1c085091cb90bf98f25.
cc @poemonsense
https://github.
dtcxzyw wrote:
Any more questions about XiangShan? If there is no question, I will merge this
PR tomorrow.
https://github.com/llvm/llvm-project/pull/70294
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@@ -6380,7 +6380,56 @@ Instruction
*InstCombinerImpl::foldICmpUsingBoolRange(ICmpInst &I) {
Y->getType()->isIntOrIntVectorTy(1) && Pred == ICmpInst::ICMP_ULE)
return BinaryOperator::CreateOr(Builder.CreateIsNull(X), Y);
+ ICmpInst::Predicate Pred1, Pred2;
const
https://github.com/dtcxzyw updated
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>From d9d8bcbb98e8f5aecb9733329389d61a489bd731 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 23:07:29 +0800
Subject: [PATCH 1/5] [InstCombine] Simplify the pattern `a ne/eq (zext (a
ne/eq c)
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https://github.com/llvm/llvm-project/pull/65852
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@@ -366,19 +366,10 @@ define void @simplify_before_foldAndOfICmps(ptr %p) {
; CHECK-LABEL: @simplify_before_foldAndOfICmps(
; CHECK-NEXT:[[A8:%.*]] = alloca i16, align 2
; CHECK-NEXT:[[L7:%.*]] = load i16, ptr [[A8]], align 2
-; CHECK-NEXT:[[TMP1:%.*]] = icmp eq i16
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>From d9d8bcbb98e8f5aecb9733329389d61a489bd731 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 23:07:29 +0800
Subject: [PATCH 1/6] [InstCombine] Simplify the pattern `a ne/eq (zext (a
ne/eq c)
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/65852
>From d9d8bcbb98e8f5aecb9733329389d61a489bd731 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 23:07:29 +0800
Subject: [PATCH 1/6] [InstCombine] Simplify the pattern `a ne/eq (zext (a
ne/eq c)
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dtcxzyw wrote:
Ping.
https://github.com/llvm/llvm-project/pull/65910
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dtcxzyw wrote:
Ping.
https://github.com/llvm/llvm-project/pull/65910
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dtcxzyw wrote:
> We should use rebase instead of merge. And I recommend force push to change
> the code before the review starts.
I am confused with the LLVM GitHub user guide. I witnessed someone mess up by
doing rebase + force push.
Examples: #65853 #65543 #65535
https://github.com/llvm/ll
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>From 85f7911dfe0f1e9112881a9f503bcd68edfde580 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Tue, 19 Sep 2023 10:19:46 +0800
Subject: [PATCH 1/3] [InstCombine] Canonicalize `and(zext(A), B)` into `select
A,
https://github.com/dtcxzyw edited
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dtcxzyw wrote:
> You might want to check whether this also fixes #66740 and if so add a test.
Confirmed. I have added a pre-commit test for 66733 in
1a73a6b80b54cd23ee8380c6fa3304847e5cb5d1.
https://github.com/llvm/llvm-project/pull/66740
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dtcxzyw wrote:
> You might want to check whether this also fixes #66740 and if so add a test.
Confirmed. I have added a pre-commit test for 66733 in
1a73a6b80b54cd23ee8380c6fa3304847e5cb5d1.
https://github.com/llvm/llvm-project/pull/66740
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dtcxzyw wrote:
To avoid backend regressions, I will merge this PR after #66793.
https://github.com/llvm/llvm-project/pull/66740
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@@ -1964,18 +1964,78 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst
&CI) {
break;
}
case Intrinsic::ptrmask: {
+KnownBits Known(DL.getPointerTypeSizeInBits(II->getType()));
+if (SimplifyDemandedInstructionBits(*II, Known))
+ return II;
+
+Val
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/65910
>From 9bb817aa40dd9bc1bbb18b4cf4bc079145c8ecaa Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Mon, 11 Sep 2023 03:58:02 +0800
Subject: [PATCH 1/2] [ValueTracking] Simplify uaddo pattern
---
llvm/lib/Analysi
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/65910
>From 9bb817aa40dd9bc1bbb18b4cf4bc079145c8ecaa Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Mon, 11 Sep 2023 03:58:02 +0800
Subject: [PATCH 1/2] [ValueTracking] Simplify uaddo pattern
---
llvm/lib/Analysi
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@@ -8291,6 +8291,29 @@ static std::optional isImpliedCondICmps(const
ICmpInst *LHS,
if (L0 == R0 && match(L1, m_APInt(LC)) && match(R1, m_APInt(RC)))
return isImpliedCondCommonOperandWithConstants(LPred, *LC, RPred, *RC);
+ // L0 = R0 = L1 + R1, L0 >=u L1 implies R0 >=
@@ -8291,6 +8291,29 @@ static std::optional isImpliedCondICmps(const
ICmpInst *LHS,
if (L0 == R0 && match(L1, m_APInt(LC)) && match(R1, m_APInt(RC)))
return isImpliedCondCommonOperandWithConstants(LPred, *LC, RPred, *RC);
+ // L0 = R0 = L1 + R1, L0 >=u L1 implies R0 >=
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>From d9d8bcbb98e8f5aecb9733329389d61a489bd731 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 23:07:29 +0800
Subject: [PATCH 1/7] [InstCombine] Simplify the pattern `a ne/eq (zext (a
ne/eq c)
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/65852
>From d9d8bcbb98e8f5aecb9733329389d61a489bd731 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 23:07:29 +0800
Subject: [PATCH 1/7] [InstCombine] Simplify the pattern `a ne/eq (zext (a
ne/eq c)
https://github.com/dtcxzyw resolved
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@@ -8291,6 +8291,29 @@ static std::optional isImpliedCondICmps(const
ICmpInst *LHS,
if (L0 == R0 && match(L1, m_APInt(LC)) && match(R1, m_APInt(RC)))
return isImpliedCondCommonOperandWithConstants(LPred, *LC, RPred, *RC);
+ // L0 = R0 = L1 + R1, L0 >=u L1 implies R0 >=
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https://github.com/llvm/llvm-project/pull/65852
>From d9d8bcbb98e8f5aecb9733329389d61a489bd731 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 23:07:29 +0800
Subject: [PATCH 1/8] [InstCombine] Simplify the pattern `a ne/eq (zext (a
ne/eq c)
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/65852
>From d9d8bcbb98e8f5aecb9733329389d61a489bd731 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 23:07:29 +0800
Subject: [PATCH 1/8] [InstCombine] Simplify the pattern `a ne/eq (zext (a
ne/eq c)
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>From 2fe5756dd4d49580d3a23b0ff1b72535f725915e Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Mon, 11 Sep 2023 15:51:46 +0800
Subject: [PATCH 1/4] [RISCV] Eliminate dead li after emitting VSETVLIs
---
llvm/
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/65934
>From 2fe5756dd4d49580d3a23b0ff1b72535f725915e Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Mon, 11 Sep 2023 15:51:46 +0800
Subject: [PATCH 1/4] [RISCV] Eliminate dead li after emitting VSETVLIs
---
llvm/
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@@ -757,7 +757,8 @@ class RISCVInsertVSETVLI : public MachineFunctionPass {
bool computeVLVTYPEChanges(const MachineBasicBlock &MBB,
VSETVLIInfo &Info) const;
void computeIncomingVLVTYPE(const MachineBasicBlock &MBB);
- void emitVSETVLIs(Machin
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@@ -757,7 +757,8 @@ class RISCVInsertVSETVLI : public MachineFunctionPass {
bool computeVLVTYPEChanges(const MachineBasicBlock &MBB,
VSETVLIInfo &Info) const;
void computeIncomingVLVTYPE(const MachineBasicBlock &MBB);
- void emitVSETVLIs(Machin
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>From 85f7911dfe0f1e9112881a9f503bcd68edfde580 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Tue, 19 Sep 2023 10:19:46 +0800
Subject: [PATCH 1/3] [InstCombine] Canonicalize `and(zext(A), B)` into `select
A,
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Ping.
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>From 2fe5756dd4d49580d3a23b0ff1b72535f725915e Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Mon, 11 Sep 2023 15:51:46 +0800
Subject: [PATCH 1/4] [RISCV] Eliminate dead li after emitting VSETVLIs
---
llvm/
@@ -6380,7 +6380,71 @@ Instruction
*InstCombinerImpl::foldICmpUsingBoolRange(ICmpInst &I) {
Y->getType()->isIntOrIntVectorTy(1) && Pred == ICmpInst::ICMP_ULE)
return BinaryOperator::CreateOr(Builder.CreateIsNull(X), Y);
+ // icmp eq/ne X, (zext/sext (icmp eq/ne X,
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/65852
>From d9d8bcbb98e8f5aecb9733329389d61a489bd731 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 23:07:29 +0800
Subject: [PATCH 1/9] [InstCombine] Simplify the pattern `a ne/eq (zext (a
ne/eq c)
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/65852
>From d9d8bcbb98e8f5aecb9733329389d61a489bd731 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 23:07:29 +0800
Subject: [PATCH 1/9] [InstCombine] Simplify the pattern `a ne/eq (zext (a
ne/eq c)
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/65852
>From d9d8bcbb98e8f5aecb9733329389d61a489bd731 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 23:07:29 +0800
Subject: [PATCH 1/9] [InstCombine] Simplify the pattern `a ne/eq (zext (a
ne/eq c)
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/65852
>From d9d8bcbb98e8f5aecb9733329389d61a489bd731 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 23:07:29 +0800
Subject: [PATCH 1/9] [InstCombine] Simplify the pattern `a ne/eq (zext (a
ne/eq c)
dtcxzyw wrote:
Ping.
https://github.com/llvm/llvm-project/pull/65934
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dtcxzyw wrote:
Ping.
https://github.com/llvm/llvm-project/pull/65852
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dtcxzyw wrote:
Ping.
https://github.com/llvm/llvm-project/pull/65852
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https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/67915
>From c4ce28c942c172e5646b5922f0b02b4169197840 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sun, 1 Oct 2023 21:52:47 +0800
Subject: [PATCH] [InstCombine] Canonicalize `(X +/- Y) & Y` into `~X & Y` when
Y i
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/67917
>From b5d134c88a04c524b1d9120a1c1a5dae3722904c Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sun, 1 Oct 2023 22:17:35 +0800
Subject: [PATCH 1/2] [ConstantRange] Handle `Intrinsic::cttz` and
`Intrinsic::ctpo
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/67917
>From b5d134c88a04c524b1d9120a1c1a5dae3722904c Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sun, 1 Oct 2023 22:17:35 +0800
Subject: [PATCH 1/2] [ConstantRange] Handle `Intrinsic::cttz` and
`Intrinsic::ctpo
https://github.com/dtcxzyw edited
https://github.com/llvm/llvm-project/pull/67917
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https://github.com/dtcxzyw edited
https://github.com/llvm/llvm-project/pull/67917
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https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/67917
>From b5d134c88a04c524b1d9120a1c1a5dae3722904c Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sun, 1 Oct 2023 22:17:35 +0800
Subject: [PATCH 1/3] [ConstantRange] Handle `Intrinsic::cttz` and
`Intrinsic::ctpo
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/67917
>From b5d134c88a04c524b1d9120a1c1a5dae3722904c Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sun, 1 Oct 2023 22:17:35 +0800
Subject: [PATCH 1/3] [ConstantRange] Handle `Intrinsic::cttz` and
`Intrinsic::ctpo
https://github.com/dtcxzyw edited
https://github.com/llvm/llvm-project/pull/67917
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@@ -1735,6 +1746,122 @@ ConstantRange ConstantRange::ctlz(bool ZeroIsPoison)
const {
return getNonEmpty(APInt(getBitWidth(), getUnsignedMax().countl_zero()),
APInt(getBitWidth(), getUnsignedMin().countl_zero() + 1));
}
+static ConstantRange getUnsignedCo
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