Author: Yaxun (Sam) Liu
Date: 2021-01-06T16:23:01-05:00
New Revision: 90bf3ecef4bb1e214a718aebcee730c24199c8ba
URL:
https://github.com/llvm/llvm-project/commit/90bf3ecef4bb1e214a718aebcee730c24199c8ba
DIFF:
https://github.com/llvm/llvm-project/commit/90bf3ecef4bb1e214a718aebcee730c24199c8ba.dif
Author: Yaxun (Sam) Liu
Date: 2021-10-13T15:01:07-04:00
New Revision: 1439df00fc5e6dfffeb6a99e3537f6de2e539785
URL:
https://github.com/llvm/llvm-project/commit/1439df00fc5e6dfffeb6a99e3537f6de2e539785
DIFF:
https://github.com/llvm/llvm-project/commit/1439df00fc5e6dfffeb6a99e3537f6de2e539785.dif
Author: Yaxun (Sam) Liu
Date: 2021-10-25T11:07:40-04:00
New Revision: a5435844f0e67c70963a1a743fef41b1a8eac4d3
URL:
https://github.com/llvm/llvm-project/commit/a5435844f0e67c70963a1a743fef41b1a8eac4d3
DIFF:
https://github.com/llvm/llvm-project/commit/a5435844f0e67c70963a1a743fef41b1a8eac4d3.dif
Author: Yaxun (Sam) Liu
Date: 2021-09-08T13:45:26-04:00
New Revision: 26e492e134c006c63b3d9f9f9eabdeba014b1d2c
URL:
https://github.com/llvm/llvm-project/commit/26e492e134c006c63b3d9f9f9eabdeba014b1d2c
DIFF:
https://github.com/llvm/llvm-project/commit/26e492e134c006c63b3d9f9f9eabdeba014b1d2c.dif
Author: Yaxun (Sam) Liu
Date: 2021-09-15T13:03:57-04:00
New Revision: ab5f2b505a0751bce41f4cec9afa3c1541d485d0
URL:
https://github.com/llvm/llvm-project/commit/ab5f2b505a0751bce41f4cec9afa3c1541d485d0
DIFF:
https://github.com/llvm/llvm-project/commit/ab5f2b505a0751bce41f4cec9afa3c1541d485d0.dif
https://github.com/yxsamliu created
https://github.com/llvm/llvm-project/pull/104638
For -fgpu-rdc linking, clang needs to collect undefined fatbin symbols and
resolve them to the embedded fatbin.
This has been done for object files and archive files passed as input files to
clang.
However,
@@ -76,8 +79,75 @@ class HIPUndefinedFatBinSymbols {
return GPUBinHandleSymbols;
}
+ // Collect symbols from static libraries specified by -l options.
+ void processStaticLibraries() {
+llvm::SmallVector LibNames;
+llvm::SmallVector LibPaths;
+llvm::SmallVe
@@ -76,8 +79,75 @@ class HIPUndefinedFatBinSymbols {
return GPUBinHandleSymbols;
}
+ // Collect symbols from static libraries specified by -l options.
+ void processStaticLibraries() {
+llvm::SmallVector LibNames;
+llvm::SmallVector LibPaths;
+llvm::SmallVe
https://github.com/yxsamliu updated
https://github.com/llvm/llvm-project/pull/104638
>From 3c281d8cfc99674f2a4de0dfe5e1f02e35e68d6d Mon Sep 17 00:00:00 2001
From: "Yaxun (Sam) Liu"
Date: Fri, 16 Aug 2024 14:24:08 -0400
Subject: [PATCH] [HIP] search fatbin symbols for libs passed by -l
For -fgp
https://github.com/yxsamliu updated
https://github.com/llvm/llvm-project/pull/104638
>From 6e6bb355f2cf79f30d01c97b580d4354cbb7e727 Mon Sep 17 00:00:00 2001
From: "Yaxun (Sam) Liu"
Date: Fri, 16 Aug 2024 14:24:08 -0400
Subject: [PATCH] [HIP] search fatbin symbols for libs passed by -l
For -fgp
https://github.com/yxsamliu closed
https://github.com/llvm/llvm-project/pull/104638
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https://github.com/llvm/llvm-project/pull/102776
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yxsamliu wrote:
ping
https://github.com/llvm/llvm-project/pull/101350
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@@ -169,6 +180,11 @@
// COMMON-UNSAFE-MATH-SAME: "-mlink-builtin-bitcode"
"{{.*}}/amdgcn/bitcode/oclc_finite_only_off.bc"
// COMMON-UNSAFE-MATH-SAME: "-mlink-builtin-bitcode"
"{{.*}}/amdgcn/bitcode/oclc_correctly_rounded_sqrt_off.bc"
+// ASAN-SAME: "-fsanitize=address"
+
+//
https://github.com/yxsamliu closed
https://github.com/llvm/llvm-project/pull/96262
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@@ -147,6 +147,14 @@ getNVIDIAOffloadTargetTriple(const Driver &D, const
ArgList &Args,
static std::optional
getHIPOffloadTargetTriple(const Driver &D, const ArgList &Args) {
if (!Args.hasArg(options::OPT_offload_EQ)) {
+auto OffloadArchs = Args.getAllArgValues(options::
@@ -147,6 +147,14 @@ getNVIDIAOffloadTargetTriple(const Driver &D, const
ArgList &Args,
static std::optional
getHIPOffloadTargetTriple(const Driver &D, const ArgList &Args) {
if (!Args.hasArg(options::OPT_offload_EQ)) {
+auto OffloadArchs = Args.getAllArgValues(options::
@@ -158,23 +158,85 @@ void test_ds_faddf(local float *out, float src) {
}
// CHECK-LABEL: @test_ds_fmin
-// CHECK: {{.*}}call{{.*}} float @llvm.amdgcn.ds.fmin.f32(ptr addrspace(3)
%out, float %src, i32 0, i32 0, i1 false)
+// CHECK: atomicrmw fmin ptr addrspace(3) %out, float
@@ -0,0 +1,77 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 5
+// RUN: %clang_cc1 -triple nvptx64-nvidia-cuda -emit-llvm -o - %s | FileCheck
%s
+
+extern void varargs_simple(int, ...);
+
+// CHECK-LABEL: define dso_local vo
@@ -0,0 +1,77 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 5
+// RUN: %clang_cc1 -triple nvptx64-nvidia-cuda -emit-llvm -o - %s | FileCheck
%s
+
+extern void varargs_simple(int, ...);
+
+// CHECK-LABEL: define dso_local vo
@@ -284,3 +284,48 @@ Example Usage
Base* basePtr = &obj;
basePtr->virtualFunction(); // Allowed since obj is constructed in
device code
}
+
+SPIR-V Support on HIPAMD ToolChain
+==
+
+The HIPAMD ToolChain supports targetting
+`AMDG
@@ -284,3 +284,48 @@ Example Usage
Base* basePtr = &obj;
basePtr->virtualFunction(); // Allowed since obj is constructed in
device code
}
+
+SPIR-V Support on HIPAMD ToolChain
+==
+
+The HIPAMD ToolChain supports targetting
+`AMDG
https://github.com/yxsamliu approved this pull request.
https://github.com/llvm/llvm-project/pull/95957
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https://github.com/llvm/llvm-project/pull/96951
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https://github.com/yxsamliu approved this pull request.
LGTM. Thanks
https://github.com/llvm/llvm-project/pull/107458
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https://github.com/llvm/llvm-project/pull/107734
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@@ -16,15 +18,15 @@
// RUN: %clang -### -x hip --target=x86_64-unknown-linux-gnu -DX=1
--no-offload-new-driver \
// RUN: --offload-arch=gfx906 -c -nogpuinc -nogpulib -fuse-cuid=hash \
-// RUN: %S/Inputs/hip_multiple_inputs/a.cu >%t.out 2>&1
+// RUN: Inputs/hip_multiple_
yxsamliu wrote:
This does not seem to be the right fix. I tends to think the test
https://github.com/ROCm/hip-tests/tree/amd-staging/samples/2_Cookbook/16_assembly_to_executable
needs fix. Since it does not expect host-only compilation to use CUID, it
should add `-fuse-cuid=none` to the host-o
yxsamliu wrote:
yet another usage of mixed signed/unsigned min
https://github.com/ROCm/hipBLASLt/issues/1227
https://github.com/llvm/llvm-project/pull/82956
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yxsamliu wrote:
> This needs some sema type restrictions to make sure it's something sensible
+1 also need sema lit test
https://github.com/llvm/llvm-project/pull/112447
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https://github.com/yxsamliu approved this pull request.
https://github.com/llvm/llvm-project/pull/112412
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yxsamliu wrote:
> > This does not seem to be the right fix. I tends to think the test
> > https://github.com/ROCm/hip-tests/tree/amd-staging/samples/2_Cookbook/16_assembly_to_executable
> > needs fix. Since it does not expect host-only compilation to use CUID, it
> > should add `-fuse-cuid=non
https://github.com/yxsamliu approved this pull request.
https://github.com/llvm/llvm-project/pull/113335
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yxsamliu wrote:
ping
https://github.com/llvm/llvm-project/pull/101350
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yxsamliu wrote:
As discussed in the RFC at LLVM discourse, close this PR and open another PR
for implementing it as a compound statement attribute
https://github.com/llvm/llvm-project/pull/114841
https://github.com/llvm/llvm-project/pull/102569
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https://github.com/yxsamliu closed
https://github.com/llvm/llvm-project/pull/102569
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https://github.com/yxsamliu approved this pull request.
https://github.com/llvm/llvm-project/pull/113509
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@@ -1450,6 +1450,13 @@ def CUDAHost : InheritableAttr {
}
def : MutualExclusions<[CUDAGlobal, CUDAHost]>;
+def CUDAGridConstant : InheritableAttr {
+ let Spellings = [GNU<"grid_constant">, Declspec<"__grid_constant__">];
+ let Subjects = SubjectList<[ParmVar]>;
+ let LangOp
yxsamliu wrote:
LGTM
https://github.com/llvm/llvm-project/pull/115545
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yxsamliu wrote:
> Is this still relevant?
Yes. The issue still exists and my arguments still hold
https://github.com/llvm/llvm-project/pull/67721
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yxsamliu wrote:
> Thank you ever so much for the review @VyacheslavLevytskyy! I will create a
> PR for the Translator as well, since there's some handling missing there; I
> will refer to it here for future readers. Final check: are you OK with the
> OpenCL changes @yxsamliu?
LGTM
https://gi
yxsamliu wrote:
> It has nothing to do with writing to those arrays while the kernel is
> running. That would indeed be UB.
>
> > both would still work just the same even with this change,
>
> No, they will not. Here's the demonstration of the behavior change that
> `const` brings to the tabl
yxsamliu wrote:
`__AMDGCN_WAVEFRONT_SIZE__` could also be used in other offloading languages
e.g. OpenMP. The check for non-constantness is not specific to HIP.
It is a constant when the triple is amdgcn and -target-cpu is specified.
Otherwise it should not be treated as constant.
I think you
yxsamliu wrote:
One drawback of not defining `__AMDGCN_WAVEFRONT_SIZE__` in host compilation is
the impairment of uniformity of source code across host and device sides. Users
have to put `#if __HIP_DEVICE_COMPILE__` anywhere they use
`__AMDGCN_WAVEFRONT_SIZE__`. Previous experience tells us t
@@ -0,0 +1,19 @@
+//===--- AtomicOptions.def - Atomic Options database -*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -569,19 +569,21 @@ void AMDGPUTargetCodeGenInfo::setTargetAtomicMetadata(
AtomicInst.setMetadata(llvm::LLVMContext::MD_noalias_addrspace, ASRange);
}
- if (!RMW || !CGF.getTarget().allowAMDGPUUnsafeFPAtomics())
+ if (!RMW)
return;
- // TODO: Introduce new, m
@@ -0,0 +1,30 @@
+// RUN: %clang_cc1 -fsyntax-only -verify %s
+// RUN: %clang_cc1 -fsyntax-only -verify -fcuda-is-device %s
+// RUN: %clang_cc1 -fsyntax-only -verify -fcuda-is-device %s \
+// RUN:
-fatomic=no_fine_grained_memory:off,no_remote_memory:on,ignore_denormal_mode:on
+
@@ -0,0 +1,30 @@
+// RUN: %clang_cc1 -fsyntax-only -verify %s
+// RUN: %clang_cc1 -fsyntax-only -verify -fcuda-is-device %s
+// RUN: %clang_cc1 -fsyntax-only -verify -fcuda-is-device %s \
+// RUN:
-fatomic=no_fine_grained_memory:off,no_remote_memory:on,ignore_denormal_mode:on
+
@@ -1093,6 +1097,169 @@ inline void FPOptions::applyChanges(FPOptionsOverride
FPO) {
*this = FPO.applyOverrides(*this);
}
+/// Atomic control options
+class AtomicOptionsOverride;
+class AtomicOptions {
+public:
+ using storage_type = uint16_t;
+
+ static constexpr unsign
https://github.com/yxsamliu approved this pull request.
https://github.com/llvm/llvm-project/pull/113614
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https://github.com/yxsamliu approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/111890
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yxsamliu wrote:
> I feel like this is a workaround. Can we not fix the "limitation of the
> driver" and if there is an issue with HSA overhead, shouldn't we file a
> ticket?
I think there was already a ticket but it cannot be fixed easily.
https://github.com/llvm/llvm-project/pull/116651
yxsamliu wrote:
I think we could use this approach for Linux. amdgpu-arch can still use HIP
runtime to detect GPU for both Linux and Windows, so we still have a fallback
even if we remove the HSA approach.
https://github.com/llvm/llvm-project/pull/116651
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yxsamliu wrote:
> > reqd_work_group_size is for OpenCL reqd_work_group_size attribute and it
> > sets exact block size. amdgpu-flat-work-group-size sets a (min, max) range
> > for block size.
> > HIP launch bounds sets a block size range (1, bound). It cannot be
> > represented by reqd_work_gr
yxsamliu wrote:
> > > > reqd_work_group_size is for OpenCL reqd_work_group_size attribute and
> > > > it sets exact block size. amdgpu-flat-work-group-size sets a (min, max)
> > > > range for block size.
> > > > HIP launch bounds sets a block size range (1, bound). It cannot be
> > > > represe
yxsamliu wrote:
> > > @jhuber6 can you comment on "lot of overhead" and if that matters? Also,
> > > not sure why the HSA library dependence is a problem. This seems to be
> > > exposing amdgpu-arch to more maintenance overhead.
> >
> >
> > Sometimes the driver will hang and since this is use
https://github.com/yxsamliu approved this pull request.
https://github.com/llvm/llvm-project/pull/116226
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yxsamliu wrote:
> @yxsamliu -- should I add it for HIP, too?
Yes please. I would appreciate that. Thanks.
https://github.com/llvm/llvm-project/pull/117074
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@@ -6405,7 +6424,12 @@ const ToolChain &Driver::getToolChain(const ArgList
&Args,
TC = std::make_unique(*this, Target, Args);
break;
case llvm::Triple::AMDHSA:
- TC = std::make_unique(*this, Target, Args);
+ TC =
+ llvm::any_of(Inputs,
+
@@ -6405,7 +6424,12 @@ const ToolChain &Driver::getToolChain(const ArgList
&Args,
TC = std::make_unique(*this, Target, Args);
break;
case llvm::Triple::AMDHSA:
- TC = std::make_unique(*this, Target, Args);
+ TC =
+ llvm::any_of(Inputs,
+
https://github.com/yxsamliu approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/116820
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https://github.com/yxsamliu edited
https://github.com/llvm/llvm-project/pull/121986
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https://github.com/yxsamliu created
https://github.com/llvm/llvm-project/pull/121986
In C++20 constexpr virtual function is allowed. In C++17 although non-pure
virtual function is not allowed to be constexpr, pure virtual function is
allowed to be constexpr and is allowed to be overriden by no
yxsamliu wrote:
> _ No description provided. _
Pls add a commit message about the issue this PR is addressing and a summary of
what it does.
https://github.com/llvm/llvm-project/pull/124989
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http
@@ -0,0 +1,41 @@
+// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -target-cpu
gfx942 \
+// RUN: -emit-llvm -xhip %s -o - | FileCheck %s --check-prefix=GCN
+// RUN: %clang_cc1 -fcuda-is-device -triple spirv64-amd-amdhsa \
+// RUN: -emit-llvm -xhip %s -o - | FileC
@@ -1,64 +1,40 @@
-// RUN: %clang_cc1 -triple aarch64 -verify=expected,aarch64 -fsyntax-only %s
+// RUN: %clang_cc1 -triple aarch64 -verify=expected,unsupported -fsyntax-only
%s
// RUN: %clang_cc1 -triple loongarch64 -verify=expected,loongarch64
-fsyntax-only %s
-// RUN: %clang
@@ -2949,15 +2950,32 @@ static void handleSectionAttr(Sema &S, Decl *D, const
ParsedAttr &AL) {
}
}
+static bool isValidCodeModelAttr(Sema &S, StringRef Str) {
+ if (S.Context.getTargetInfo().getTriple().isLoongArch()) {
+return Str == "normal" || Str == "medium" || St
@@ -1115,14 +1117,13 @@ def fno_convergent_functions : Flag<["-"],
"fno-convergent-functions">,
// Common offloading options
let Group = offload_Group in {
-def offload_arch_EQ : Joined<["--"], "offload-arch=">, Flags<[NoXarchOption]>,
yxsamliu wrote:
For HI
@@ -1106,8 +1106,12 @@ bool AMDGPUToolChain::shouldSkipSanitizeOption(
// For simplicity, we only allow -fsanitize=address
SanitizerMask K = parseSanitizerValue(A->getValue(), /*AllowGroups=*/false);
- if (K != SanitizerKind::Address)
+ if (K != SanitizerKind::Address) {
@@ -0,0 +1,19 @@
+//===--- AtomicOptions.def - Atomic Options database -*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -1096,6 +1100,177 @@ inline void FPOptions::applyChanges(FPOptionsOverride
FPO) {
*this = FPO.applyOverrides(*this);
}
+/// Atomic control options
+class AtomicOptionsOverride;
+class AtomicOptions {
+public:
+ using storage_type = uint16_t;
+
+ static constexpr unsign
@@ -1096,6 +1100,177 @@ inline void FPOptions::applyChanges(FPOptionsOverride
FPO) {
*this = FPO.applyOverrides(*this);
}
+/// Atomic control options
+class AtomicOptionsOverride;
+class AtomicOptions {
+public:
+ using storage_type = uint16_t;
+
+ static constexpr unsign
@@ -1115,14 +1117,13 @@ def fno_convergent_functions : Flag<["-"],
"fno-convergent-functions">,
// Common offloading options
let Group = offload_Group in {
-def offload_arch_EQ : Joined<["--"], "offload-arch=">, Flags<[NoXarchOption]>,
yxsamliu wrote:
For HI
@@ -5404,6 +5404,115 @@ third argument, can only occur at file scope.
a = b[i] * c[i] + e;
}
+Extensions for controlling atomic code generation
+=
+
+The ``[[clang::atomic]]`` statement attribute enables users to control ho
https://github.com/yxsamliu approved this pull request.
https://github.com/llvm/llvm-project/pull/124754
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@@ -4972,3 +4972,59 @@ def NoTrivialAutoVarInit: InheritableAttr {
let Documentation = [NoTrivialAutoVarInitDocs];
let SimpleHandler = 1;
}
+
+def Atomic : StmtAttr {
+ let Spellings = [Clang<"atomic">];
+ let Args = [
+EnumArgument<"NoRemoteMemory", "NoRemoteMemoryTy
yxsamliu wrote:
> The changes should definitely come with a release note in
> `clang/docs/ReleaseNotes.rst`, but this also seems like it maybe should get
> wider documentation in the language extensions manual. I mentioned a need for
> attribute documentation, that could be simple docs which p
@@ -764,6 +764,73 @@ void Parser::ParseGNUAttributeArgs(
ScopeLoc, Form);
}
+void Parser::ParseAtomicAttribute(
yxsamliu wrote:
I've simplified ParseAtomicAttribute by introducing a lambda that handles
parsing a single option (inc
@@ -5958,6 +5968,58 @@ void Clang::ConstructJob(Compilation &C, const JobAction
&JA,
RenderFloatingPointOptions(TC, D, OFastEnabled, Args, CmdArgs, JA);
+ if (Arg *AtomicArg = Args.getLastArg(options::OPT_fatomic_EQ)) {
yxsamliu wrote:
Refactored the cod
@@ -1797,55 +1798,62 @@ void Preprocessor::ExpandBuiltinMacro(Token &Tok) {
diag::err_feature_check_malformed);
return II && HasExtension(*this, II->getName());
});
- } else if (II == Ident__has_builtin) {
--
@@ -357,6 +357,7 @@ void Preprocessor::RegisterBuiltinMacros() {
Ident__has_builtin = RegisterBuiltinMacro("__has_builtin");
Ident__has_constexpr_builtin =
RegisterBuiltinMacro("__has_constexpr_builtin");
+ Ident__has_target_builtin = RegisterBuiltinMacro("__has_targ
yxsamliu wrote:
need release note
https://github.com/llvm/llvm-project/pull/126324
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@@ -357,6 +357,7 @@ void Preprocessor::RegisterBuiltinMacros() {
Ident__has_builtin = RegisterBuiltinMacro("__has_builtin");
Ident__has_constexpr_builtin =
RegisterBuiltinMacro("__has_constexpr_builtin");
+ Ident__has_target_builtin = RegisterBuiltinMacro("__has_targ
@@ -0,0 +1,13 @@
+// RUN: %clang -### -nogpuinc -nogpulib --offload-arch=gfx1030
--offload-arch=gfx1100 --offload-arch=gfx1101 -MD -MF tmp.d %s 2>&1 | FileCheck
%s
yxsamliu wrote:
adding `-target x86_64-pc-linux-gnu` probably fix the buildbot failure
https://g
yxsamliu wrote:
> I'm out of my depth here and will leave it up to @yxsamliu.
It seems reasonable to me, but I would like @rjmccall to take a look.
https://github.com/llvm/llvm-project/pull/124989
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https://github.com/yxsamliu edited
https://github.com/llvm/llvm-project/pull/114841
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https://github.com/yxsamliu edited
https://github.com/llvm/llvm-project/pull/114841
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yxsamliu wrote:
This may break ROCm santizer builds since whether santizer is on should be
determined by -fsanitize only, i.e. by default -fgpu-sanitize should be on.
https://github.com/llvm/llvm-project/pull/126090
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@@ -5404,6 +5404,151 @@ third argument, can only occur at file scope.
a = b[i] * c[i] + e;
}
+Extensions for controlling atomic code generation
+=
+
+The ``[[clang::atomic]]`` statement attribute enables users to control ho
https://github.com/yxsamliu approved this pull request.
https://github.com/llvm/llvm-project/pull/125646
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@@ -5404,6 +5404,151 @@ third argument, can only occur at file scope.
a = b[i] * c[i] + e;
}
+Extensions for controlling atomic code generation
+=
+
+The ``[[clang::atomic]]`` statement attribute enables users to control ho
https://github.com/yxsamliu approved this pull request.
https://github.com/llvm/llvm-project/pull/126186
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@@ -5618,10 +5618,18 @@ def nogpuinc : Flag<["-"], "nogpuinc">,
Group,
def nohipwrapperinc : Flag<["-"], "nohipwrapperinc">, Group,
HelpText<"Do not include the default HIP wrapper headers and include paths">;
def : Flag<["-"], "nocudainc">, Alias;
-def nogpulib : Flag<["-"]
@@ -7088,7 +7088,7 @@ void Clang::ConstructJob(Compilation &C, const JobAction
&JA,
}
// Forward -nogpulib to -cc1.
- if (Args.hasArg(options::OPT_nogpulib))
+ if (!Args.hasFlag(options::OPT_offloadlib, options::OPT_no_offloadlib, true))
CmdArgs.push_back("-nogpuli
@@ -96,6 +101,37 @@ the header file to conditionally make a
function constexpr whenever
the constant evaluation of the corresponding builtin (for example,
``std::fmax`` calls ``__builtin_fmax``) is supported in Clang.
+``__has_target_builtin``
+
+
@@ -0,0 +1,19 @@
+//===--- AtomicOptions.def - Atomic Options database -*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
yxsamliu wrote:
ping
https://github.com/llvm/llvm-project/pull/111885
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