[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/76357 >From a54f47f8055e898b6452183663863f6df01e98e1 Mon Sep 17 00:00:00 2001 From: wangpc Date: Mon, 25 Dec 2023 18:52:36 +0800 Subject: [PATCH 1/2] [RFC][RISCV] Support RISC-V Profiles in -march option This PR imp

[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)

@@ -0,0 +1,189 @@ +//===-- RISCVProfiles.td - RISC-V Profiles -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)

@@ -138,6 +150,8 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo { /// initializeProperties(). RISCVProcFamilyEnum getProcFamily() const { return RISCVProcFamily; } + RISCVProfileEnum getRISCVProfile() const { return RISCVProfile; } wangpc-pp wrote

[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)

@@ -0,0 +1,189 @@ +//===-- RISCVProfiles.td - RISC-V Profiles -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)

@@ -0,0 +1,189 @@ +//===-- RISCVProfiles.td - RISC-V Profiles -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/76357 >From 8dc42f5c90ba369a145868f8c1a9a8cb3e988cb0 Mon Sep 17 00:00:00 2001 From: wangpc Date: Mon, 25 Dec 2023 18:52:36 +0800 Subject: [PATCH] [RISCV] Support RISC-V Profiles in -march option This PR implements t

[clang] [llvm] [RISCV] Add generic CPUs for profiles (PR #84877)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/84877 As discussed in https://github.com/llvm/llvm-project/pull/76357#discussion_r1518452608, we may need to add generic CPUs for profiles. I don't know if we need S-mode profile CPUs. >From ec68548a470d6d9032a900

[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)

@@ -7105,10 +7105,15 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, Args.addOptInFlag(CmdArgs, options::OPT_frelaxed_template_template_args, options::OPT_fno_relaxed_template_template_args); - // -fsized-deallocation is off by default,

[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)

@@ -2912,16 +2912,70 @@ static bool sdkSupportsBuiltinModules(const Darwin::DarwinPlatformKind &TargetPl } } -void Darwin::addClangTargetOptions(const llvm::opt::ArgList &DriverArgs, - llvm::opt::ArgStringList &CC1Args, -

[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/83774 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)

wangpc-pp wrote: > The `__cpp_sized_deallocation` feature test macro should be set to 201309L This has been done. https://github.com/llvm/llvm-project/blob/1d900e298449d43547312364751f730b7a0d07d1/clang/lib/Frontend/InitPreprocessor.cpp#L690C1-L692C1 https://github.com/llvm/llvm-project/pull/83

[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/83774 >From 26245679b0f40b510e628aaed091739e9931c29c Mon Sep 17 00:00:00 2001 From: wangpc Date: Fri, 14 Jul 2023 10:38:14 +0800 Subject: [PATCH 1/4] [clang] Enable sized deallocation by default in C++14 onwards Si

[clang] [clang] Define SwiftInfo for RISCVTargetCodeGenInfo (PR #82152)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/82152 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Remove experimental from Zacas. (PR #83195)

https://github.com/wangpc-pp approved this pull request. LGTM. Will it be in LLVM 18? Or we need more time to examine its robustness? https://github.com/llvm/llvm-project/pull/83195 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.

[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)

wangpc-pp wrote: Ping. https://github.com/llvm/llvm-project/pull/76357 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)

@@ -839,6 +860,33 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension, "string must be lowercase"); } + bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") || + Arch.starts_with("r

[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/83774 Since C++14 has been released for about nine years and most standard libraries have implemented sized deallocation functions, it's time to make this feature default again. This is another try of https://reviews

[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/83774 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/83774 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add support of Sscofpmf (PR #83831)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/83831 This is used in profile, but somehow we missed it. >From 7e0815dda185c635448bf08c150fc54d9f9d4b5f Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Mon, 4 Mar 2024 19:51:15 +0800 Subject: [PATCH] [RISCV] Add

[clang] [llvm] [RISCV] Add support of Sscofpmf (PR #83831)

https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/83831 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/76357 >From bd9b759d853d8196ae893a90442a3c3e7e5fa74d Mon Sep 17 00:00:00 2001 From: wangpc Date: Mon, 25 Dec 2023 18:52:36 +0800 Subject: [PATCH] [RFC][RISCV] Support RISC-V Profiles in -march option This PR impleme

[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/76357 >From a54f47f8055e898b6452183663863f6df01e98e1 Mon Sep 17 00:00:00 2001 From: wangpc Date: Mon, 25 Dec 2023 18:52:36 +0800 Subject: [PATCH] [RFC][RISCV] Support RISC-V Profiles in -march option This PR impleme

[clang] [RISCV][Clang] Added builtin support for experimental Zimop extension (PR #79971)

@@ -5588,6 +5588,14 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, // Check if rnum is in [0, 10] case RISCV::BI__builtin_riscv_aes64ks1i: return SemaBuiltinConstantArgRange(TheCall, 1, 0, 10); + // Check if n of mop.r.[n] is in [0, 31] + case RISC

[clang] [RISCV][Clang] Added builtin support for experimental Zimop extension (PR #79971)

@@ -89,5 +89,13 @@ TARGET_BUILTIN(__builtin_riscv_sm3p1, "UiUi", "nc", "zksh") TARGET_BUILTIN(__builtin_riscv_ntl_load, "v.", "t", "zihintntl") TARGET_BUILTIN(__builtin_riscv_ntl_store, "v.", "t", "zihintntl") +// Zimop extension wangpc-pp wrote: You may need

[clang] [llvm] [RISCV][MC] MC layer support for the experimental zalasr extension (PR #79911)

wangpc-pp wrote: What's the status of Zalasr extension? Is it an official extension now? https://github.com/llvm/llvm-project/pull/79911 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][RISCV] Add assumptions to vsetvli/vsetvlimax (PR #79975)

wangpc-pp wrote: After some random thinking, I think these assumptions may need to be added to vsetvli/vsetvlimax LLVM intrinsics instead of adding them in Clang CodeGen. In this way, we can make other frontends like `flang/Rust/TVM/MLIR/...` benefit from these assumptions. Is it possible? I d

[clang] [Clang][RISCV] Add assumptions to vsetvli/vsetvlimax (PR #79975)

wangpc-pp wrote: > I'm concerned that llvm.assume is handled differently than a branch to > unreachable in the middle end. Actually the CodeGen part is written by referring to the LLVM IR generated by unreachable way (https://godbolt.org/z/vf1v7f744). > Have you tested that these assumes hav

[clang] [Clang][RISCV] Add assumptions to vsetvli/vsetvlimax (PR #79975)

wangpc-pp wrote: > Also I guess most of RVV intrinsic could add `const` too, that could help > some generic optimization work better like CSE. This PR doesn't add the `const` attribute, I don't know if adding `const` may help to optimize. https://github.com/llvm/llvm-project/pull/79975 __

[clang] [Clang][TableGen] Add Features to TargetBuiltin (PR #80279)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/80279 RISCV target will use this parameter, so we need a way to specify it. >From b0728e172ab9d6c139fc665b739d51af20a27bd2 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Thu, 1 Feb 2024 19:47:46 +0800 Subject:

[clang] [clang-tools-extra] [llvm] [RISCV][NFC] Simplify calls.ll and autogenerate checks for tail-calls.ll (PR #79248)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/79248 >From 63ca83d205a361464ec59e9c134fafa795b17cef Mon Sep 17 00:00:00 2001 From: wangpc Date: Wed, 24 Jan 2024 11:22:03 +0800 Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?= =?UTF-8?q

[clang] [llvm] [clang-tools-extra] [RISCV][NFC] Simplify calls.ll and autogenerate checks for tail-calls.ll (PR #79248)

https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/79248 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [RISCV] Add Ssqosid support to -march. (PR #80747)

@@ -1612,6 +1613,14 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-SUPM-EXT %s // CHECK-SUPM-EXT: __riscv_supm 8000{{$}} +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_ssqosid1p0 -E -dM %s \ +// RUN: -o - | FileCheck --check-p

[llvm] [clang] [RISCV][MC] Add experimental support of Zaamo and Zalrsc (PR #78970)

@@ -1307,6 +1309,13 @@ // CHECK-ZVKT-EXT: __riscv_zvkt 100{{$}} // Experimental extensions +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_zaamo0p1 -x c -E -dM %s \ wangpc-pp wrote: Sorry for that I forgot to upda

[clang-tools-extra] [clang] [llvm] [flang] [compiler-rt] [RISCV][MC] Add experimental support of Zaamo and Zalrsc (PR #78970)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/78970 >From 8cc71cb7ddb2e6691d31138ae2ef683a0690e171 Mon Sep 17 00:00:00 2001 From: wangpc Date: Mon, 22 Jan 2024 21:11:42 +0800 Subject: [PATCH 1/5] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?= =?UTF-8?q

[llvm] [clang] [RISCV] Add -march support for many of the S extensions mentioned in the profile specification. (PR #79399)

https://github.com/wangpc-pp commented: [Ssstrict](https://github.com/riscv/riscv-profiles/commit/962bcc6764f3b6ccfbdcfe030c77b05c6a475c5e) too? I was going to add it but why not just hitchhike this PR? :-) https://github.com/llvm/llvm-project/pull/79399

[clang-tools-extra] [flang] [clang] [compiler-rt] [llvm] [RISCV][MC] Add experimental support of Zaamo and Zalrsc (PR #78970)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/78970 >From 8cc71cb7ddb2e6691d31138ae2ef683a0690e171 Mon Sep 17 00:00:00 2001 From: wangpc Date: Mon, 22 Jan 2024 21:11:42 +0800 Subject: [PATCH 1/6] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?= =?UTF-8?q

[clang-tools-extra] [flang] [clang] [compiler-rt] [llvm] [RISCV][MC] Add experimental support of Zaamo and Zalrsc (PR #78970)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/78970 >From 8cc71cb7ddb2e6691d31138ae2ef683a0690e171 Mon Sep 17 00:00:00 2001 From: wangpc Date: Mon, 22 Jan 2024 21:11:42 +0800 Subject: [PATCH 1/7] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?= =?UTF-8?q

[clang] [RISCV] Support __riscv_v_fixed_vlen for vbool types. (PR #76551)

https://github.com/wangpc-pp approved this pull request. Oh sorry, I was going to approve this before llvm 18 branch but I forgot. Should we backport this to llvm 18? https://github.com/llvm/llvm-project/pull/76551 ___ cfe-commits mailing list cfe-comm

[clang] [RISCV] Reformat riscv-target-features.c. NFC (PR #79409)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/79409 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang-tools-extra] [flang] [compiler-rt] [lldb] [libc] [clang] [libcxx] [libunwind] [llvm] [lld] [RISCV][MC] Add experimental support of Zaamo and Zalrsc (PR #78970)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/78970 >From 8cc71cb7ddb2e6691d31138ae2ef683a0690e171 Mon Sep 17 00:00:00 2001 From: wangpc Date: Mon, 22 Jan 2024 21:11:42 +0800 Subject: [PATCH 1/7] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?= =?UTF-8?q

[flang] [lld] [libc] [clang-tools-extra] [clang] [libcxx] [libunwind] [llvm] [lldb] [compiler-rt] [RISCV][MC] Add experimental support of Zaamo and Zalrsc (PR #78970)

https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/78970 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Graduate Zicond to non-experimental (PR #79811)

wangpc-pp wrote: Should we backport this to llvm 18? https://github.com/llvm/llvm-project/pull/79811 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [RISCV] Graduate Zicond to non-experimental (PR #79811)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/79811 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Support __riscv_v_fixed_vlen for vbool types. (PR #76551)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/76551 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Support __riscv_v_fixed_vlen for vbool types. (PR #76551)

@@ -2415,7 +2415,10 @@ only be a power of 2 between 64 and 65536. For types where LMUL!=1, ``__riscv_v_fixed_vlen`` needs to be scaled by the LMUL of the type before passing to the attribute. -``vbool*_t`` types are not supported at this time. +For ``vbool*_t`` types, ``__ris

[clang] [RISCV] Support __riscv_v_fixed_vlen for vbool types. (PR #76551)

https://github.com/wangpc-pp commented: Please add a release note. https://github.com/llvm/llvm-project/pull/76551 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

wangpc-pp wrote: It's not easy to push this forward and thanks a lot! I'll merge this soon. If there are some issues (hope not 😄), follow-up patches will fix them. https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commit

[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [RISCV] Add B extension (PR #76893)

wangpc-pp wrote: I will hold this PR util B extension is ratified (I think it won't take too long). Or, at least after llvm 18 branch is created. https://github.com/llvm/llvm-project/pull/76893 ___ cfe-commits mailing list cfe-commits@lists.llvm.org h

[clang] [RISCV] Re-order riscv-target-features.c to put non-experimental extensions together. (PR #78675)

https://github.com/wangpc-pp approved this pull request. LGTM! https://github.com/llvm/llvm-project/pull/78675 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add B extension (PR #76893)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/76893 >From c4f7441b2809dfbb6ed4b6d97d581e3d736819fe Mon Sep 17 00:00:00 2001 From: wangpc Date: Thu, 4 Jan 2024 13:05:53 +0800 Subject: [PATCH] [RISCV] Add B extension It seems that we have `B` extension again: htt

[clang] [llvm] [RISCV] Add experimental support of Zaamo and Zalrsc (PR #78970)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/78970 `A` extension has been split into two parts: Zaamo (Atomic Memory Operations) and Zalrsc (Load-Reserved/Store-Conditional). See also https://github.com/riscv/riscv-zaamo-zalrsc. This patch adds the MC support.

[clang] [llvm] [RISCV] Add experimental support of Zaamo and Zalrsc (PR #77424)

wangpc-pp wrote: > Can we split the CodeGen part out of this patch? MC part is https://github.com/llvm/llvm-project/pull/78970. This PR will be the CodeGen part and I will update this PR later. https://github.com/llvm/llvm-project/pull/77424 ___ cfe-c

[clang] [llvm] [RISCV] Add experimental support of Zaamo and Zalrsc (PR #78970)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/78970 >From 8cc71cb7ddb2e6691d31138ae2ef683a0690e171 Mon Sep 17 00:00:00 2001 From: wangpc Date: Mon, 22 Jan 2024 21:11:42 +0800 Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?= =?UTF-8?q

[clang] [llvm] [RISCV][MC] Add experimental support of Zaamo and Zalrsc (PR #78970)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/78970 >From 8cc71cb7ddb2e6691d31138ae2ef683a0690e171 Mon Sep 17 00:00:00 2001 From: wangpc Date: Mon, 22 Jan 2024 21:11:42 +0800 Subject: [PATCH 1/3] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?= =?UTF-8?q

[llvm] [clang] [RISCV][MC] Add experimental support of Zaamo and Zalrsc (PR #78970)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/78970 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add sifive-p670 processor (PR #79015)

@@ -241,7 +241,17 @@ // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbb" // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbs" // MCPU-SIFIVE-P450-SAME: "-target-abi" "lp64d" -// + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p670 | FileCheck -check-prefix=MCPU-SIF

[llvm] [clang] [RISCV] Add sifive-p670 processor (PR #79015)

@@ -1082,6 +1082,13 @@ def TuneShortForwardBranchOpt def HasShortForwardBranchOpt : Predicate<"Subtarget->hasShortForwardBranchOpt()">; def NoShortForwardBranchOpt : Predicate<"!Subtarget->hasShortForwardBranchOpt()">; +// P670 requires a S2V transfer buffer to move scalars

[llvm] [clang] [RISCV][MC] Add experimental support of Zaamo and Zalrsc (PR #78970)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/78970 >From 8cc71cb7ddb2e6691d31138ae2ef683a0690e171 Mon Sep 17 00:00:00 2001 From: wangpc Date: Mon, 22 Jan 2024 21:11:42 +0800 Subject: [PATCH 1/4] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?= =?UTF-8?q

[llvm] [clang] [RISCV][MC] Add experimental support of Zaamo and Zalrsc (PR #78970)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/78970 >From 8cc71cb7ddb2e6691d31138ae2ef683a0690e171 Mon Sep 17 00:00:00 2001 From: wangpc Date: Mon, 22 Jan 2024 21:11:42 +0800 Subject: [PATCH 1/5] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?= =?UTF-8?q

[clang] [Clang][RISCV] Support CSRs in clobbered registers of inline assembly (PR #67646)

wangpc-pp wrote: Ping. Any suggestions? https://github.com/llvm/llvm-project/pull/67646 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][RISCV] Support CSRs in clobbered registers of inline assembly (PR #67646)

https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/67646 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Run mem2reg to simplify Zbc tests (PR #70169)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/70169 None >From c5500404b5885e7038b0360d7d8bfbb317d6a1b5 Mon Sep 17 00:00:00 2001 From: wangpc Date: Wed, 25 Oct 2023 14:36:09 +0800 Subject: [PATCH] [RISCV] Run mem2reg to simplify Zbc tests --- clang/test/CodeG

[clang] [RISCV] Run mem2reg to simplify Zbc tests (PR #70169)

https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/70169 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Add processor definition for XiangShan-NanHu (PR #70294)

wangpc-pp wrote: LGTM in general, except one question: will zicbom and zicboz be in the final RTL? https://github.com/llvm/llvm-project/pull/70294 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/

[clang] [RISCV] Add processor definition for XiangShan-NanHu (PR #70294)

https://github.com/wangpc-pp approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/70294 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Add processor definition for XiangShan-NanHu (PR #70294)

@@ -20,6 +20,17 @@ // MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+zicsr" "-target-feature" "+zifencei" // MCPU-SYNTACORE-SCR1-MAX: "-target-abi" "ilp32" +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=xiangshan-nanhu | FileCheck -check-prefix=MCPU-XIANGSHAN-NANHU %s

[clang] [RISCV] Add processor definition for XiangShan-NanHu (PR #70294)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/70294 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Add processor definition for XiangShan-NanHu (PR #70294)

wangpc-pp wrote: > > LGTM in general, except one question: will zicbom and zicboz be in the > > final RTL? > > You can find the full implementation of `zicbom` and `zicboz` here: > [OpenXiangShan/XiangShan@ca18a0b](https://github.com/OpenXiangShan/XiangShan/commit/ca18a0b47b0e4089fd0dd1c085091

[clang] [Clang][RISCV] Add vcreate intrinsics for RVV non-tuple types (PR #70355)

@@ -345,6 +345,54 @@ class VString { !eq(nf, 8): !if(signed, "", "UvUvUvUvUvUvUvUv")); } + +class FixedVString { + string V = "(LFixedLog2LMUL:" # fixed_lmul # ")" # !if(signed, "v", "Uv"); + string S = !cond(!eq(num, 1): V, + !eq

[clang] [Clang][RISCV] Add vcreate intrinsics for RVV non-tuple types (PR #70355)

@@ -345,6 +345,54 @@ class VString { !eq(nf, 8): !if(signed, "", "UvUvUvUvUvUvUvUv")); } + +class FixedVString { + string V = "(LFixedLog2LMUL:" # fixed_lmul # ")" # !if(signed, "v", "Uv"); + string S = !cond(!eq(num, 1): V, + !eq

[clang] [RISCV] Add processor definition for XiangShan-NanHu (PR #70294)

wangpc-pp wrote: Xiangshan is of great famousness in China and there is already a community in which many individual developers and organiztions/companies like PLCT, T-Head have participated. So I think we needn't worry about the maintenance. :-) https://github.com/llvm/llvm-project/pull/70294

[clang] [Clang][RISCV] Support CSRs in clobbered registers of inline assembly (PR #67646)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/67646 To match GCC's behaviors. Fixes #67596 >From d37c233588aaa1ba0df29ffc9bc402a98254f2d2 Mon Sep 17 00:00:00 2001 From: wangpc Date: Thu, 28 Sep 2023 16:50:31 +0800 Subject: [PATCH] [Clang][RISCV] Support CSRs

[clang] [Clang][RISCV] Support CSRs in clobbered registers of inline assembly (PR #67646)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/67646 >From a82026fb50d3dafd4955aba8d193de62d881960f Mon Sep 17 00:00:00 2001 From: wangpc Date: Thu, 28 Sep 2023 16:50:31 +0800 Subject: [PATCH] [Clang][RISCV] Support CSRs in clobbered registers of inline assembly

[clang] [clang] Define SwiftInfo for RISCVTargetCodeGenInfo (PR #82152)

wangpc-pp wrote: Can this be tested? I don't know what the affects are. https://github.com/llvm/llvm-project/pull/82152 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][RISCV] Add assumptions to vsetvli/vsetvlimax (PR #79975)

wangpc-pp wrote: > Can we implement this in `computeKnownBitsFromOperator/getRangeForIntrinsic`? > > https://github.com/llvm/llvm-project/blob/b21e3282864c9f7ad656c64bc375f5869ef76d19/llvm/lib/Analysis/ValueTracking.cpp#L1578-L1584 Thanks! We can implement this partly (will create another PR to

[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/76357 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)

https://github.com/wangpc-pp ready_for_review https://github.com/llvm/llvm-project/pull/76357 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/76357 >From c7f2589692c4d310d4e61ebcbbceb3602b0ef227 Mon Sep 17 00:00:00 2001 From: wangpc Date: Mon, 25 Dec 2023 18:52:36 +0800 Subject: [PATCH] [RFC][RISCV] Support RISC-V Profiles in -march option This PR impleme

[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/76357 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)

@@ -138,6 +150,8 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo { /// initializeProperties(). RISCVProcFamilyEnum getProcFamily() const { return RISCVProcFamily; } + RISCVProfileEnum getRISCVProfile() const { return RISCVProfile; } wangpc-pp wrote

[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/76357 >From c7f2589692c4d310d4e61ebcbbceb3602b0ef227 Mon Sep 17 00:00:00 2001 From: wangpc Date: Mon, 25 Dec 2023 18:52:36 +0800 Subject: [PATCH 1/2] [RFC][RISCV] Support RISC-V Profiles in -march option This PR imp

[clang] eaa063f - [RISCV] Remove duplicated --target

Author: Wang Pengcheng Date: 2024-04-08T14:59:17+08:00 New Revision: eaa063f0c6d51a3b561bc2007fe95420949f42d1 URL: https://github.com/llvm/llvm-project/commit/eaa063f0c6d51a3b561bc2007fe95420949f42d1 DIFF: https://github.com/llvm/llvm-project/commit/eaa063f0c6d51a3b561bc2007fe95420949f42d1.diff

[clang] b36fcf4 - [RISCV] Rename variable CPUModel to Model

Author: Wang Pengcheng Date: 2024-11-22T20:12:28+08:00 New Revision: b36fcf4f493ad9d30455e178076d91be99f3a7d8 URL: https://github.com/llvm/llvm-project/commit/b36fcf4f493ad9d30455e178076d91be99f3a7d8 DIFF: https://github.com/llvm/llvm-project/commit/b36fcf4f493ad9d30455e178076d91be99f3a7d8.diff

[clang] 875b10f - [RISCV] Support __builtin_cpu_is

Author: Pengcheng Wang Date: 2024-11-22T22:58:54+08:00 New Revision: 875b10f7d0888ca7e53f527f4c30531bd6b50bfb URL: https://github.com/llvm/llvm-project/commit/875b10f7d0888ca7e53f527f4c30531bd6b50bfb DIFF: https://github.com/llvm/llvm-project/commit/875b10f7d0888ca7e53f527f4c30531bd6b50bfb.diff

[clang] e57f4e8 - [RISCV][NFC] Make generated intrinsic records more human-readable (#133710)

Author: Pengcheng Wang Date: 2025-04-14T13:00:57+08:00 New Revision: e57f4e8969db32f075d8f3e554506ec8b187a2f1 URL: https://github.com/llvm/llvm-project/commit/e57f4e8969db32f075d8f3e554506ec8b187a2f1 DIFF: https://github.com/llvm/llvm-project/commit/e57f4e8969db32f075d8f3e554506ec8b187a2f1.diff

[clang] 21ff45d - Revert "[RISCV][NFC] Make generated intrinsic records more human-readable (#133710)"

Author: Wang Pengcheng Date: 2025-04-14T12:56:33+08:00 New Revision: 21ff45dea1601d6d12438b5201ff09b8726899be URL: https://github.com/llvm/llvm-project/commit/21ff45dea1601d6d12438b5201ff09b8726899be DIFF: https://github.com/llvm/llvm-project/commit/21ff45dea1601d6d12438b5201ff09b8726899be.diff

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