https://github.com/vikramRH approved this pull request.
https://github.com/llvm/llvm-project/pull/71656
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
vikramRH wrote:
@b-sumner, @ssahasra , what are your thoughts about making the hostcall default
throughout ?
Also I do not think splitting this into separate patches is feasible since
changes are interdependent, however I could split changes into separate commits
to make it easier to review.
https://github.com/vikramRH closed
https://github.com/llvm/llvm-project/pull/70932
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
https://github.com/vikramRH created
https://github.com/llvm/llvm-project/pull/72554
This is a prerequisite to enable opencl hostcall printf. ensures that AMDGPU
printf calls are lowered at clang CodeGen for both HIP and OCL.
>From 6ace9d0a51064be189093ca3bb42416aafadb7f6 Mon Sep 17 00:00:00 2
https://github.com/vikramRH created
https://github.com/llvm/llvm-project/pull/72556
Kindly review top commit here, The builtin specific changes are up for in a
seperate patch (https://github.com/llvm/llvm-project/pull/72554)
Few implementation details,
1. Hostcall printf is now default for bot
vikramRH wrote:
Two different patch sets have been created here,
https://github.com/llvm/llvm-project/pull/72554
https://github.com/llvm/llvm-project/pull/72556
https://github.com/llvm/llvm-project/pull/70932
___
cfe-commits mailing list
cfe-commits
@@ -2458,6 +2458,11 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl
GD, unsigned BuiltinID,
&getTarget().getLongDoubleFormat() == &llvm::APFloat::IEEEquad())
BuiltinID = mutateLongDoubleBuiltin(BuiltinID);
+ // Mutate the printf builtin ID so that we u
@@ -406,5 +410,9 @@ TARGET_BUILTIN(__builtin_amdgcn_cvt_pk_fp8_f32, "iffiIb",
"nc", "fp8-insts")
TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_bf8_f32, "ifiiIi", "nc", "fp8-insts")
TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_fp8_f32, "ifiiIi", "nc", "fp8-insts")
+// OpenCL
+LANGBUILTIN(p
vikramRH wrote:
> Any tests? Can you explain why it's not sufficient to do this lowering in the
> AMDGPU pass?
I intended these changes to be part of
https://github.com/llvm/llvm-project/pull/72556, but it seemed too many changes
at one place, so I extracted this part out for ease of review.
https://github.com/vikramRH updated
https://github.com/llvm/llvm-project/pull/72554
>From 9833353ab6d7bb9716883b89f4e8b90285c1a60c Mon Sep 17 00:00:00 2001
From: Vikram
Date: Fri, 10 Nov 2023 09:39:41 +
Subject: [PATCH] [AMDGPU] Treat printf as builtin for OpenCL
---
clang/include/clang/B
https://github.com/vikramRH edited
https://github.com/llvm/llvm-project/pull/72556
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
https://github.com/vikramRH edited
https://github.com/llvm/llvm-project/pull/72554
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
https://github.com/vikramRH updated
https://github.com/llvm/llvm-project/pull/72556
>From 6ace9d0a51064be189093ca3bb42416aafadb7f6 Mon Sep 17 00:00:00 2001
From: Vikram
Date: Fri, 10 Nov 2023 09:39:41 +
Subject: [PATCH 1/3] [AMDGPU] Treat printf as builtin for OpenCL
---
clang/include/cla
@@ -170,20 +173,46 @@ static Value *appendString(IRBuilder<> &Builder, Value
*Desc, Value *Arg,
return callAppendStringN(Builder, Desc, Arg, Length, IsLast);
}
+static Value *appendVectorArg(IRBuilder<> &Builder, Value *Desc, Value *Arg,
+ bool
@@ -170,20 +173,46 @@ static Value *appendString(IRBuilder<> &Builder, Value
*Desc, Value *Arg,
return callAppendStringN(Builder, Desc, Arg, Length, IsLast);
}
+static Value *appendVectorArg(IRBuilder<> &Builder, Value *Desc, Value *Arg,
+ bool
@@ -170,20 +173,46 @@ static Value *appendString(IRBuilder<> &Builder, Value
*Desc, Value *Arg,
return callAppendStringN(Builder, Desc, Arg, Length, IsLast);
}
+static Value *appendVectorArg(IRBuilder<> &Builder, Value *Desc, Value *Arg,
vikramRH wrote:
Do
@@ -278,7 +310,13 @@ static Value *callBufferedPrintfStart(
StringData(StringRef(), LenWithNull, LenWithNullAligned, false));
}
} else {
- int AllocSize = M->getDataLayout().getTypeAllocSize(Args[i]->getType());
+ int AllocSize = 0;
+ if (OC
@@ -278,7 +310,13 @@ static Value *callBufferedPrintfStart(
StringData(StringRef(), LenWithNull, LenWithNullAligned, false));
}
} else {
- int AllocSize = M->getDataLayout().getTypeAllocSize(Args[i]->getType());
+ int AllocSize = 0;
+ if (OC
https://github.com/vikramRH created
https://github.com/llvm/llvm-project/pull/70932
Attempt to enable OpenCL hostcall printf (SWDEV-204804). I would like to have
some inputs regarding few key points listed here,
1. We continue to use "-mprintf-kind" option to decide the lowering scheme. It
n
vikramRH wrote:
@arsenm, The choice of defaults is based on current state of printf. HIP uses
hostcalls and OpenCL uses buffered variant by default. However I'm willing to
make one of the two variants consistent (preferably hostcalls for me). Do note
that this would make all OpenCL printf to
https://github.com/vikramRH updated
https://github.com/llvm/llvm-project/pull/70932
>From 4c0467078b2f38e814569ad351f86129d1c1d5ee Mon Sep 17 00:00:00 2001
From: Vikram
Date: Wed, 4 Oct 2023 05:41:47 -0400
Subject: [PATCH] [WIP][AMDGPU] hostcall printf support for OpenCL
---
clang/include/cla
https://github.com/vikramRH updated
https://github.com/llvm/llvm-project/pull/72556
>From 6ace9d0a51064be189093ca3bb42416aafadb7f6 Mon Sep 17 00:00:00 2001
From: Vikram
Date: Fri, 10 Nov 2023 09:39:41 +
Subject: [PATCH 1/4] [AMDGPU] Treat printf as builtin for OpenCL
---
clang/include/cla
@@ -170,20 +173,49 @@ static Value *appendString(IRBuilder<> &Builder, Value
*Desc, Value *Arg,
return callAppendStringN(Builder, Desc, Arg, Length, IsLast);
}
+static Value *appendVectorArg(IRBuilder<> &Builder, Value *Desc, Value *Arg,
+ bool
@@ -1,12 +1,68 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// RUN: %clang_cc1 -cl-std=CL1.2 -triple amdgcn-amd-amdhsa
-disable-llvm-passes -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -cl-std=CL1.2 -triple amdgcn-amd-amdhsa
-mprint
@@ -194,6 +226,8 @@ static void locateCStrings(SparseBitVector<8> &BV,
StringRef Str) {
SpecPos += 2;
continue;
}
+if (Str.find_first_of("v", SpecPos) != StringRef::npos)
vikramRH wrote:
Fixed
https://github.com/llvm/llvm-project/pull/725
@@ -170,20 +173,49 @@ static Value *appendString(IRBuilder<> &Builder, Value
*Desc, Value *Arg,
return callAppendStringN(Builder, Desc, Arg, Length, IsLast);
}
+static Value *appendVectorArg(IRBuilder<> &Builder, Value *Desc, Value *Arg,
+ bool
@@ -26,28 +26,31 @@ using namespace llvm;
#define DEBUG_TYPE "amdgpu-emit-printf"
-static Value *fitArgInto64Bits(IRBuilder<> &Builder, Value *Arg) {
+static Value *fitArgInto64Bits(IRBuilder<> &Builder, Value *Arg,
+ bool IsBuffered) {
+ const
@@ -26,28 +26,31 @@ using namespace llvm;
#define DEBUG_TYPE "amdgpu-emit-printf"
-static Value *fitArgInto64Bits(IRBuilder<> &Builder, Value *Arg) {
+static Value *fitArgInto64Bits(IRBuilder<> &Builder, Value *Arg,
+ bool IsBuffered) {
+ const
@@ -406,5 +410,9 @@ TARGET_BUILTIN(__builtin_amdgcn_cvt_pk_fp8_f32, "iffiIb",
"nc", "fp8-insts")
TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_bf8_f32, "ifiiIi", "nc", "fp8-insts")
TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_fp8_f32, "ifiiIi", "nc", "fp8-insts")
+// OpenCL
+LANGBUILTIN(p
https://github.com/vikramRH edited
https://github.com/llvm/llvm-project/pull/72554
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
https://github.com/vikramRH ready_for_review
https://github.com/llvm/llvm-project/pull/72556
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
https://github.com/vikramRH edited
https://github.com/llvm/llvm-project/pull/72556
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
vikramRH wrote:
ping
https://github.com/llvm/llvm-project/pull/72556
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
vikramRH wrote:
@arsenm , apologies for the trouble here. I should have based this out of my
earlier commit. currently I do not see a way to base this patch off of my
earlier commit and it might get too confusing for other reviewers if I close
this and raise another review. would the individua
@@ -406,5 +410,9 @@ TARGET_BUILTIN(__builtin_amdgcn_cvt_pk_fp8_f32, "iffiIb",
"nc", "fp8-insts")
TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_bf8_f32, "ifiiIi", "nc", "fp8-insts")
TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_fp8_f32, "ifiiIi", "nc", "fp8-insts")
+// OpenCL
+LANGBUILTIN(p
https://github.com/vikramRH edited
https://github.com/llvm/llvm-project/pull/72554
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
vikramRH wrote:
> Is there a separate PR open for "Add vector processing support to AMDGPU
> printf"? I think it's easiest to move this part forward first
@arsenm , you are right. I just want to make sure we are good on runtime
changes too now since there seems to be a blocker. The changes her
@@ -4742,6 +4742,16 @@ void Clang::ConstructJob(Compilation &C, const JobAction
&JA,
Args.ClaimAllArgs(options::OPT_gen_cdb_fragment_path);
}
+ if (TC.getTriple().isAMDGPU() && types::isOpenCL(Input.getType())) {
+if (Args.getLastArg(options::OPT_mprintf_kind_EQ))
https://github.com/vikramRH created
https://github.com/llvm/llvm-project/pull/76379
Feel free to add additional reviewers as relevant,
I'm yet to update float test cases as I'm not sure whether it would be safe to
directly compare float results in static assert. Would it okay to integer cast
https://github.com/vikramRH edited
https://github.com/llvm/llvm-project/pull/76379
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
vikramRH wrote:
It seems there are few crashes with systemZ vectors. Looking into them
https://github.com/llvm/llvm-project/pull/76379
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
https://github.com/vikramRH updated
https://github.com/llvm/llvm-project/pull/76379
>From 89c79eea31d1a9ec0656fbf5c4eacf75b2471034 Mon Sep 17 00:00:00 2001
From: Vikram
Date: Wed, 20 Dec 2023 05:36:40 +
Subject: [PATCH] [Clang] support vector subscript expressions in constant
evaluator
--
https://github.com/vikramRH closed
https://github.com/llvm/llvm-project/pull/76379
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
vikramRH wrote:
Putting this on hold hold as @yuanfang-chen already has a PR
https://github.com/llvm/llvm-project/pull/76379
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
@@ -202,12 +207,20 @@ RValue
CodeGenFunction::EmitAMDGPUDevicePrintfCallExpr(const CallExpr *E) {
Args.push_back(Arg);
}
- llvm::IRBuilder<> IRB(Builder.GetInsertBlock(), Builder.GetInsertPoint());
- IRB.SetCurrentDebugLocation(Builder.getCurrentDebugLocation());
+ a
@@ -3616,6 +3617,12 @@ unsigned FunctionDecl::getBuiltinID(bool
ConsiderWrapperFunctions) const {
if (!ConsiderWrapperFunctions && getStorageClass() == SC_Static)
return 0;
+ // AMDGCN implementation supports printf as a builtin
+ // for OpenCL
+ if (Context.getTarge
@@ -3616,6 +3617,12 @@ unsigned FunctionDecl::getBuiltinID(bool
ConsiderWrapperFunctions) const {
if (!ConsiderWrapperFunctions && getStorageClass() == SC_Static)
return 0;
+ // AMDGCN implementation supports printf as a builtin
+ // for OpenCL
+ if (Context.getTarge
@@ -3616,6 +3617,12 @@ unsigned FunctionDecl::getBuiltinID(bool
ConsiderWrapperFunctions) const {
if (!ConsiderWrapperFunctions && getStorageClass() == SC_Static)
return 0;
+ // AMDGCN implementation supports printf as a builtin
+ // for OpenCL
+ if (Context.getTarge
https://github.com/vikramRH edited
https://github.com/llvm/llvm-project/pull/72556
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
https://github.com/vikramRH edited
https://github.com/llvm/llvm-project/pull/72556
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
@@ -3616,6 +3617,12 @@ unsigned FunctionDecl::getBuiltinID(bool
ConsiderWrapperFunctions) const {
if (!ConsiderWrapperFunctions && getStorageClass() == SC_Static)
return 0;
+ // AMDGCN implementation supports printf as a builtin
+ // for OpenCL
+ if (Context.getTarge
https://github.com/vikramRH created
https://github.com/llvm/llvm-project/pull/86801
The motivation for this change comes from an ongoing PR (#72556 ) , which
enables hostcall based printf lowering for AMDGPU target and OpenCL inputs. The
OpenCL printf has a different signature than the C print
https://github.com/vikramRH closed
https://github.com/llvm/llvm-project/pull/72554
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
vikramRH wrote:
closing this in favour of https://github.com/llvm/llvm-project/pull/86801
https://github.com/llvm/llvm-project/pull/72554
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commit
https://github.com/vikramRH ready_for_review
https://github.com/llvm/llvm-project/pull/86801
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
vikramRH wrote:
Thanks for the comments @AaronBallman. The core issue here is that the current
builtin handling design does not allow multiple overloads for the same
identifier to coexist (ref.
https://github.com/llvm/llvm-project/blob/eacda36c7dd842cb15c0c954eda74b67d0c73814/clang/include/cl
vikramRH wrote:
> I looked at the OpenCL spec for C standard library support and was surprised
> that 1) it's only talking about C99 so it's unclear what happens for C11
> (clause 6 says "This document describes the modifications and restrictions to
> C99 and C11 in OpenCL C" but 6.11 only tal
@@ -3616,6 +3617,12 @@ unsigned FunctionDecl::getBuiltinID(bool
ConsiderWrapperFunctions) const {
if (!ConsiderWrapperFunctions && getStorageClass() == SC_Static)
return 0;
+ // AMDGCN implementation supports printf as a builtin
+ // for OpenCL
+ if (Context.getTarge
@@ -2550,6 +2550,11 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl
GD, unsigned BuiltinID,
&getTarget().getLongDoubleFormat() == &llvm::APFloat::IEEEquad())
BuiltinID = mutateLongDoubleBuiltin(BuiltinID);
+ // Mutate the printf builtin ID so that we us
@@ -202,12 +207,20 @@ RValue
CodeGenFunction::EmitAMDGPUDevicePrintfCallExpr(const CallExpr *E) {
Args.push_back(Arg);
}
- llvm::IRBuilder<> IRB(Builder.GetInsertBlock(), Builder.GetInsertPoint());
- IRB.SetCurrentDebugLocation(Builder.getCurrentDebugLocation());
+ a
vikramRH wrote:
The new set of changes adds following changes,
1. The iteration over vector elements now happens using vector size from the
format specifier as reference, this is inline with runtime implementation and
helps handling undefined behavior when we have a mismatch.
2. The error flag
@@ -178,17 +181,29 @@ RValue
CodeGenFunction::EmitNVPTXDevicePrintfCallExpr(const CallExpr *E) {
E, this, GetVprintfDeclaration(CGM.getModule()), false);
}
+// Deterimines if an argument is a string
+static bool isString(const clang::Type *argXTy) {
vik
vikramRH wrote:
> @jayfoad's testcase fails and the same test should be repeated for all 3
> intrinsics
added MIR tests for 3 intrinsics. The issue is that Im not able to attach the
glue nodes to newly created laneop pieces since they fail at selection.
https://github.com/llvm/llvm-project/pu
@@ -0,0 +1,46 @@
+# RUN: not --crash llc -mtriple=amdgcn -run-pass=none -verify-machineinstrs -o
/dev/null %s 2>&1 | FileCheck %s
vikramRH wrote:
Okay, I'll update with IR's
https://github.com/llvm/llvm-project/pull/89217
___
vikramRH wrote:
> > > @jayfoad's testcase fails and the same test should be repeated for all 3
> > > intrinsics
> >
> >
> > added MIR tests for 3 intrinsics. The issue is that Im not able to attach
> > the glue nodes to newly created laneop pieces since they fail at selection.
> > #87509 sho
vikramRH wrote:
> > > > @jayfoad's testcase fails and the same test should be repeated for all
> > > > 3 intrinsics
> > >
> > >
> > > added MIR tests for 3 intrinsics. The issue is that Im not able to attach
> > > the glue nodes to newly created laneop pieces since they fail at
> > > selecti
vikramRH wrote:
> That's another option. The only real plus to the intermediate is it's
> slightly less annoying to write combines for. But there are limited combining
> opportunities for these
we now legalize to intrinsics directly. The SDAG lowering uses a new helper to
unroll vector ca
@@ -0,0 +1,65 @@
+; RUN: llc -stop-after=amdgpu-isel -mtriple=amdgcn-- -mcpu=gfx1100
-verify-machineinstrs -o - %s | FileCheck --check-prefixes=CHECK,ISEL %s
+
+; CHECK-LABEL: name:basic_readfirstlane_i64
+; CHECK:[[TOKEN:%[0-9]+]]{{[^ ]*}} = CONVERGENCECTRL
@@ -0,0 +1,65 @@
+; RUN: llc -stop-after=amdgpu-isel -mtriple=amdgcn-- -mcpu=gfx1100
-verify-machineinstrs -o - %s | FileCheck --check-prefixes=CHECK,ISEL %s
+
+; CHECK-LABEL: name:basic_readfirstlane_i64
+; CHECK:[[TOKEN:%[0-9]+]]{{[^ ]*}} = CONVERGENCECTRL
https://github.com/vikramRH edited
https://github.com/llvm/llvm-project/pull/89217
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
@@ -0,0 +1,65 @@
+; RUN: llc -stop-after=amdgpu-isel -mtriple=amdgcn-- -mcpu=gfx1100
-verify-machineinstrs -o - %s | FileCheck --check-prefixes=CHECK,ISEL %s
+
+; CHECK-LABEL: name:basic_readfirstlane_i64
+; CHECK:[[TOKEN:%[0-9]+]]{{[^ ]*}} = CONVERGENCECTRL
vikramRH wrote:
@yuanfang-chen , @AaronBallman, @shafik, are we still actively looking into
this ? (I would be willing to commandeer this if its not high on your priority
list)
https://github.com/llvm/llvm-project/pull/72607
___
cfe-commits mailing
@@ -18479,6 +18479,28 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned
BuiltinID,
CGM.getIntrinsic(Intrinsic::amdgcn_update_dpp, Args[0]->getType());
return Builder.CreateCall(F, Args);
}
+ case AMDGPU::BI__builtin_amdgcn_permlane16:
+ case AMDGPU::BI_
vikramRH wrote:
Updated this PR to be in sync with #89217, However still plan is to land this
land this only after changes in #89217 are accepted.
https://github.com/llvm/llvm-project/pull/92725
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
vikramRH wrote:
> Hello @vikramRH, please feel free to commandeer this.
Thanks @yuanfang-chen. Also, clang already rejects expressions like &V[0]
(https://godbolt.org/z/eGcxzGo66), which is also true with constexprs and this
PR. What's the specific concern here ?
https://github.com/llvm/llvm-
@@ -6086,6 +6086,63 @@ static SDValue lowerBALLOTIntrinsic(const
SITargetLowering &TLI, SDNode *N,
DAG.getConstant(0, SL, MVT::i32), DAG.getCondCode(ISD::SETNE));
}
+static SDValue lowerLaneOp(const SITargetLowering &TLI, SDNode *N,
+ Selection
https://github.com/vikramRH edited
https://github.com/llvm/llvm-project/pull/92725
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
vikramRH wrote:
1. Added/updated tests for permlanex16, permlane64
2. This needs https://github.com/llvm/llvm-project/pull/89217 to land first so
that only incremental changes can be reviewed.
https://github.com/llvm/llvm-project/pull/92725
___
cfe-c
https://github.com/vikramRH edited
https://github.com/llvm/llvm-project/pull/89217
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
@@ -6086,6 +6086,63 @@ static SDValue lowerBALLOTIntrinsic(const
SITargetLowering &TLI, SDNode *N,
DAG.getConstant(0, SL, MVT::i32), DAG.getCondCode(ISD::SETNE));
}
+static SDValue lowerLaneOp(const SITargetLowering &TLI, SDNode *N,
+ Selection
@@ -5387,6 +5387,124 @@ bool
AMDGPULegalizerInfo::legalizeDSAtomicFPIntrinsic(LegalizerHelper &Helper,
return true;
}
+// TODO: Fix pointer type handling
+bool AMDGPULegalizerInfo::legalizeLaneOp(LegalizerHelper &Helper,
+ MachineInst
@@ -1170,6 +1170,23 @@ The AMDGPU backend implements the following LLVM IR
intrinsics.
:ref:`llvm.set.fpenv` Sets the floating point
environment to the specifies state.
+ llvm.amdgcn.readfirstlaneProvides direct access to
v_readfirstl
@@ -6086,6 +6086,63 @@ static SDValue lowerBALLOTIntrinsic(const
SITargetLowering &TLI, SDNode *N,
DAG.getConstant(0, SL, MVT::i32), DAG.getCondCode(ISD::SETNE));
}
+static SDValue lowerLaneOp(const SITargetLowering &TLI, SDNode *N,
+ Selection
@@ -1170,6 +1170,23 @@ The AMDGPU backend implements the following LLVM IR
intrinsics.
:ref:`llvm.set.fpenv` Sets the floating point
environment to the specifies state.
+ llvm.amdgcn.readfirstlaneProvides direct access to
v_readfirstl
@@ -5461,8 +5461,7 @@ bool AMDGPULegalizerInfo::legalizeLaneOp(LegalizerHelper
&Helper,
SmallVector PartialRes;
unsigned NumParts = Size / 32;
- MachineInstrBuilder Src0Parts, Src2Parts;
- Src0Parts = B.buildUnmerge(PartialResTy, Src0);
+ MachineInstrBuilder Src0Parts
@@ -5496,6 +5496,9 @@ const char*
AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
NODE_NAME_CASE(LDS)
NODE_NAME_CASE(FPTRUNC_ROUND_UPWARD)
NODE_NAME_CASE(FPTRUNC_ROUND_DOWNWARD)
+ NODE_NAME_CASE(READLANE)
+ NODE_NAME_CASE(READFIRSTLANE)
---
vikramRH wrote:
> You should add the mentioned convergence-tokens.ll test function
Added the test in a separate test file
https://github.com/llvm/llvm-project/pull/89217
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cg
vikramRH wrote:
Added/updated tests for readfirstlane and writelane ops
https://github.com/llvm/llvm-project/pull/89217
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
vikramRH wrote:
Gentle ping :)
https://github.com/llvm/llvm-project/pull/89217
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
@@ -4822,6 +4822,111 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr
&MI,
return RetBB;
}
+static MachineBasicBlock *lowerPseudoLaneOp(MachineInstr &MI,
vikramRH wrote:
@arsenm, would "PreISelIntrinsicLowering" be a proper place for this ?
https
https://github.com/vikramRH created
https://github.com/llvm/llvm-project/pull/101126
None
>From 690901f2370381285afa7cf7c2f7401d89e568f6 Mon Sep 17 00:00:00 2001
From: Vikram
Date: Mon, 29 Jul 2024 08:56:07 -0400
Subject: [PATCH] [clang][ExprConst] allow single element access of vector
object
vikramRH wrote:
* **#101126** https://app.graphite.dev/github/pr/llvm/llvm-project/101126?utm_source=stack-comment-icon";
target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite"
width="10px" height="10px"/> 👈
* `main`
This stack of pull requests is managed by Grap
https://github.com/vikramRH edited
https://github.com/llvm/llvm-project/pull/101126
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
https://github.com/vikramRH ready_for_review
https://github.com/llvm/llvm-project/pull/101126
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
@@ -442,6 +446,16 @@ namespace {
MostDerivedArraySize = 2;
MostDerivedPathLength = Entries.size();
}
+
+void addVectorElementUnchecked(QualType EltTy, uint64_t Size,
+ uint64_t Idx) {
+ Entries.push_back(PathEntry::Arra
@@ -3,40 +3,40 @@
typedef int __attribute__((vector_size(16))) VI4;
constexpr VI4 A = {1,2,3,4};
-static_assert(A[0] == 1, ""); // ref-error {{not an integral constant
expression}}
-static_assert(A[1] == 2, ""); // ref-error {{not an integral constant
expression}}
-static_as
vikramRH wrote:
new commit extends @jayfoad's implementation with GIsel support. yet to add
tests for half, floats and some vectors
https://github.com/llvm/llvm-project/pull/89217
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.
vikramRH wrote:
1. Review comments
2. improve GIsel lowering
3. add tests for half, bfloat, float2, ptr, vector of ptr and int
4. removed gfx700 checks from writelane test since it caused issues with f16
legalization. is this required ?
https://github.com/llvm/llvm-project/pull/89217
__
https://github.com/vikramRH edited
https://github.com/llvm/llvm-project/pull/89217
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
@@ -5386,6 +5386,130 @@ bool
AMDGPULegalizerInfo::legalizeDSAtomicFPIntrinsic(LegalizerHelper &Helper,
return true;
}
+bool AMDGPULegalizerInfo::legalizeLaneOp(LegalizerHelper &Helper,
+ MachineInstr &MI,
+
1 - 100 of 170 matches
Mail list logo
