[clang] [NVPTX][AMDGPU][CodeGen] Fix `local_space nullptr` handling for NVPTX and local/private `nullptr` value for AMDGPU. (PR #78759)

2024-01-25 Thread Victor Lomuller via cfe-commits
@@ -285,6 +289,20 @@ void NVPTXTargetCodeGenInfo::addNVVMMetadata(llvm::GlobalValue *GV, bool NVPTXTargetCodeGenInfo::shouldEmitStaticExternCAliases() const { return false; } + +llvm::Constant * +NVPTXTargetCodeGenInfo::getNullPointer(const CodeGen::CodeGenModule &CGM, +

[clang] [NVPTX][AMDGPU][CodeGen] Fix `local_space nullptr` handling for NVPTX and local/private `nullptr` value for AMDGPU. (PR #78759)

2024-01-25 Thread Victor Lomuller via cfe-commits
@@ -418,8 +418,10 @@ class LLVM_LIBRARY_VISIBILITY AMDGPUTargetInfo final : public TargetInfo { // value ~0. uint64_t getNullPointerValue(LangAS AS) const override { // FIXME: Also should handle region. -return (AS == LangAS::opencl_local || AS == LangAS::opencl_pr

[clang] [clang][NVPTX] Define macro indicating the PTX version (PR #94934)

2024-06-09 Thread Victor Lomuller via cfe-commits
https://github.com/Naghasan created https://github.com/llvm/llvm-project/pull/94934 Define __PTX_VERSION__ macro to indicate the used PTX version. Usually each new PTX version brings a new sm version and the associated instructions. However, some of these instructions can also be made avialabl

[clang] [clang][NVPTX] Define macro indicating the PTX version (PR #94934)

2024-06-18 Thread Victor Lomuller via cfe-commits
Naghasan wrote: @Artem-B could you have a look ? I think you are the most relevant for this, thanks. (Sorry I can't manage assignment) https://github.com/llvm/llvm-project/pull/94934 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://list

[clang] [clang][NVPTX] Define macro indicating the PTX version (PR #94934)

2024-07-09 Thread Victor Lomuller via cfe-commits
Naghasan wrote: ping https://github.com/llvm/llvm-project/pull/94934 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][NVPTX] Define macro indicating the PTX version (PR #94934)

2024-06-27 Thread Victor Lomuller via cfe-commits
Naghasan wrote: Thanks for setting the reviewer > Can you please include rationale for why this this name e.g. why not > __NVPTX_VERSION__? `NVPTX` is the name of the LLVM backend, `PTX` is the name of assembly which have a version hence `__PTX_VERSION__`. Happy to use a better name, but it i

[clang] [clang][NVPTX] Define macro indicating the PTX version (PR #94934)

2024-06-27 Thread Victor Lomuller via cfe-commits
https://github.com/Naghasan edited https://github.com/llvm/llvm-project/pull/94934 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][NVPTX] Define macro indicating the PTX version (PR #94934)

2024-06-27 Thread Victor Lomuller via cfe-commits
Naghasan wrote: Still I forgot to answer this point as well... > Are there ever point releases that might mea +ptx78 should actually expand to > 780 rather than 78? not sure what you exactly mean with your question. I guess we can mirror the cuda arch macro so, major * 100 + minor * 10, no op

[clang] [llvm] [llvm][opt][Transforms][SPIR-V] Enable `InferAddressSpaces` for SPIR-V (PR #110897)

2024-10-16 Thread Victor Lomuller via cfe-commits
@@ -91,6 +97,88 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T, const Triple &TT, setRequiresStructuredCFG(false); } +enum AddressSpace { + Function = storageClassToAddressSpace(SPIRV::StorageClass::Function), + CrossWorkgroup = + storageClassToAddressSpac

[clang] [llvm] [llvm][opt][Transforms][SPIR-V] Enable `InferAddressSpaces` for SPIR-V (PR #110897)

2024-11-28 Thread Victor Lomuller via cfe-commits
@@ -91,6 +97,88 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T, const Triple &TT, setRequiresStructuredCFG(false); } +enum AddressSpace { + Function = storageClassToAddressSpace(SPIRV::StorageClass::Function), + CrossWorkgroup = + storageClassToAddressSpac

[clang] [llvm] [llvm][opt][Transforms][SPIR-V] Enable `InferAddressSpaces` for SPIR-V (PR #110897)

2024-11-28 Thread Victor Lomuller via cfe-commits
@@ -92,6 +98,63 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T, const Triple &TT, setRequiresStructuredCFG(false); } +enum AddressSpace { + Function = storageClassToAddressSpace(SPIRV::StorageClass::Function), + CrossWorkgroup = + storageClassToAddressSpac

[clang] [llvm] [llvm][opt][Transforms][SPIR-V] Enable `InferAddressSpaces` for SPIR-V (PR #110897)

2024-11-28 Thread Victor Lomuller via cfe-commits
@@ -92,6 +98,63 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T, const Triple &TT, setRequiresStructuredCFG(false); } +enum AddressSpace { + Function = storageClassToAddressSpace(SPIRV::StorageClass::Function), + CrossWorkgroup = + storageClassToAddressSpac

[clang] [llvm] [llvm][opt][Transforms][SPIR-V] Enable `InferAddressSpaces` for SPIR-V (PR #110897)

2024-11-28 Thread Victor Lomuller via cfe-commits
@@ -91,6 +97,88 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T, const Triple &TT, setRequiresStructuredCFG(false); } +enum AddressSpace { + Function = storageClassToAddressSpace(SPIRV::StorageClass::Function), + CrossWorkgroup = + storageClassToAddressSpac

[clang] [llvm] [llvm][opt][Transforms][SPIR-V] Enable `InferAddressSpaces` for SPIR-V (PR #110897)

2024-12-02 Thread Victor Lomuller via cfe-commits
@@ -91,6 +97,88 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T, const Triple &TT, setRequiresStructuredCFG(false); } +enum AddressSpace { + Function = storageClassToAddressSpace(SPIRV::StorageClass::Function), + CrossWorkgroup = + storageClassToAddressSpac

[clang] [llvm] [llvm][opt][Transforms][SPIR-V] Enable `InferAddressSpaces` for SPIR-V (PR #110897)

2024-12-10 Thread Victor Lomuller via cfe-commits
@@ -91,6 +97,88 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T, const Triple &TT, setRequiresStructuredCFG(false); } +enum AddressSpace { + Function = storageClassToAddressSpace(SPIRV::StorageClass::Function), + CrossWorkgroup = + storageClassToAddressSpac

[clang] [Clang][SYCL] Add AOT compilation support for Intel GPUs in clang-sycl-linker (PR #133194)

2025-04-04 Thread Victor Lomuller via cfe-commits
@@ -0,0 +1,131 @@ +//===--- SYCL.h -*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [Clang][SYCL] Add AOT compilation support for Intel GPUs in clang-sycl-linker (PR #133194)

2025-04-03 Thread Victor Lomuller via cfe-commits
@@ -0,0 +1,131 @@ +//===--- SYCL.h -*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap