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@@ -13725,12 +13725,10 @@ void
ASTContext::getFunctionFeatureMap(llvm::StringMap &FeatureMap,
// Make a copy of the features as passed on the command line into the
// beginning of the additional features from the function to override.
-// AArch64 handles command l
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@@ -114,12 +114,14 @@ using ExtensionBitset = Bitset;
// SubtargetFeature which may represent either an actual extension or some
// internal LLVM property.
struct ExtensionInfo {
- StringRef Name; // Human readable name, e.g. "profile".
+ StringRef UserVisible
@@ -114,12 +114,14 @@ using ExtensionBitset = Bitset;
// SubtargetFeature which may represent either an actual extension or some
// internal LLVM property.
struct ExtensionInfo {
- StringRef Name; // Human readable name, e.g. "profile".
+ StringRef UserVisible
@@ -114,12 +114,14 @@ using ExtensionBitset = Bitset;
// SubtargetFeature which may represent either an actual extension or some
// internal LLVM property.
struct ExtensionInfo {
- StringRef Name; // Human readable name, e.g. "profile".
+ StringRef UserVisible
@@ -23,6 +23,7 @@
class Extension<
string TargetFeatureName,// String used for -target-feature and
-march, unless overridden.
string Spelling, // The XYZ in HasXYZ and AEK_XYZ.
+ string ArchitectureFeatureName, // The extension's "FEAT
@@ -116,7 +116,9 @@ const AArch64::ArchInfo *AArch64::parseArch(StringRef Arch)
{
std::optional
AArch64::parseArchExtension(StringRef ArchExt) {
for (const auto &A : Extensions) {
-if (ArchExt == A.Name || ArchExt == A.Alias)
+if (A.UserVisibleName.empty() && !A.Alia
@@ -19,3 +19,19 @@
// RUN: %clang --target=arm64 -mlittle-endian -march=armv8.1a -### -c %s 2>&1
| FileCheck -check-prefix=ARM64-GENERICV81A %s
// RUN: %clang --target=arm64 -mlittle-endian -march=armv8.1-a -### -c %s 2>&1
| FileCheck -check-prefix=ARM64-GENERICV81A %s
// ARM
@@ -19,3 +19,19 @@
// RUN: %clang --target=arm64 -mlittle-endian -march=armv8.1a -### -c %s 2>&1
| FileCheck -check-prefix=ARM64-GENERICV81A %s
// RUN: %clang --target=arm64 -mlittle-endian -march=armv8.1-a -### -c %s 2>&1
| FileCheck -check-prefix=ARM64-GENERICV81A %s
// ARM
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LGTM
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>From b3e9e2f313d3c3a51b7b6690a5cca67a3ec87dd6 Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Tue, 18 Jun 2024 22:23:11 +0100
Subject: [PATCH] [AArch64][TargetParser] Split FMV and extensions
---
cla
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>From b3e9e2f313d3c3a51b7b6690a5cca67a3ec87dd6 Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Tue, 18 Jun 2024 22:23:11 +0100
Subject: [PATCH 1/2] [AArch64][TargetParser] Split FMV and extensions
---
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>From b3e9e2f313d3c3a51b7b6690a5cca67a3ec87dd6 Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Tue, 18 Jun 2024 22:23:11 +0100
Subject: [PATCH 1/2] [AArch64][TargetParser] Split FMV and extensions
---
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/92882
>From b3e9e2f313d3c3a51b7b6690a5cca67a3ec87dd6 Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Tue, 18 Jun 2024 22:23:11 +0100
Subject: [PATCH 1/3] [AArch64][TargetParser] Split FMV and extensions
---
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/92882
>From b3e9e2f313d3c3a51b7b6690a5cca67a3ec87dd6 Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Tue, 18 Jun 2024 22:23:11 +0100
Subject: [PATCH 1/4] [AArch64][TargetParser] Split FMV and extensions
---
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/92882
>From b3e9e2f313d3c3a51b7b6690a5cca67a3ec87dd6 Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Tue, 18 Jun 2024 22:23:11 +0100
Subject: [PATCH 1/4] [AArch64][TargetParser] Split FMV and extensions
---
tmatheson-arm wrote:
> Looking good Tomas and thanks for your effort to tidy things up. I know this
> is NFC, but can we rectify the implied features for rcpc2 and rcpc3 by adding
> rcpc-immo as shown here
> https://github.com/llvm/llvm-project/pull/92319/files#diff-0df0a19b911b768165642047ad8
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LGTM
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>From 76ccb775de5103dde3b59b838ba3f71be367418d Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Tue, 21 May 2024 09:36:48 +0100
Subject: [PATCH] Separate FMV and Extensions
---
clang/include/clang/AST/
@@ -0,0 +1,84 @@
+// Function MultiVersioning (FMV) properties
+
+// Something you can add to target_version or target_clones
+class FMVExtension {
+// Name, as spelled in target_version or target_clones. e.g. "memtag"
+string Name = n;
+
+// A C++ expression giving th
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>From 76ccb775de5103dde3b59b838ba3f71be367418d Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Tue, 21 May 2024 09:36:48 +0100
Subject: [PATCH 1/2] Separate FMV and Extensions
---
clang/include/clang/
@@ -13754,11 +13760,14 @@ void
ASTContext::getFunctionFeatureMap(llvm::StringMap &FeatureMap,
}
Target->initFeatureMap(FeatureMap, getDiagnostics(), TargetCPU, Features);
} else if (const auto *TV = FD->getAttr()) {
-std::vector Feats = filterFunctionTargetVersio
https://github.com/tmatheson-arm edited
https://github.com/llvm/llvm-project/pull/93695
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@@ -286,7 +286,6 @@ void AArch64TargetInfo::getTargetDefinesARMV84A(const
LangOptions &Opts,
void AArch64TargetInfo::getTargetDefinesARMV85A(const LangOptions &Opts,
MacroBuilder &Builder) const {
Builder.defineMacro("__ARM_FEA
https://github.com/tmatheson-arm updated
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>From 518b83ab69c4852f7e7ea71c17df3f58e8ff50ef Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Fri, 17 May 2024 21:39:17 +0100
Subject: [PATCH 1/3] [AArch64] set AppleA14 architecture version to 8.5
--
@@ -718,12 +718,16 @@ def ProcessorFeatures {
list AppleA13 = [HasV8_4aOps, FeatureCrypto,
FeatureFPARMv8,
FeatureNEON, FeaturePerfMon,
FeatureFullFP16,
FeatureFP16FML, FeatureSHA3];
+ // Apple A14 a
@@ -250,13 +248,17 @@ void AArch64::ExtensionSet::addArchDefaults(const
ArchInfo &Arch) {
bool AArch64::ExtensionSet::parseModifier(StringRef Modifier) {
LLVM_DEBUG(llvm::dbgs() << "parseModifier(" << Modifier << ")\n");
- bool IsNegated = Modifier.starts_with("no");
- St
@@ -13663,17 +13664,18 @@ QualType
ASTContext::getCorrespondingSignedFixedPointType(QualType Ty) const {
}
}
-std::vector ASTContext::filterFunctionTargetVersionAttrs(
-const TargetVersionAttr *TV) const {
- assert(TV != nullptr);
- llvm::SmallVector Feats;
- std::ve
@@ -166,6 +174,11 @@ void AArch64::ExtensionSet::enable(ArchExtKind E) {
Touched.set(E);
Enabled.set(E);
+ // These depend on each other, meaning you can't have one without the other.
+ // We don't want this to be in ExtensionDependencies to avoid infinite loops.
+ if (
@@ -106,7 +106,7 @@ def FeatureFPARMv8 : Extension<"fp-armv8", "FPARMv8",
"Enable ARMv8 (FEAT_FP)", [],
"FEAT_FP", "+fp-armv8,+neon", 90>;
-let ArchExtKindSpelling = "AEK_SIMD", MArchName = "simd" in
+let ArchExtKindSpelling = "AEK_SIMD", MArchName = "simd", MArchAlias = "
@@ -69,8 +69,8 @@ void undefined(uint32x2_t v2i32, uint32x4_t v4i32, uint16x8_t
v8i16, uint8x16_t
vrnd_f16(v4f16); // expected-error {{always_inline function 'vrnd_f16'
requires target feature 'fullfp16'}}
vmaxnm_f16(v4f16, v4f16); // expected-error {{always_inline functio
@@ -265,6 +267,21 @@ bool AArch64::ExtensionSet::parseModifier(StringRef
Modifier) {
return false;
}
+void AArch64::ExtensionSet::reconstructFromParsedFeatures(
+std::vector &Features) {
tmatheson-arm wrote:
```suggestion
const std::vector &Feature
@@ -250,13 +248,17 @@ void AArch64::ExtensionSet::addArchDefaults(const
ArchInfo &Arch) {
bool AArch64::ExtensionSet::parseModifier(StringRef Modifier) {
LLVM_DEBUG(llvm::dbgs() << "parseModifier(" << Modifier << ")\n");
- bool IsNegated = Modifier.starts_with("no");
- St
@@ -5,13 +5,18 @@
// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -S -emit-llvm
-o - -mbranch-protection=pac-ret+b-key %s | FileCheck %s --check-prefix=CHECK
--check-prefix=PART
// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -S -emit-llvm
-o - -
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@@ -2323,15 +2323,33 @@ void Verifier::verifyFunctionAttrs(FunctionType *FT,
AttributeList Attrs,
if (S != "a_key" && S != "b_key")
CheckFailed("invalid value for 'sign-return-address-key' attribute: " +
S,
V);
+if (auto AA = Attrs.getFnAttr("s
@@ -2323,15 +2323,33 @@ void Verifier::verifyFunctionAttrs(FunctionType *FT,
AttributeList Attrs,
if (S != "a_key" && S != "b_key")
CheckFailed("invalid value for 'sign-return-address-key' attribute: " +
S,
V);
+if (auto AA = Attrs.getFnAttr("s
https://github.com/tmatheson-arm commented:
In general LGTM. This seems like a better approach. The summary could do with
clarification, it is hard to understand.
https://github.com/llvm/llvm-project/pull/82819
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@@ -0,0 +1,22 @@
+// REQUIRES: arm-registered-target
+
+// RUN: %clang_cc1 -triple=thumbv7m-unknown-unknown-eabi
-msign-return-address=non-leaf %s -S -emit-llvm -o - 2>&1 | FileCheck %s
--check-prefix=CHECK --check-prefix=SIGN
+// RUN: %clang_cc1 -triple=thumbv7m-unknown-unknown
@@ -58,8 +58,8 @@ entry:
;; CHECK-NEXT: .cfi_negate_ra_state
attributes #0 = { norecurse nounwind readnone "sign-return-address"="all"
"sign-return-address-key"="b_key" }
-attributes #1 = { noinline }
-attributes #2 = { nofree noinline norecurse nounwind writeonly }
+attribut
@@ -22,4 +22,9 @@ attributes #1 = {
; CHECK: invalid value for 'sign-return-address-key' attribute: B_Key
"sign-return-address-key"="B_Key"
; CHECK: invalid value for 'branch-target-enforcement' attribute: True
- "branch-target-enforcement"="True" }
+ "branch-target-enfor
@@ -61,12 +61,12 @@ entry:
;; CHECK: paciasp
;; CHECK: retaa
-attributes #0 = { nounwind "branch-target-enforcement"="false"
"sign-return-address"="none" }
-attributes #1 = { nounwind "branch-target-enforcement"="true"
"sign-return-address"="none" }
-attributes
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@@ -895,7 +895,10 @@ def ProcessorFeatures {
FeatureLSE, FeaturePAuth, FeatureFPAC,
FeatureRAS, FeatureRCPC, FeatureRDM,
FeatureBF16, FeatureDotProd,
FeatureMatMulInt
tmatheson-arm wrote:
This looks like the right direction to go.
https://github.com/llvm/llvm-project/pull/106304
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@@ -305,9 +305,17 @@ def FeatureWFxT : ExtensionWithMArch<"wfxt", "WFxT",
"FEAT_WFxT",
def FeatureHCX : Extension<"hcx", "HCX", "FEAT_HCX",
"Enable Armv8.7-A HCRX_EL2 system register">;
-def FeatureLS64 : ExtensionWithMArch<"ls64", "LS64",
- "FEAT_LS64, FEAT_LS64_V, FEAT_L
@@ -305,9 +305,17 @@ def FeatureWFxT : ExtensionWithMArch<"wfxt", "WFxT",
"FEAT_WFxT",
def FeatureHCX : Extension<"hcx", "HCX", "FEAT_HCX",
"Enable Armv8.7-A HCRX_EL2 system register">;
-def FeatureLS64 : ExtensionWithMArch<"ls64", "LS64",
- "FEAT_LS64, FEAT_LS64_V, FEAT_L
@@ -3682,6 +3682,8 @@ static const struct Extension {
{"sve2-bitperm", {AArch64::FeatureSVE2BitPerm}},
{"sve2p1", {AArch64::FeatureSVE2p1}},
{"ls64", {AArch64::FeatureLS64}},
+{"ls64_v", {AArch64::FeatureLS64_V}},
+{"ls64_accdata", {AArch64::FeatureLS64_ACCD
tmatheson-arm wrote:
Can something be done to prevent this happening accidentally again?
https://github.com/llvm/llvm-project/pull/98307
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tmatheson-arm wrote:
Whatever the solution is, it would be better off done now, as "in future" is
likely to get forgotten.
https://github.com/llvm/llvm-project/pull/98307
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@@ -141,7 +141,7 @@ class ARMTargetCodeGenInfo : public TargetCodeGenInfo {
ParsedTargetAttr Attr =
CGM.getTarget().parseTargetAttr(TA->getFeaturesStr());
if (!Attr.BranchProtection.empty()) {
-TargetInfo::BranchProtectionInfo BPI;
+TargetI
@@ -1434,7 +1434,14 @@ class TargetInfo : public TransferrableTargetInfo,
}
public:
-BranchProtectionInfo() = default;
+BranchProtectionInfo() {
+ SignReturnAddr = LangOptions::SignReturnAddressScopeKind::None;
+ SignKey = LangOptions::SignReturnAddress
@@ -161,14 +161,10 @@ struct CpuInfo {
StringRef Name; // Name, as written for -mcpu.
const ArchInfo &Arch;
AArch64::ExtensionBitset
- DefaultExtensions; // Default extensions for this CPU. These will be
- // ORd with the architecture defaults
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LGTM. I haven't checked all the CPU feature changes, but the tests give a lot
of confidence. I also haven't checked all the TRMs but the changes there make
sense given the MEC/RME architecture changes.
https://github.com/llvm/llvm-pr
@@ -1626,7 +1628,7 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_FP16FML, AArch64::AEK_SHA3,AArch64::AEK_BF16,
AArch64::AEK_I8MM,AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
AArch64::AEK_PAUTH, AArch64::AEK_PERFMON, AArch64::AEK_HCX}),
-
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LGTM. Seems like there are still many more inconsistencies that could be
improved too.
https://github.com/llvm/llvm-project/pull/98550
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@@ -65,7 +65,7 @@ class ExtensionWithMArch<
let ArchExtKindSpelling = "AEK_FP", UserVisibleName = "fp" in
def FeatureFPARMv8 : ExtensionWithMArch<"fp-armv8", "FPARMv8", "FEAT_FP",
- "Enable ARMv8">;
+ "Enable Armv8.0-A Floating Point Extensions">;
tmatheson-
@@ -210,29 +210,29 @@ def FeatureDotProd : ExtensionWithMArch<"dotprod",
"DotProd", "FEAT_DotProd",
"Enable dot product support", [FeatureNEON]>;
def FeatureMPAM : Extension<"mpam", "MPAM", "FEAT_MPAM",
- "Enable v8.4-A Memory system Partitioning and Monitoring extension">
@@ -89,14 +89,14 @@ def FeatureCrypto : ExtensionWithMArch<"crypto", "Crypto",
"FEAT_Crypto",
"Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>;
def FeatureCRC : ExtensionWithMArch<"crc", "CRC", "FEAT_CRC32",
- "Enable ARMv8 CRC-32 checksum instr
@@ -106,24 +106,24 @@ def FeatureSpecRestrict : Extension<"specrestrict",
"SpecRestrict", "FEAT_CSV2_2
//===--===//
def FeatureLSE : ExtensionWithMArch<"lse", "LSE", "FEAT_LSE",
- "Enable ARMv8.1 Large Syst
@@ -472,22 +472,22 @@ def FeatureFP8 : ExtensionWithMArch<"fp8", "FP8",
"FEAT_FP8",
"Enable FP8 instructions", [FeatureFAMINMAX, FeatureLUT, FeatureBF16]>;
def FeatureFP8FMA : ExtensionWithMArch<"fp8fma", "FP8FMA", "FEAT_FP8FMA",
- "Enable fp8 multiply-add instructions",
tmatheson-arm wrote:
> Seems like there are still many more inconsistencies that could be improved
> too.
To be clear, I'm not suggesting you need to do them in this PR.
https://github.com/llvm/llvm-project/pull/98550
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@@ -161,14 +161,10 @@ struct CpuInfo {
StringRef Name; // Name, as written for -mcpu.
const ArchInfo &Arch;
AArch64::ExtensionBitset
- DefaultExtensions; // Default extensions for this CPU. These will be
- // ORd with the architecture defaults
https://github.com/tmatheson-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/98698
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Author: Tomas Matheson
Date: 2024-05-01T18:01:14+01:00
New Revision: 6c369cf937b7d9acb98a1fc46b1340cef7703e12
URL:
https://github.com/llvm/llvm-project/commit/6c369cf937b7d9acb98a1fc46b1340cef7703e12
DIFF:
https://github.com/llvm/llvm-project/commit/6c369cf937b7d9acb98a1fc46b1340cef7703e12.diff
https://github.com/tmatheson-arm edited
https://github.com/llvm/llvm-project/pull/90320
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tmatheson-arm wrote:
I agree with the other comments, and also I think changes like this should not
go in this fast and with so few eyes on them.
https://github.com/llvm/llvm-project/pull/90928
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h
tmatheson-arm wrote:
Thanks for the comments everyone. Given that this requires an IR break and
additions to the importer, and there is still some question about which way to
go with the renaming (i.e. FEAT_ names or user-facing names) I think it makes
sense to defer renaming until later. For
https://github.com/tmatheson-arm closed
https://github.com/llvm/llvm-project/pull/90320
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https://github.com/tmatheson-arm created
https://github.com/llvm/llvm-project/pull/91490
None
>From 9097058fe1c6e661efe60899f0da7cfd966c6ee7 Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Wed, 8 May 2024 16:42:24 +0100
Subject: [PATCH] [AArch64] add some more tests for FMV
---
clang/tes
https://github.com/tmatheson-arm edited
https://github.com/llvm/llvm-project/pull/91490
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https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/91490
>From 9097058fe1c6e661efe60899f0da7cfd966c6ee7 Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Wed, 8 May 2024 16:42:24 +0100
Subject: [PATCH 1/3] [AArch64] add some more tests for FMV
---
clang/test/
@@ -0,0 +1,381 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --check-attributes --check-globals all --filter "define|attributes"
--include-generated-funcs --version 4
+
+// Test/document all of the dependencies between possible AArch
@@ -0,0 +1,381 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --check-attributes --check-globals all --filter "define|attributes"
--include-generated-funcs --version 4
+
+// Test/document all of the dependencies between possible AArch
@@ -0,0 +1,25 @@
+// Test which driver flags enable/disable Function Multiversioning on aarch64.
+
+// FMV is enabled for non-android aarch64 targets:
+// RUN: %clang --target=aarch64 --rtlib=compiler-rt -### -c %s 2>&1 |
FileCheck -check-prefix=FMV-ENABLED %s
+// RUN: %clang --t
tmatheson-arm wrote:
The autogenerated checks for `clang/test/CodeGen/aarch64-fmv-dependencies.c`
did not actually pass, due to changes in function ordering, so I have manually
written the check lines, which makes the intent clearer anyway.
Some things look odd to me:
- The "aes", "dgh", "fp",
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/90987
>From 4b8b776348438847c2eb238dac973e93fe93294e Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Mon, 29 Apr 2024 19:57:17 +0100
Subject: [PATCH 1/6] [AArch64] move extension information into tablgen
Gen
https://github.com/tmatheson-arm closed
https://github.com/llvm/llvm-project/pull/91490
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https://github.com/tmatheson-arm closed
https://github.com/llvm/llvm-project/pull/90987
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