@@ -683,6 +698,65 @@ struct AAAMDAttributesFunction : public AAAMDAttributes {
return !A.checkForAllCallLikeInstructions(DoesNotRetrieve, *this,
UsedAssumedInformation);
}
+
+ // Returns true if FlatScratchInit is needed, i.e
@@ -262,6 +262,18 @@ class AMDGPUInformationCache : public InformationCache {
return !HasAperture && (Access & ADDR_SPACE_CAST);
}
+ bool constHasASCastFromPrivate(const Constant *C, Function &Fn) {
shiltian wrote:
nit: function starts with a verb
htt
https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/115306
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shiltian wrote:
> Test that the unsupported clang builtins are errors?
Done.
https://github.com/llvm/llvm-project/pull/115190
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>From ee359e381d66b21f0b60974ee87f1a3443cb2ab9 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 6 Nov 2024 12:49:45 -0500
Subject: [PATCH] [AMDGPU] Introduce a new generic target `gfx9-4-generic`
---
cla
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/115190
>From e58b5c48036e9fd8bd1adcb1d3f73331e19dd53d Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 6 Nov 2024 12:49:45 -0500
Subject: [PATCH] [AMDGPU] Introduce a new generic target `gfx9-4-generic`
---
cla
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/115190
>From 629e974f35e5c7cd733458305c14b487deea67da Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 6 Nov 2024 12:49:45 -0500
Subject: [PATCH] [AMDGPU] Introduce a new generic target `gfx9-4-generic`
---
cla
shiltian wrote:
I'm not sure about this. What does `compiler-rt` provide?
https://github.com/llvm/llvm-project/pull/109152
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https://github.com/llvm/llvm-project/pull/108786
>From cad9ac7478a158c455b8865cab8bb553a46f7773 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Tue, 17 Sep 2024 21:47:45 -0400
Subject: [PATCH] [IR] Introduce `T` to `DataLayout` to
represent flat address spa
shiltian wrote:
ping
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shiltian wrote:
> Is there a value in not defining 0 as flat?
Like @AlexVlx mentioned, as well as the wording I put into `LangRef.rst`,
SPIR/SPIR-V uses AS 4 as flat AS.
> It's what we basically assume everywhere already, isn't it?
I don't think this is technically true, but it is unfortunate
shiltian wrote:
> I would like to avoid adding additional special properties to AS0, or
> defining the flat concept.
How can we add a new specification w/o defining it?
> The simple solution is just have a switch over the target architecture in
> Attributor.
That means in the future when a n
@@ -0,0 +1,187 @@
+//===-- amdgpuintrin.h - AMDPGU intrinsic functions
---===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,187 @@
+//===-- amdgpuintrin.h - AMDPGU intrinsic functions
---===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
shiltian wrote:
> I am wondering if it would be easier to provide generic builtins in clang and
> just codegen them. I guess in that case we'd just upscale everything to
> 64-bit and say "If you need the other one use the target specific version".
I'm not sure if that's a good idea. For simple
shiltian wrote:
The fix looks good. A test would be preferred.
https://github.com/llvm/llvm-project/pull/109366
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>From 7b6a66d635fdb522d6fe0046157971f9d5112982 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Tue, 17 Sep 2024 21:47:45 -0400
Subject: [PATCH] [IR] Introduce `T` to `DataLayout` to
represent flat address spa
shiltian wrote:
> Would it be possible to update the SPIR-V DataLayout(s) as well please?
> Caveat, those targets use 4 to denote Flat/Generic, see e.g.
> [here](https://github.com/llvm/llvm-project/blob/47c3df2a7fcdfb33064d4d5e7d82dde1ea379023/llvm/lib/Target/SPIRV/SPIRVUtils.cpp#L176)
> and
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/108786
>From 3052d9ab2225f32f0bed254f3d6eb64a096f3d5e Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Tue, 17 Sep 2024 21:47:45 -0400
Subject: [PATCH] [IR] Introduce `T` to `DataLayout` to
represent flat address spa
shiltian wrote:
> Why is that a DL property and not just a target property?
It is indeed a target property. DL is one choice here (if it is not the most
preferable one). Like I mentioned before, TTI and `TargetMachine` could have
been one, but not feasible. Where else do you suggest?
> Or eve
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shiltian wrote:
> > > I would like to avoid adding additional special properties to AS0, or
> > > defining the flat concept.
> >
> >
> > How can we add a new specification w/o defining it?
>
> By not defining it in terms of flat addressing. Just make it the undesirable
> address space
But t
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/108786
>From 4d86d8dc50b526ddca3de21709fe78ddafa7280e Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Tue, 17 Sep 2024 21:47:45 -0400
Subject: [PATCH] [IR] Introduce `T` to `DataLayout` to
represent flat address spa
shiltian wrote:
It's a good idea to make it more generic. Potentially we can add an API like
`isAddressSpaceOptimizable(unsigned AS)`. If we want to do that, the question
would be, where to put this API? Like I mentioned in the description, I tried
some similar approach but they didn't pan out
shiltian wrote:
I like this direction and I think it should be the right way. However, IMHO, I
think it needs discussion (and potentially an RFC).
https://github.com/llvm/llvm-project/pull/109152
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@@ -156,6 +157,8 @@ StringRef llvm::AMDGPU::getArchFamilyNameAMDGCN(GPUKind AK)
{
switch (AK) {
case AMDGPU::GK_GFX9_GENERIC:
return "gfx9";
+ case AMDGPU::GK_GFX9_4_GENERIC:
+return "gfx9";
shiltian wrote:
I suppose the family name is still `gfx
shiltian wrote:
* **#115190** https://app.graphite.dev/github/pr/llvm/llvm-project/115190?utm_source=stack-comment-icon";
target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite"
width="10px" height="10px"/> 👈
* `main`
This stack of pull requests is managed by Grap
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@@ -1468,15 +1471,36 @@ def FeatureISAVersion9_4_Common : FeatureSet<
def FeatureISAVersion9_4_0 : FeatureSet<
!listconcat(FeatureISAVersion9_4_Common.Features,
-[FeatureForceStoreSC0SC1])>;
+[
+ FeatureForceStoreSC0SC1,
+ FeatureFP8Insts,
+ FeatureFP8
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@@ -1468,15 +1471,36 @@ def FeatureISAVersion9_4_Common : FeatureSet<
def FeatureISAVersion9_4_0 : FeatureSet<
!listconcat(FeatureISAVersion9_4_Common.Features,
-[FeatureForceStoreSC0SC1])>;
+[
+ FeatureForceStoreSC0SC1,
+ FeatureFP8Insts,
https://github.com/shiltian commented:
Test
https://github.com/llvm/llvm-project/pull/115241
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@@ -17,6 +17,15 @@
typedef void *omp_depend_t;
void foo() {}
+void tmainc(){
+ omp_depend_t obj;
+#pragma omp depobj(obj) depend(inout: omp_all_memory)
+{
+ volatile omp_depend_t temp = obj;
+char* char_ptr = reinterpret_cast(temp);
+char_ptr[0] = 1;
+}
---
@@ -36,9 +45,24 @@ int main(int argc, char **argv) {
#pragma omp depobj(b) update(mutexinoutset)
#pragma omp depobj(a) depend(iterator(char *p = argv[argc]:argv[0]:-1), out:
p[0])
(void)tmain(a), tmain(b);
+ tmainc();
shiltian wrote:
here as well, at least
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@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 2
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942
-start-before=machine-scheduler -verify-misched -o - %s | FileCheck
-check-prefix=GCN %s
+# RUN: llc -mtriple
@@ -156,6 +157,8 @@ StringRef llvm::AMDGPU::getArchFamilyNameAMDGCN(GPUKind AK)
{
switch (AK) {
case AMDGPU::GK_GFX9_GENERIC:
return "gfx9";
+ case AMDGPU::GK_GFX9_4_GENERIC:
+return "gfx9";
shiltian wrote:
Define those macros like `__GFX9__`
ht
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/115190
>From 36713d37cb2852cea6f6095e2e6684428a1255fb Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 6 Nov 2024 12:49:45 -0500
Subject: [PATCH] [AMDGPU] Introduce a new generic target `gfx9-4-generic`
---
cla
shiltian wrote:
Still need to resolve the following test failures due to mismatch check lines
with gfx942.
```
LLVM :: CodeGen/AMDGPU/div-rem-by-constant-64.ll
LLVM :: CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.large.mir
LLVM :: CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.small.mir
```
https://
@@ -4683,13 +4683,22 @@ void CGOpenMPRuntime::emitTaskLoopCall(CodeGenFunction
&CGF, SourceLocation Loc,
Data.Schedule.getPointer()
? CGF.Builder.CreateIntCast(Data.Schedule.getPointer(), CGF.Int64Ty,
/*isSigned=*/false)
-
@@ -1780,6 +1786,15 @@ void CXXNameMangler::mangleDeviceStubName(const
IdentifierInfo *II) {
<< II->getName();
}
+void CXXNameMangler::mangleOCLDeviceStubName(const IdentifierInfo *II) {
+ // ::= __clang_ocl_kern_imp_
+ // ::= [n]
+ // ::=
+ StringRef OCLDevi
@@ -196,13 +203,21 @@ class GlobalDecl {
}
GlobalDecl getWithKernelReferenceKind(KernelReferenceKind Kind) {
-assert(isa(getDecl()) &&
- cast(getDecl())->hasAttr() &&
- "Decl is not a GPU kernel!");
+assert((isa(getDecl()) &&
+cast(g
@@ -0,0 +1,77 @@
+//===- AMDGPUArchByKFD.cpp - list AMDGPU installed --*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
shiltian wrote:
Maybe add this information into the beginning of the file.
https://github.com/llvm/llvm-project/pull/116651
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shiltian wrote:
> Here's a question, should it respect `ROCR_VISIBLE_DEVICES`?
I think it depends on whether you consider this as a ROCm toolchain. If not,
I'd prefer not to be bound to any ROCm related stuff.
https://github.com/llvm/llvm-project/pull/116651
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shiltian wrote:
Yes, that's the idea. In that way, we will not have any function call to a
`amdgpu_kernel`.
https://github.com/llvm/llvm-project/pull/115821
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@@ -0,0 +1,43 @@
+// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -emit-llvm -o - %s |
FileCheck %s
shiltian wrote:
I think we really need to force auto generate to make (other's) future life
much easier.
https://github.com/llvm/llvm-project/pull/115821
@@ -0,0 +1,256 @@
+// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -x c++
-emit-llvm %s -o - | FileCheck %s
shiltian wrote:
Can you auto generate the check lines?
https://github.com/llvm/llvm-project/pull/117196
___
@@ -0,0 +1,256 @@
+// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -x c++
-emit-llvm %s -o - | FileCheck %s
shiltian wrote:
This file look like auto generated but there is no head line at the beginning
of the file
https://github.com/llvm/llvm
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@@ -0,0 +1,43 @@
+// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -emit-llvm -o - %s |
FileCheck %s
shiltian wrote:
the pair can be "detected" or checked by the check lines and any minor change
could lead to a test failure, thus makes it more robust.
https:/
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@@ -3377,7 +3377,8 @@ static void encodeTypeForFunctionPointerAuth(const
ASTContext &Ctx,
#include "clang/Basic/HLSLIntangibleTypes.def"
case BuiltinType::Dependent:
llvm_unreachable("should never get here");
-case BuiltinType::AMDGPUBufferRsrc:
+#define AMDGPU_T
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https://github.com/llvm/llvm-project/pull/108786
>From 2546b9cef422ab60f75dfc1321a097ae22415a82 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Sun, 15 Sep 2024 21:53:50 -0400
Subject: [PATCH] [IR] Introduce `T` to `DataLayout` to
represent flat address spa
shiltian wrote:
Thank all for the valuable input. I changed the wording in `LangRef.rst`.
Hopefully it can make it more clear.
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>From 89eb7686f8304b33a8cacb639ced6c229b70f6ea Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Tue, 17 Sep 2024 21:47:45 -0400
Subject: [PATCH] [IR] Introduce `T` to `DataLayout` to
represent flat address spa
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/108786
>From feadf29036d9157fec452343cf768a6b78d018e5 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Tue, 17 Sep 2024 21:47:45 -0400
Subject: [PATCH] [IR] Introduce `T` to `DataLayout` to
represent flat address spa
@@ -245,6 +246,7 @@ class DataLayout {
unsigned getDefaultGlobalsAddressSpace() const {
return DefaultGlobalsAddrSpace;
}
+ unsigned getFlatAddressSpace() const { return FlatAddressSpace; }
shiltian wrote:
I added an enum such that all the checks can
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/108786
>From a4187bb5ca769ae3eac4dfe6ec57642640bb6e74 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Tue, 17 Sep 2024 21:47:45 -0400
Subject: [PATCH] [IR] Introduce `T` to `DataLayout` to
represent flat address spa
@@ -1780,6 +1786,15 @@ void CXXNameMangler::mangleDeviceStubName(const
IdentifierInfo *II) {
<< II->getName();
}
+void CXXNameMangler::mangleOCLDeviceStubName(const IdentifierInfo *II) {
+ // ::= __clang_ocl_kern_imp_
+ // ::= [n]
+ // ::=
+ StringRef OCLDevi
https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/118297
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https://github.com/shiltian created
https://github.com/llvm/llvm-project/pull/116435
AMDGPU disabled the use of `byval` for struct argument passing in commit
d77c620. However, when emitting `__enqueue_kernel_basic`, Clang still adds the
`byval` attribute by default. This PR introduces a target c
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/116435
>From 50b6941f3ee43f5c4e559112fbb3fd8fa9fb6016 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 15 Nov 2024 15:04:39 -0500
Subject: [PATCH] [Clang][AMDGPU] Avoid Using `byval` for `ndrange_t` when
emittin
shiltian wrote:
* **#116435** https://app.graphite.dev/github/pr/llvm/llvm-project/116435?utm_source=stack-comment-icon";
target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite"
width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/116
@@ -5985,10 +5985,14 @@ RValue CodeGenFunction::EmitBuiltinExpr(const
GlobalDecl GD, unsigned BuiltinID,
llvm::Value *Block =
Builder.CreatePointerCast(Info.BlockArg, GenericVoidPtrTy);
- AttrBuilder B(Builder.getContext());
- B.addByValAttr(NDRangeL
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>From c48f66338d05e21f2a60062cf825f4cba445d5d8 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 15 Nov 2024 15:04:39 -0500
Subject: [PATCH] [Clang][AMDGPU] Avoid Using `byval` for `ndrange_t` when
emittin
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shiltian wrote:
* **#118515** https://app.graphite.dev/github/pr/llvm/llvm-project/118515?utm_source=stack-comment-icon";
target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite"
width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/118
https://github.com/shiltian created
https://github.com/llvm/llvm-project/pull/118515
None
>From 537c973c88727c65faf39bd6e7e8d44b48837259 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Tue, 3 Dec 2024 11:25:37 -0500
Subject: [PATCH] [AMDGPU] Use COV6 by default
---
clang/include/clang/Drive
shiltian wrote:
@jplehr @ronlieb A heads-up for OpenMP folks. This change might be intrusive.
https://github.com/llvm/llvm-project/pull/118515
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shiltian wrote:
AFAIK it has nothing fancy for runtime.
https://github.com/llvm/llvm-project/pull/118515
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https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/118515
>From 169b95d90e1ae5660f400a65f8e5cd9a471accfb Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Tue, 3 Dec 2024 11:25:37 -0500
Subject: [PATCH] [AMDGPU] Use COV6 by default
---
clang/include/clang/Driver/Opti
Author: Shilei Tian
Date: 2024-12-03T12:12:58-05:00
New Revision: 5ae613c9b9dc37ec1b0a6d76714099375288d772
URL:
https://github.com/llvm/llvm-project/commit/5ae613c9b9dc37ec1b0a6d76714099375288d772
DIFF:
https://github.com/llvm/llvm-project/commit/5ae613c9b9dc37ec1b0a6d76714099375288d772.diff
L
shiltian wrote:
> > AFAIK it has nothing fancy for runtime.
>
> The `libc` CMake has a variable that sets it to 5, might be worth bumping
> that up since it's actively tested. It's in the
> `prepare_libc_gpu_build.cmake`.
Done.
https://github.com/llvm/llvm-project/pull/118515
___
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/118515
>From 57fa521750d902926d210eb9d783a9cbed71ef36 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Tue, 3 Dec 2024 11:25:37 -0500
Subject: [PATCH] [AMDGPU] Use COV6 by default
---
clang/include/clang/Driver/Opti
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/118515
>From dc6f54cd68819ad280e004f3969fd61db94f31b4 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Tue, 3 Dec 2024 11:25:37 -0500
Subject: [PATCH] [AMDGPU] Use COV6 by default
---
clang/docs/ReleaseNotes.rst
Author: Shilei Tian
Date: 2024-12-03T12:27:04-05:00
New Revision: 95a4d30b0d64c544106acf306c3d3fa5fde99c02
URL:
https://github.com/llvm/llvm-project/commit/95a4d30b0d64c544106acf306c3d3fa5fde99c02
DIFF:
https://github.com/llvm/llvm-project/commit/95a4d30b0d64c544106acf306c3d3fa5fde99c02.diff
L
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/118515
>From 88df866f5d1cc7fef7bea0d938f9457a3969025b Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Tue, 3 Dec 2024 11:25:37 -0500
Subject: [PATCH] [AMDGPU] Use COV6 by default
---
clang/docs/ReleaseNotes.rst
@@ -34,7 +34,7 @@
static llvm::cl::opt DefaultAMDHSACodeObjectVersion(
"amdhsa-code-object-version", llvm::cl::Hidden,
-llvm::cl::init(llvm::AMDGPU::AMDHSA_COV5),
+llvm::cl::init(llvm::AMDGPU::AMDHSA_COV6),
shiltian wrote:
It does things. If we do
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/118515
>From af3d46f389a2b4e77f0d4681c1f62eca86c3140f Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Tue, 3 Dec 2024 11:25:37 -0500
Subject: [PATCH] [AMDGPU] Use COV6 by default
---
clang/docs/ReleaseNotes.rst
@@ -34,7 +34,7 @@
static llvm::cl::opt DefaultAMDHSACodeObjectVersion(
"amdhsa-code-object-version", llvm::cl::Hidden,
-llvm::cl::init(llvm::AMDGPU::AMDHSA_COV5),
+llvm::cl::init(llvm::AMDGPU::AMDHSA_COV6),
shiltian wrote:
> The .amdhsa_code_objec
@@ -34,7 +34,7 @@
static llvm::cl::opt DefaultAMDHSACodeObjectVersion(
"amdhsa-code-object-version", llvm::cl::Hidden,
-llvm::cl::init(llvm::AMDGPU::AMDHSA_COV5),
+llvm::cl::init(llvm::AMDGPU::AMDHSA_COV6),
shiltian wrote:
Not really. Nothing chan
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/118515
>From a0dfb34e2c0711826b5bbf5dc0ed15e87918fa27 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Tue, 3 Dec 2024 11:25:37 -0500
Subject: [PATCH] [AMDGPU] Use COV6 by default
---
clang/docs/ReleaseNotes.rst
shiltian wrote:
> Why change the clang default only, and not the backend?
Yeah, initially I thought that was dictated by the front end but forgot we
could invoke directly via `opt`, `llc`, etc. Done.
https://github.com/llvm/llvm-project/pull/118515
_
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/118515
>From 8ba940796d4092c225ce34ff883b80d36fee58fe Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Tue, 3 Dec 2024 11:25:37 -0500
Subject: [PATCH] [AMDGPU] Use COV6 by default
---
clang/docs/ReleaseNotes.rst
@@ -0,0 +1,7 @@
+; RUN: llc -mtriple=amdgcn-amd-amdhsa %s -o - | FileCheck %s
+
+; CHECK: .amdhsa_code_object_version 6
shiltian wrote:
We already have multiple tests that have explicit module flag and checks for
the match.
https://github.com/llvm/llvm-project/
https://github.com/shiltian closed
https://github.com/llvm/llvm-project/pull/118515
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