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@@ -0,0 +1,45 @@
+; RUN: split-file %s %t
shiltian wrote:
This is an interesting thing that I learned from this PR. :-)
https://github.com/l
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shiltian wrote:
@asb I did receive some emails initially but haven't gotten any lately. I
assumed that issue had been fixed, as it seemed like the driver was just
unconditionally adding `unknown`.
https://github.com/llvm/llvm-project/pull/122629
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shiltian wrote:
Why this lowering? We have a table right?
https://github.com/llvm/llvm-project/pull/133741
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https://github.com/llv
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@@ -0,0 +1,84 @@
+//===-- llvm/Target/TargetVerifier.h - LLVM IR Target Verifier --*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
@@ -0,0 +1,84 @@
+//===-- llvm/Target/TargetVerifier.h - LLVM IR Target Verifier --*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
@@ -481,6 +481,9 @@ static cl::opt HasClosedWorldAssumption(
cl::desc("Whether has closed-world assumption at link time"),
cl::init(false), cl::Hidden);
+static cl::opt VerifyTarget("verify-tgt",
shiltian wrote:
`verify-tgt` is too broad. I'd add an `
@@ -0,0 +1,84 @@
+//===-- llvm/Target/TargetVerifier.h - LLVM IR Target Verifier --*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
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@@ -683,6 +683,30 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned
BuiltinID,
return Builder.CreateInsertElement(I0, A, 1);
}
+ case AMDGPU::BI__builtin_amdgcn_image_load_2d_f32_i32: {
+llvm::Type *RetTy = llvm::Type::getFloatTy(Builder.getContext());
+
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shiltian wrote:
Hmm, in what cases `-nogpuinc` is added but we don't actually want it?
https://github.com/llvm/llvm-project/pull/140106
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@@ -683,6 +683,30 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned
BuiltinID,
return Builder.CreateInsertElement(I0, A, 1);
}
+ case AMDGPU::BI__builtin_amdgcn_image_load_2d_f32_i32: {
+llvm::Type *RetTy = llvm::Type::getFloatTy(Builder.getContext());
+
@@ -0,0 +1,31 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 5
+// RUN: %clang_cc1 -triple amdgcn-unknown-unknown %s -emit-llvm -o - |
FileCheck %s
shiltian wrote:
use right triple `amdgcn-amd-amdhsa` pls
@@ -683,6 +683,30 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned
BuiltinID,
return Builder.CreateInsertElement(I0, A, 1);
}
+ case AMDGPU::BI__builtin_amdgcn_image_load_2d_f32_i32: {
+llvm::Type *RetTy = llvm::Type::getFloatTy(Builder.getContext());
@@ -635,5 +635,10 @@ TARGET_BUILTIN(__builtin_amdgcn_bitop3_b16, "IUi",
"nc", "bitop3-insts")
TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_bf16_f32, "V2yV2yfUiIb", "nc",
"f32-to-f16bf16-cvt-sr-insts")
TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_f16_f32, "V2hV2hfUiIb", "nc",
"f32-to-
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@@ -14924,8 +14924,25 @@ StmtResult
SemaOpenMP::ActOnOpenMPUnrollDirective(ArrayRef Clauses,
SourceLocation FactorLoc;
if (Expr *FactorVal = PartialClause->getFactor();
FactorVal && !FactorVal->containsErrors()) {
+if (!VerifyPositiveIntegerConstantInClause(Facto
@@ -14924,8 +14924,25 @@ StmtResult
SemaOpenMP::ActOnOpenMPUnrollDirective(ArrayRef Clauses,
SourceLocation FactorLoc;
if (Expr *FactorVal = PartialClause->getFactor();
FactorVal && !FactorVal->containsErrors()) {
+if (!VerifyPositiveIntegerConstantInClause(Facto
@@ -14924,8 +14924,25 @@ StmtResult
SemaOpenMP::ActOnOpenMPUnrollDirective(ArrayRef Clauses,
SourceLocation FactorLoc;
if (Expr *FactorVal = PartialClause->getFactor();
FactorVal && !FactorVal->containsErrors()) {
+if (!VerifyPositiveIntegerConstantInClause(Facto
shiltian wrote:
> comgr is the JIT compiler for HIP on ROCm. comgr uses -nogpuinc by default.
> However, some users of comgr need to override that so that comgr enables the
> wrapper headers. We cannot simply let comgr stop using -nogpuinc by default
> since it will break existing comgr users.
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@@ -11762,52 +11762,98 @@ bool
OpenMPAtomicCompareChecker::checkCondUpdateStmt(IfStmt *S,
X = BO->getLHS();
- auto *Cond = dyn_cast(S->getCond());
- if (!Cond) {
-ErrorInfo.Error = ErrorTy::NotABinaryOp;
-ErrorInfo.ErrorLoc = ErrorInfo.NoteLoc = S->getCond()->get
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@@ -11762,52 +11762,98 @@ bool
OpenMPAtomicCompareChecker::checkCondUpdateStmt(IfStmt *S,
X = BO->getLHS();
- auto *Cond = dyn_cast(S->getCond());
- if (!Cond) {
-ErrorInfo.Error = ErrorTy::NotABinaryOp;
-ErrorInfo.ErrorLoc = ErrorInfo.NoteLoc = S->getCond()->get
@@ -11762,52 +11762,98 @@ bool
OpenMPAtomicCompareChecker::checkCondUpdateStmt(IfStmt *S,
X = BO->getLHS();
- auto *Cond = dyn_cast(S->getCond());
- if (!Cond) {
-ErrorInfo.Error = ErrorTy::NotABinaryOp;
-ErrorInfo.ErrorLoc = ErrorInfo.NoteLoc = S->getCond()->get
shiltian wrote:
Can you also remove all `t`? They don't seem to be necessary here.
https://github.com/llvm/llvm-project/pull/138141
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LGTM as long as it builds successfully. I tried something similar in a few
files before, but it ended up breaking the build, so I gave up. :-)
https://github.com/llvm/llvm-project/pull/142296
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LGTM as long as it doesn't break the build.
https://github.com/llvm/llvm-project/pull/142295
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@@ -0,0 +1,170 @@
+//===-- AMDGPUTargetVerifier.cpp - AMDGPU ---*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,170 @@
+//===-- AMDGPUTargetVerifier.cpp - AMDGPU ---*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
shiltian wrote:
Why did we have `t` in some of the builtins in the first place…
https://github.com/llvm/llvm-project/pull/138141
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CI will tell us whether this is broken or not. :-)
https://github.com/llvm/llvm-project/pull/144285
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shiltian wrote:
> Bit of a hack it seems
It is a hack (or workaround). The correct approach would be either to redesign
the lowering of LDS, or create another flavor of ThinLTO. Neither of it can be
done in a reasonably short amount of time.
https://github.com/llvm/llvm-project/pull/144914
__
shiltian wrote:
* **#144914** https://app.graphite.dev/github/pr/llvm/llvm-project/144914?utm_source=stack-comment-icon";
target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite"
width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/144
https://github.com/shiltian created
https://github.com/llvm/llvm-project/pull/144914
On AMDGPU, we need an extra argument `-avail-extern-gv-in-addrspace-to-local=3`
to privatize LDS global variables when ThinLTO is enabled.
>From bf7b936421379ae7e043360c6515136660e2e550 Mon Sep 17 00:00:00 2001
shiltian wrote:
No test is needed?
https://github.com/llvm/llvm-project/pull/144570
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@@ -417,3 +417,15 @@ void HIPAMDToolChain::checkTargetID(
getDriver().Diag(clang::diag::err_drv_bad_target_id)
<< *PTID.OptionalTargetID;
}
+
+SPIRVAMDToolChain::SPIRVAMDToolChain(const Driver &D,
+ const llvm::Triple &Triple,
+
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@@ -683,6 +683,206 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned
BuiltinID,
return Builder.CreateInsertElement(I0, A, 1);
}
+ case AMDGPU::BI__builtin_amdgcn_image_load_1d_v4f32_i32:
+ case AMDGPU::BI__builtin_amdgcn_image_load_1darray_v4f32_i32:
+ case A
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@@ -5500,7 +5504,34 @@ struct AAAlignCallSiteReturned final
using Base = AACalleeToCallSite;
AAAlignCallSiteReturned(const IRPosition &IRP, Attributor &A)
: Base(IRP, A) {}
+ ChangeStatus updateImpl(Attributor &A) override {
+SmallVector Values;
+const auto &
@@ -1381,7 +1399,7 @@ static bool runImpl(Module &M, AnalysisGetter &AG,
TargetMachine &TM,
&AAAMDMaxNumWorkgroups::ID, &AAAMDWavesPerEU::ID, &AAAMDGPUNoAGPR::ID,
&AACallEdges::ID, &AAPointerInfo::ID, &AAPotentialConstantValues::ID,
&AAUnderlyingObjects::I
@@ -5500,7 +5504,34 @@ struct AAAlignCallSiteReturned final
using Base = AACalleeToCallSite;
AAAlignCallSiteReturned(const IRPosition &IRP, Attributor &A)
: Base(IRP, A) {}
+ ChangeStatus updateImpl(Attributor &A) override {
+SmallVector Values;
+const auto &
@@ -5500,7 +5504,34 @@ struct AAAlignCallSiteReturned final
using Base = AACalleeToCallSite;
AAAlignCallSiteReturned(const IRPosition &IRP, Attributor &A)
: Base(IRP, A) {}
+ ChangeStatus updateImpl(Attributor &A) override {
+SmallVector Values;
+const auto &
@@ -5500,7 +5504,34 @@ struct AAAlignCallSiteReturned final
using Base = AACalleeToCallSite;
AAAlignCallSiteReturned(const IRPosition &IRP, Attributor &A)
: Base(IRP, A) {}
+ ChangeStatus updateImpl(Attributor &A) override {
+SmallVector Values;
+const auto &
shiltian wrote:
> I assume AMDGPU does not support unaligned loads
We do support unaligned access IIUC, and it is actually required by HSA ABI. CC
@arsenm
https://github.com/llvm/llvm-project/pull/133301
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Miguel =?utf-8?q?C=C3=A1rdenas?= ,
Miguel =?utf-8?q?C=C3=A1rdenas?=
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@@ -83,6 +83,38 @@ bool SemaAMDGPU::CheckAMDGCNBuiltinFunctionCall(unsigned
BuiltinID,
case AMDGPU::BI__builtin_amdgcn_update_dpp: {
return checkMovDPPFunctionCall(TheCall, 6, 2);
}
+ case AMDGPU::BI__builtin_amdgcn_image_load_1d_v4f32_i32:
+ case AMDGPU::BI__builtin
@@ -683,6 +683,206 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned
BuiltinID,
return Builder.CreateInsertElement(I0, A, 1);
}
+ case AMDGPU::BI__builtin_amdgcn_image_load_1d_v4f32_i32:
+ case AMDGPU::BI__builtin_amdgcn_image_load_1darray_v4f32_i32:
+ case A
@@ -128,6 +160,16 @@ bool SemaAMDGPU::CheckAMDGCNBuiltinFunctionCall(unsigned
BuiltinID,
return false;
}
+bool SemaAMDGPU::checkImageImmArgFunctionCall(CallExpr *TheCall,
+ unsigned ArgCount) {
+ llvm::APSInt Result;
+ if (!(Se
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@@ -1044,82 +1040,78 @@ void
Driver::CreateOffloadingDeviceToolChains(Compilation &C,
<< OpenMPTargets->getAsString(C.getInputArgs());
return;
}
+
+ // Make sure these show up in a deterministic order.
+ std::multiset OpenMPTriples;
f
@@ -1044,82 +1040,78 @@ void
Driver::CreateOffloadingDeviceToolChains(Compilation &C,
<< OpenMPTargets->getAsString(C.getInputArgs());
return;
}
+
+ // Make sure these show up in a deterministic order.
+ std::multiset OpenMPTriples;
f
@@ -1044,82 +1040,78 @@ void
Driver::CreateOffloadingDeviceToolChains(Compilation &C,
<< OpenMPTargets->getAsString(C.getInputArgs());
return;
}
+
+ // Make sure these show up in a deterministic order.
+ std::multiset OpenMPTriples;
f
@@ -1044,82 +1040,78 @@ void
Driver::CreateOffloadingDeviceToolChains(Compilation &C,
<< OpenMPTargets->getAsString(C.getInputArgs());
return;
}
+
+ // Make sure these show up in a deterministic order.
+ std::multiset OpenMPTriples;
f
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https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/143278
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https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/146636
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shiltian wrote:
### Merge activity
* **Jun 25, 8:56 PM UTC**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/145747).
https://github.com/llvm/llvm-project/pull/145747
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@@ -5501,7 +5505,32 @@ struct AAAlignCallSiteReturned final
using Base = AACalleeToCallSite;
AAAlignCallSiteReturned(const IRPosition &IRP, Attributor &A)
: Base(IRP, A) {}
+ ChangeStatus updateImpl(Attributor &A) override {
+SmallVector Values;
+SmallVector
@@ -1432,6 +1442,26 @@ static bool runImpl(Module &M, AnalysisGetter &AG,
TargetMachine &TM,
} else if (auto *CmpX = dyn_cast(&I)) {
A.getOrCreateAAFor(
IRPosition::value(*CmpX->getPointerOperand()));
+ } else if (auto *II = dyn_cast(&I)) {
+
https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/146707
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https://github.com/llvm/llvm-project/pull/146706
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https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/146409
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https://github.com/shiltian edited
https://github.com/llvm/llvm-project/pull/146594
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shiltian wrote:
I see. That makes sense. Worth a release note item.
https://github.com/llvm/llvm-project/pull/146594
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https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/146547
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shiltian wrote:
Why not stick with `--offload-arch` for generic use? I'm not really sure about
the motivation.
https://github.com/llvm/llvm-project/pull/146594
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@@ -635,5 +635,66 @@ TARGET_BUILTIN(__builtin_amdgcn_bitop3_b16, "IUi",
"nc", "bitop3-insts")
TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_bf16_f32, "V2yV2yfUiIb", "nc",
"f32-to-f16bf16-cvt-sr-insts")
TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_f16_f32, "V2hV2hfUiIb", "nc",
"f32-to-
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