@@ -50,20 +50,30 @@ using TypeSpec = std::string;
namespace {
class SVEType {
- bool Float, Signed, Immediate, Void, Constant, Pointer, BFloat, MFloat;
- bool DefaultType, IsScalable, Predicate, PredicatePattern, PrefetchOp,
- Svcount;
+
+ enum TypeKind {
+Void,
+
sdesmalen-arm wrote:
It would be good to land this and get this cherry-picked onto the release/19.x
branch. Any objection in merging this @wwwatermiao?
https://github.com/llvm/llvm-project/pull/118109
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@@ -1328,4 +1328,57 @@ void SemaARM::handleInterruptAttr(Decl *D, const
ParsedAttr &AL) {
ARMInterruptAttr(getASTContext(), AL, Kind));
}
+// Check if the function definition uses any AArch64 SME features without
+// having the '+sme' feature enabled and warn
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -std=c++23 -fsyntax-only
-verify %s
sdesmalen-arm wrote:
What about this change requires c++23?
https://github.com/llv
@@ -48,3 +48,9 @@ void streaming_compatible_def2(void (*streaming_fn_ptr)(void)
__arm_streaming,
// Also test when call-site is not a function.
int streaming_decl_ret_int() __arm_streaming;
int x = streaming_decl_ret_int(); // expected-error {{call to a streaming
function req
https://github.com/sdesmalen-arm created
https://github.com/llvm/llvm-project/pull/121788
This adds support for parsing the attribute and codegen to map it to
"aarch64_za_state_agnostic" LLVM IR attribute.
This attribute is described in the Arm C Language Extensions (ACLE) document:
https:/
@@ -11335,6 +11335,13 @@ Value
*CodeGenFunction::EmitAArch64SMEBuiltinExpr(unsigned BuiltinID,
unsigned SMEAttrs = FPT->getAArch64SMEAttributes();
if (!(SMEAttrs & FunctionType::SME_PStateSMCompatibleMask)) {
bool IsStreaming = SMEAttrs & FunctionType::SME_
https://github.com/sdesmalen-arm updated
https://github.com/llvm/llvm-project/pull/121788
>From 159bc2ccdab5457d997c9fc8ed679e4607db0b79 Mon Sep 17 00:00:00 2001
From: Sander de Smalen
Date: Mon, 9 Sep 2024 15:20:26 +0100
Subject: [PATCH 1/2] [AArch64][Clang] Add support for
__arm_agnostic("sm
@@ -7559,6 +7559,26 @@ The attributes ``__arm_in(S)``, ``__arm_out(S)``,
``__arm_inout(S)`` and
}];
}
+def ArmAgnosticDocs : Documentation {
+ let Category = DocCatArmSmeAttributes;
+ let Content = [{
+The ``__arm_agnostic`` keyword applies to prototyped function types an
https://github.com/sdesmalen-arm approved this pull request.
LGTM as well. +1 on @MacDue's suggestion to add an extra test to
sme-inline-callees-streaming-attrs.c as well.
https://github.com/llvm/llvm-project/pull/121338
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@@ -61,13 +61,13 @@ unsigned AArch64::getFMVPriority(ArrayRef
Features) {
return Priority + MaxFMVPriority * NumFeatures;
}
-uint64_t AArch64::getCpuSupportsMask(ArrayRef FeatureStrs) {
- uint64_t FeaturesMask = 0;
- for (const StringRef &FeatureStr : FeatureStrs) {
-
@@ -349,6 +349,14 @@ void AArch64::ExtensionSet::reconstructFromParsedFeatures(
}
}
+uint64_t AArch64::ExtensionSet::toCpuSupportsMask() const {
sdesmalen-arm wrote:
I guess you could always move the functionality back into a separate function
if future ch
https://github.com/sdesmalen-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/119231
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@@ -61,13 +61,13 @@ unsigned AArch64::getFMVPriority(ArrayRef
Features) {
return Priority + MaxFMVPriority * NumFeatures;
}
-uint64_t AArch64::getCpuSupportsMask(ArrayRef FeatureStrs) {
- uint64_t FeaturesMask = 0;
- for (const StringRef &FeatureStr : FeatureStrs) {
-
@@ -349,6 +349,14 @@ void AArch64::ExtensionSet::reconstructFromParsedFeatures(
}
}
+uint64_t AArch64::ExtensionSet::toCpuSupportsMask() const {
+ uint64_t FeaturesMask = 0;
+ for (const auto &I : getFMVInfo())
sdesmalen-arm wrote:
nit: This shouldn't be
@@ -61,13 +61,13 @@ unsigned AArch64::getFMVPriority(ArrayRef
Features) {
return Priority + MaxFMVPriority * NumFeatures;
}
-uint64_t AArch64::getCpuSupportsMask(ArrayRef FeatureStrs) {
- uint64_t FeaturesMask = 0;
- for (const StringRef &FeatureStr : FeatureStrs) {
-
@@ -349,6 +349,14 @@ void AArch64::ExtensionSet::reconstructFromParsedFeatures(
}
}
+uint64_t AArch64::ExtensionSet::toCpuSupportsMask() const {
sdesmalen-arm wrote:
This function only has one use, perhaps just merge it into `getCpuSupportsMask`?
https://g
@@ -27292,6 +27294,13 @@ void AArch64TargetLowering::ReplaceNodeResults(
N->getOperand(1), N->getOperand(2));
Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, V));
return;
+}
+ case Intrinsic::aarch64_sme_in_streaming_mode: {
@@ -1636,12 +1636,8 @@ void SVEEmitter::createSMEHeader(raw_ostream &OS) {
OS << " return x0 & (1ULL << 63);\n";
OS << "}\n\n";
- OS << "__ai bool __arm_in_streaming_mode(void) __arm_streaming_compatible "
-"{\n";
- OS << " uint64_t x0, x1;\n";
- OS << " __bu
@@ -0,0 +1,44 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -verify-machineinstrs < %s |
FileCheck %s
+
+
+define i1 @streaming_mode_st_compatible() #0 {
+; CHECK-LABEL: streaming_mode_st_compa
@@ -8,32 +8,26 @@
// CHECK-LABEL: @test_in_streaming_mode(
// CHECK-NEXT: entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call aarch64_sme_preservemost_from_x2 {
i64, i64 } @__arm_sme_state() #[[ATTR3:[0-9]+]]
-// CHECK-NEXT:[[TMP1:%.*]] = extractvalue { i64, i64 } [[TMP0]
@@ -0,0 +1,44 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -verify-machineinstrs < %s |
FileCheck %s
+
+
+define i1 @streaming_mode_st_compatible() #0 {
sdesmalen-arm wrote:
https://github.com/sdesmalen-arm commented:
Could you add some rationale for adding the intrinsic to the commit message?
https://github.com/llvm/llvm-project/pull/120265
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@@ -27293,6 +27295,15 @@ void AArch64TargetLowering::ReplaceNodeResults(
Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, V));
return;
}
+case Intrinsic::aarch64_sme_in_streaming_mode: {
+ auto DL = SDLoc(N);
+ SDValue Chain = DAG.getEntryNode(
https://github.com/sdesmalen-arm edited
https://github.com/llvm/llvm-project/pull/120265
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@@ -27293,6 +27295,15 @@ void AArch64TargetLowering::ReplaceNodeResults(
Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, V));
return;
}
+case Intrinsic::aarch64_sme_in_streaming_mode: {
+ auto DL = SDLoc(N);
sdesmalen-arm wrote:
`
@@ -11285,6 +11285,21 @@ Value
*CodeGenFunction::EmitAArch64SMEBuiltinExpr(unsigned BuiltinID,
if (Builtin->LLVMIntrinsic == 0)
return nullptr;
+ if (BuiltinID == SME::BI__builtin_sme___arm_in_streaming_mode) {
+// If we already know the streaming mode, don't bothe
@@ -11285,6 +11285,21 @@ Value
*CodeGenFunction::EmitAArch64SMEBuiltinExpr(unsigned BuiltinID,
if (Builtin->LLVMIntrinsic == 0)
return nullptr;
+ if (BuiltinID == SME::BI__builtin_sme___arm_in_streaming_mode) {
+// If we already know the streaming mode, don't bothe
@@ -11285,6 +11285,21 @@ Value
*CodeGenFunction::EmitAArch64SMEBuiltinExpr(unsigned BuiltinID,
if (Builtin->LLVMIntrinsic == 0)
return nullptr;
+ if (BuiltinID == SME::BI__builtin_sme___arm_in_streaming_mode) {
+// If we already know the streaming mode, don't bothe
https://github.com/sdesmalen-arm edited
https://github.com/llvm/llvm-project/pull/120265
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https://github.com/sdesmalen-arm approved this pull request.
LGTM with nits addressed
https://github.com/llvm/llvm-project/pull/120265
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@@ -1143,30 +1146,62 @@ void AArch64TargetCodeGenInfo::checkFunctionABI(
}
}
-void AArch64TargetCodeGenInfo::checkFunctionCallABIStreaming(
-CodeGenModule &CGM, SourceLocation CallLoc, const FunctionDecl *Caller,
-const FunctionDecl *Callee) const {
- if (!Caller ||
@@ -1143,30 +1146,62 @@ void AArch64TargetCodeGenInfo::checkFunctionABI(
}
}
-void AArch64TargetCodeGenInfo::checkFunctionCallABIStreaming(
-CodeGenModule &CGM, SourceLocation CallLoc, const FunctionDecl *Caller,
-const FunctionDecl *Callee) const {
- if (!Caller ||
https://github.com/sdesmalen-arm commented:
Thanks for including the `clang::always_inline` statement attribute as well.
https://github.com/llvm/llvm-project/pull/116391
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@@ -0,0 +1,72 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -emit-llvm -target-feature
+sme %s -o - | FileCheck %s
sdesmalen-arm wrote:
nit: Given that the tests are otherwise identical, could you merge these with
`sme-flatten-streaming-attrs.c` and def
sdesmalen-arm wrote:
@efriedma-quic a motivating example is https://godbolt.org/z/aW9zTrdf9
With @NickGuy-Arm's patch, this would compile to:
```
_Z1xv:
rdvlx0, #1
ret
_Z1yv:
rdsvl x0, #1
ret
```
https://github.com/llvm/llvm-project/pull/121917
___
@@ -1060,7 +1060,7 @@ let SVETargetGuard = "sve,bf16", SMETargetGuard =
"sme,bf16" in {
def SVEXT: SInst<"svext[_{d}]", "dddi", "csilUcUsUiUlhfd",
MergeNone, "aarch64_sve_ext", [VerifyRuntimeMode], [ImmCheck<2,
ImmCheckExtract, 1>]>;
defm SVLASTA : SVEPerm<"
https://github.com/sdesmalen-arm commented:
@RKSimon do you know if there is a reason CodeGen AA is not enabled for x86?
I'd otherwise be happy to approve this patch, lowering to the intrinsic seems
like the right thing to do.
https://github.com/llvm/llvm-project/pull/121763
__
@@ -4568,9 +4568,23 @@ buildCapturedStmtCaptureList(Sema &S,
CapturedRegionScopeInfo *RSI,
return false;
}
+static bool
+isOpenMPCapturedRegionInArmStreamingFunction(Sema const &S,
+ CapturedRegionKind Kind) {
+ if (!S.getLangOpt
@@ -708,7 +708,7 @@ AArch64TargetInfo::getVScaleRange(const LangOptions
&LangOpts) const {
return std::pair(
LangOpts.VScaleMin ? LangOpts.VScaleMin : 1, LangOpts.VScaleMax);
- if (hasFeature("sve"))
+ if (hasFeature("sve") || hasFeature("sme"))
https://github.com/sdesmalen-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/124590
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@@ -0,0 +1,47 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve \
sdesmalen-arm wrote:
Maybe it makes more sense to move the existing
`aarch64-incompat-sm-builtin-calls.c` to
`aarch64-incompat-sm-builtin-calls.cpp` (there is nothing C-
https://github.com/sdesmalen-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/124750
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https://github.com/sdesmalen-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/124968
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https://github.com/sdesmalen-arm updated
https://github.com/llvm/llvm-project/pull/121788
>From 4e2166f1c19246e3fb5074da466d151070b5606c Mon Sep 17 00:00:00 2001
From: Sander de Smalen
Date: Mon, 9 Sep 2024 15:20:26 +0100
Subject: [PATCH 1/4] [AArch64][Clang] Add support for
__arm_agnostic("sm
Author: Sander de Smalen
Date: 2025-01-12T22:09:26Z
New Revision: 08028d68a90bbc47464562a745e33fa10256a7d3
URL:
https://github.com/llvm/llvm-project/commit/08028d68a90bbc47464562a745e33fa10256a7d3
DIFF:
https://github.com/llvm/llvm-project/commit/08028d68a90bbc47464562a745e33fa10256a7d3.diff
L
https://github.com/sdesmalen-arm closed
https://github.com/llvm/llvm-project/pull/121788
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https://github.com/sdesmalen-arm edited
https://github.com/llvm/llvm-project/pull/122899
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https://github.com/sdesmalen-arm created
https://github.com/llvm/llvm-project/pull/122899
None
>From e5c0686058f5dac17b02547e283df9bd20d24cae Mon Sep 17 00:00:00 2001
From: Sander de Smalen
Date: Tue, 14 Jan 2025 13:23:54 +
Subject: [PATCH] [Clang] Add AArch64 SME changes to the release no
https://github.com/sdesmalen-arm updated
https://github.com/llvm/llvm-project/pull/122899
>From 0218a54ea332dc77a95e887fc5c83ffe9b47d0b8 Mon Sep 17 00:00:00 2001
From: Sander de Smalen
Date: Tue, 14 Jan 2025 13:23:54 +
Subject: [PATCH] [Clang] Add AArch64 SME changes to the release notes
-
sdesmalen-arm wrote:
The assumption cache mechanism is used by a number of passes, such as [partial]
inlining, function specialization and IPSCCP (interprocedural sparse
conditional constant propagation).
The idea behind doing this is to let optimizations iteratively apply knowledge
about the
@@ -1328,4 +1328,57 @@ void SemaARM::handleInterruptAttr(Decl *D, const
ParsedAttr &AL) {
ARMInterruptAttr(getASTContext(), AL, Kind));
}
+// Check if the function definition uses any AArch64 SME features without
+// having the '+sme' feature enabled and warn
https://github.com/sdesmalen-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/121777
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>From 159bc2ccdab5457d997c9fc8ed679e4607db0b79 Mon Sep 17 00:00:00 2001
From: Sander de Smalen
Date: Mon, 9 Sep 2024 15:20:26 +0100
Subject: [PATCH 1/3] [AArch64][Clang] Add support for
__arm_agnostic("sm
@@ -1275,6 +1279,31 @@ bool
AArch64TargetCodeGenInfo::wouldInliningViolateFunctionCallABI(
GetArmSMEInlinability(Caller, Callee) != ArmSMEInlinability::Ok;
}
+void AArch64TargetCodeGenInfo::emitFunctionCallProlog(
+CGBuilderTy &Builder, const FunctionDecl *Caller
https://github.com/sdesmalen-arm edited
https://github.com/llvm/llvm-project/pull/121917
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@@ -1275,6 +1279,31 @@ bool
AArch64TargetCodeGenInfo::wouldInliningViolateFunctionCallABI(
GetArmSMEInlinability(Caller, Callee) != ArmSMEInlinability::Ok;
}
+void AArch64TargetCodeGenInfo::emitFunctionCallProlog(
+CGBuilderTy &Builder, const FunctionDecl *Caller
@@ -1275,6 +1279,31 @@ bool
AArch64TargetCodeGenInfo::wouldInliningViolateFunctionCallABI(
GetArmSMEInlinability(Caller, Callee) != ArmSMEInlinability::Ok;
}
+void AArch64TargetCodeGenInfo::emitFunctionCallProlog(
+CGBuilderTy &Builder, const FunctionDecl *Caller
https://github.com/sdesmalen-arm commented:
@NickGuy-Arm this PR is missing some test-coverage.
@efriedma-quic do you have any thoughts on emitting the llvm.assume as a
prologue to the actual call? I guess the alternative would be to analyse the
function to see if there's any calls to streamin
@@ -21962,6 +21962,35 @@ SDValue tryLowerPartialReductionToWideAdd(SDNode *N,
return DAG.getNode(TopOpcode, DL, AccVT, BottomNode, ExtOp);
}
+static SDValue foldRevInvolution(SDNode *N) {
+ SDValue InnerRev = N->getOperand(1);
+ if (!InnerRev.hasOneUse())
+return SDVal
@@ -21962,6 +21962,35 @@ SDValue tryLowerPartialReductionToWideAdd(SDNode *N,
return DAG.getNode(TopOpcode, DL, AccVT, BottomNode, ExtOp);
}
+static SDValue foldRevInvolution(SDNode *N) {
+ SDValue InnerRev = N->getOperand(1);
+ if (!InnerRev.hasOneUse())
+return SDVal
@@ -22270,6 +22299,15 @@ static SDValue performIntrinsicCombine(SDNode *N,
return tryConvertSVEWideCompare(N, ISD::SETULT, DCI, DAG);
case Intrinsic::aarch64_sve_cmpls_wide:
return tryConvertSVEWideCompare(N, ISD::SETULE, DCI, DAG);
+ case Intrinsic::aarch64_sve_rev:
https://github.com/sdesmalen-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/127065
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@@ -1990,21 +2028,56 @@ static bool canConvertValue(const DataLayout &DL, Type
*OldTy, Type *NewTy) {
static Value *convertValue(const DataLayout &DL, IRBuilderTy &IRB, Value *V,
Type *NewTy) {
Type *OldTy = V->getType();
- assert(canConvertValue(
@@ -554,6 +554,22 @@ class VectorType : public Type {
return VectorType::get(VTy->getElementType(), EltCnt * 2);
}
+ /// This static method returns a VectorType with the same size-in-bits as
+ /// SizeTy but with an element type that matches the scalar type of EltTy.
+
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