Author: Saiyedul Islam
Date: 2020-04-27T09:39:03+05:30
New Revision: 06bdffb2bb45d8666ec86782d21214ef545a71fd
URL:
https://github.com/llvm/llvm-project/commit/06bdffb2bb45d8666ec86782d21214ef545a71fd
DIFF:
https://github.com/llvm/llvm-project/commit/06bdffb2bb45d8666ec86782d21214ef545a71fd.diff
@@ -26,28 +26,31 @@ using namespace llvm;
#define DEBUG_TYPE "amdgpu-emit-printf"
-static Value *fitArgInto64Bits(IRBuilder<> &Builder, Value *Arg) {
+static Value *fitArgInto64Bits(IRBuilder<> &Builder, Value *Arg,
+ bool IsBuffered) {
+ const
@@ -406,5 +410,9 @@ TARGET_BUILTIN(__builtin_amdgcn_cvt_pk_fp8_f32, "iffiIb",
"nc", "fp8-insts")
TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_bf8_f32, "ifiiIi", "nc", "fp8-insts")
TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_fp8_f32, "ifiiIi", "nc", "fp8-insts")
+// OpenCL
+LANGBUILTIN(p
@@ -4742,6 +4742,16 @@ void Clang::ConstructJob(Compilation &C, const JobAction
&JA,
Args.ClaimAllArgs(options::OPT_gen_cdb_fragment_path);
}
+ if (TC.getTriple().isAMDGPU() && types::isOpenCL(Input.getType())) {
+if (Args.getLastArg(options::OPT_mprintf_kind_EQ))
@@ -26,28 +26,31 @@ using namespace llvm;
#define DEBUG_TYPE "amdgpu-emit-printf"
-static Value *fitArgInto64Bits(IRBuilder<> &Builder, Value *Arg) {
+static Value *fitArgInto64Bits(IRBuilder<> &Builder, Value *Arg,
+ bool IsBuffered) {
+ const
@@ -170,20 +173,49 @@ static Value *appendString(IRBuilder<> &Builder, Value
*Desc, Value *Arg,
return callAppendStringN(Builder, Desc, Arg, Length, IsLast);
}
+static Value *appendVectorArg(IRBuilder<> &Builder, Value *Desc, Value *Arg,
+ bool
@@ -170,20 +173,49 @@ static Value *appendString(IRBuilder<> &Builder, Value
*Desc, Value *Arg,
return callAppendStringN(Builder, Desc, Arg, Length, IsLast);
}
+static Value *appendVectorArg(IRBuilder<> &Builder, Value *Desc, Value *Arg,
+ bool
@@ -194,6 +226,8 @@ static void locateCStrings(SparseBitVector<8> &BV,
StringRef Str) {
SpecPos += 2;
continue;
}
+if (Str.find_first_of("v", SpecPos) != StringRef::npos)
ssahasra wrote:
I don't think this will work as expected. It can cle
@@ -170,20 +173,49 @@ static Value *appendString(IRBuilder<> &Builder, Value
*Desc, Value *Arg,
return callAppendStringN(Builder, Desc, Arg, Length, IsLast);
}
+static Value *appendVectorArg(IRBuilder<> &Builder, Value *Desc, Value *Arg,
+ bool
@@ -1,12 +1,68 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// RUN: %clang_cc1 -cl-std=CL1.2 -triple amdgcn-amd-amdhsa
-disable-llvm-passes -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -cl-std=CL1.2 -triple amdgcn-amd-amdhsa
-mprint
@@ -406,5 +410,9 @@ TARGET_BUILTIN(__builtin_amdgcn_cvt_pk_fp8_f32, "iffiIb",
"nc", "fp8-insts")
TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_bf8_f32, "ifiiIi", "nc", "fp8-insts")
TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_fp8_f32, "ifiiIi", "nc", "fp8-insts")
+// OpenCL
+LANGBUILTIN(p
ssahasra wrote:
> ping
Some comments still need to be addressed.
https://github.com/llvm/llvm-project/pull/72556
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@@ -406,5 +410,9 @@ TARGET_BUILTIN(__builtin_amdgcn_cvt_pk_fp8_f32, "iffiIb",
"nc", "fp8-insts")
TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_bf8_f32, "ifiiIi", "nc", "fp8-insts")
TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_fp8_f32, "ifiiIi", "nc", "fp8-insts")
+// OpenCL
+LANGBUILTIN(p
@@ -198,6 +229,10 @@ static void locateCStrings(SparseBitVector<8> &BV,
StringRef Str) {
if (SpecEnd == StringRef::npos)
return;
auto Spec = Str.slice(SpecPos, SpecEnd + 1);
+
+if ((Spec.find_first_of("v")) != StringRef::npos)
ssahasra wrote:
@@ -26,28 +26,31 @@ using namespace llvm;
#define DEBUG_TYPE "amdgpu-emit-printf"
-static Value *fitArgInto64Bits(IRBuilder<> &Builder, Value *Arg) {
+static Value *fitArgInto64Bits(IRBuilder<> &Builder, Value *Arg,
+ bool IsBuffered) {
+ const
@@ -1,12 +1,68 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// RUN: %clang_cc1 -cl-std=CL1.2 -triple amdgcn-amd-amdhsa
-disable-llvm-passes -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -cl-std=CL1.2 -triple amdgcn-amd-amdhsa
-mprint
https://github.com/ssahasra created
https://github.com/llvm/llvm-project/pull/73920
The Clang declaration of the wave-64 builtin uses "UL" as the return type,
which is interpreted as a 32-bit unsigned integer on Windows. This emits an
incorrect LLVM declaration with i32 return type instead of
https://github.com/ssahasra updated
https://github.com/llvm/llvm-project/pull/73920
>From 6b87550b48f5fae5c34304a14a302d37e81a Mon Sep 17 00:00:00 2001
From: Sameer Sahasrabuddhe
Date: Fri, 1 Dec 2023 11:49:02 +0530
Subject: [PATCH] [clang][AMDGPU] precommit test for ballot on Windows
The
https://github.com/ssahasra updated
https://github.com/llvm/llvm-project/pull/73920
>From 8ecb6310a4912de50628cf3db5ff8488fa919bb1 Mon Sep 17 00:00:00 2001
From: Sameer Sahasrabuddhe
Date: Fri, 1 Dec 2023 14:24:30 +0530
Subject: [PATCH] [clang][AMDGPU] precommit test for ballot on Windows
The
https://github.com/ssahasra updated
https://github.com/llvm/llvm-project/pull/73906
>From 8ecb6310a4912de50628cf3db5ff8488fa919bb1 Mon Sep 17 00:00:00 2001
From: Sameer Sahasrabuddhe
Date: Fri, 1 Dec 2023 14:24:30 +0530
Subject: [PATCH 1/2] [clang][AMDGPU] precommit test for ballot on Windows
@@ -150,8 +150,8 @@ BUILTIN(__builtin_amdgcn_mqsad_u32_u8, "V4UiWUiUiV4Ui",
"nc")
// Ballot builtins.
//===--===//
-TARGET_BUILTIN(__builtin_amdgcn_ballot_w32, "Uib", "nc", "wavefrontsize32")
-TARGET_BUILTIN
@@ -0,0 +1,15 @@
+// REQUIRES: amdgpu-registered-target
+// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -target-cpu gfx900 -x hip
-emit-llvm -fcuda-is-device -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -target-cpu gfx900 -x hip -S
-fcuda-is-device -o - %s
@@ -0,0 +1,27 @@
+// REQUIRES: amdgpu-registered-target
+// XFAIL: *
+// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -aux-triple
x86_64-pc-windows-msvc -target-cpu gfx900 -x hip -emit-llvm -fcuda-is-device -o
- %s | FileCheck %s
+// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -aux-t
@@ -406,5 +410,9 @@ TARGET_BUILTIN(__builtin_amdgcn_cvt_pk_fp8_f32, "iffiIb",
"nc", "fp8-insts")
TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_bf8_f32, "ifiiIi", "nc", "fp8-insts")
TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_fp8_f32, "ifiiIi", "nc", "fp8-insts")
+// OpenCL
+LANGBUILTIN(p
https://github.com/ssahasra closed
https://github.com/llvm/llvm-project/pull/73920
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https://github.com/ssahasra updated
https://github.com/llvm/llvm-project/pull/73906
>From 8ecb6310a4912de50628cf3db5ff8488fa919bb1 Mon Sep 17 00:00:00 2001
From: Sameer Sahasrabuddhe
Date: Fri, 1 Dec 2023 14:24:30 +0530
Subject: [PATCH 1/2] [clang][AMDGPU] precommit test for ballot on Windows
https://github.com/ssahasra closed
https://github.com/llvm/llvm-project/pull/73906
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@@ -170,20 +173,49 @@ static Value *appendString(IRBuilder<> &Builder, Value
*Desc, Value *Arg,
return callAppendStringN(Builder, Desc, Arg, Length, IsLast);
}
+static Value *appendVectorArg(IRBuilder<> &Builder, Value *Desc, Value *Arg,
+ bool
@@ -4742,6 +4742,16 @@ void Clang::ConstructJob(Compilation &C, const JobAction
&JA,
Args.ClaimAllArgs(options::OPT_gen_cdb_fragment_path);
}
+ if (TC.getTriple().isAMDGPU() && types::isOpenCL(Input.getType())) {
+if (Args.getLastArg(options::OPT_mprintf_kind_EQ))
@@ -4742,6 +4742,16 @@ void Clang::ConstructJob(Compilation &C, const JobAction
&JA,
Args.ClaimAllArgs(options::OPT_gen_cdb_fragment_path);
}
+ if (TC.getTriple().isAMDGPU() && types::isOpenCL(Input.getType())) {
+if (Args.getLastArg(options::OPT_mprintf_kind_EQ))
Author: Sameer Sahasrabuddhe
Date: 2022-02-11T22:51:56+05:30
New Revision: d8f99bb6e0641474b6bc1728295b40a8fa279f9a
URL:
https://github.com/llvm/llvm-project/commit/d8f99bb6e0641474b6bc1728295b40a8fa279f9a
DIFF:
https://github.com/llvm/llvm-project/commit/d8f99bb6e0641474b6bc1728295b40a8fa279f9
Nathan =?utf-8?q?Gauër?= ,
Nathan =?utf-8?q?Gauër?= ,
Nathan =?utf-8?q?Gauër?= ,
Nathan =?utf-8?q?Gauër?= ,
Nathan =?utf-8?q?Gauër?= ,
Nathan =?utf-8?q?Gauër?= ,
Nathan =?utf-8?q?Gauër?=
Message-ID:
In-Reply-To:
https://github.com/ssahasra commented:
LGTM, with a few nits.
For the record, I d
Nathan =?utf-8?q?Gauër?= ,
Nathan =?utf-8?q?Gauër?= ,
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Nathan =?utf-8?q?Gauër?= ,
Nathan =?utf-8?q?Gauër?=
Message-ID:
In-Reply-To:
@@ -1130,8 +1130,92 @@ struct BitTest {
static BitTest decode
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Nathan =?utf-8?q?Gau=C3=ABr?= ,
Nathan =?utf-8?q?Gau=C3=ABr?= ,
Nathan =?utf-8?q?Gau=C3=ABr?= ,
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Nathan =?utf-8?q?Gau=C3=ABr?= ,
Nathan =?utf-8?q?Gau=C3=ABr?=
Message-ID:
In-Reply-To:
@@ -1130,8 +1130,92 @@ struct B
Nathan =?utf-8?q?Gauër?= ,
Nathan =?utf-8?q?Gauër?= ,
Nathan =?utf-8?q?Gauër?= ,
Nathan =?utf-8?q?Gauër?= ,
Nathan =?utf-8?q?Gauër?= ,
Nathan =?utf-8?q?Gauër?= ,
Nathan =?utf-8?q?Gauër?=
Message-ID:
In-Reply-To:
@@ -1130,8 +1130,92 @@ struct BitTest {
static BitTest decode
Nathan =?utf-8?q?Gauër?= ,
Nathan =?utf-8?q?Gauër?= ,
Nathan =?utf-8?q?Gauër?= ,
Nathan =?utf-8?q?Gauër?= ,
Nathan =?utf-8?q?Gauër?= ,
Nathan =?utf-8?q?Gauër?= ,
Nathan =?utf-8?q?Gauër?=
Message-ID:
In-Reply-To:
https://github.com/ssahasra edited
https://github.com/llvm/llvm-project/pull/80680
Nathan =?utf-8?q?Gau=C3=ABr?= ,
Nathan =?utf-8?q?Gau=C3=ABr?= ,
Nathan =?utf-8?q?Gau=C3=ABr?= ,
Nathan =?utf-8?q?Gau=C3=ABr?= ,
Nathan =?utf-8?q?Gau=C3=ABr?= ,
Nathan =?utf-8?q?Gau=C3=ABr?= ,
Nathan =?utf-8?q?Gau=C3=ABr?=
Message-ID:
In-Reply-To:
https://github.com/ssahasra approved this pull r
Nathan =?utf-8?q?Gauër?= ,
Nathan =?utf-8?q?Gauër?= ,
Nathan =?utf-8?q?Gauër?= ,
Nathan =?utf-8?q?Gauër?=
Message-ID:
In-Reply-To:
@@ -1130,8 +1130,96 @@ struct BitTest {
static BitTest decodeBitTestBuiltin(unsigned BuiltinID);
};
+
+// Returns the first convergence entry
https://github.com/ssahasra approved this pull request.
https://github.com/llvm/llvm-project/pull/72556
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@@ -3616,6 +3617,12 @@ unsigned FunctionDecl::getBuiltinID(bool
ConsiderWrapperFunctions) const {
if (!ConsiderWrapperFunctions && getStorageClass() == SC_Static)
return 0;
+ // AMDGCN implementation supports printf as a builtin
+ // for OpenCL
+ if (Context.getTarge
https://github.com/ssahasra edited
https://github.com/llvm/llvm-project/pull/72556
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https://github.com/ssahasra requested changes to this pull request.
https://github.com/llvm/llvm-project/pull/72556
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@@ -26,28 +26,34 @@ using namespace llvm;
#define DEBUG_TYPE "amdgpu-emit-printf"
-static Value *fitArgInto64Bits(IRBuilder<> &Builder, Value *Arg) {
+static Value *fitArgInto64Bits(IRBuilder<> &Builder, Value *Arg,
+ bool IsBuffered) {
+ const
@@ -4742,6 +4742,16 @@ void Clang::ConstructJob(Compilation &C, const JobAction
&JA,
Args.ClaimAllArgs(options::OPT_gen_cdb_fragment_path);
}
+ if (TC.getTriple().isAMDGPU() && types::isOpenCL(Input.getType())) {
+if (Args.getLastArg(options::OPT_mprintf_kind_EQ))
@@ -170,20 +173,49 @@ static Value *appendString(IRBuilder<> &Builder, Value
*Desc, Value *Arg,
return callAppendStringN(Builder, Desc, Arg, Length, IsLast);
}
+static Value *appendVectorArg(IRBuilder<> &Builder, Value *Desc, Value *Arg,
+ bool
@@ -168,20 +174,48 @@ static Value *appendString(IRBuilder<> &Builder, Value
*Desc, Value *Arg,
return callAppendStringN(Builder, Desc, Arg, Length, IsLast);
}
+static Value *appendVectorArg(IRBuilder<> &Builder, Value *Desc, Value *Arg,
+ bool
@@ -198,15 +213,31 @@ RValue
CodeGenFunction::EmitAMDGPUDevicePrintfCallExpr(const CallExpr *E) {
}
llvm::Value *Arg = A.getRValue(*this).getScalarVal();
+if (isString(A.getType().getTypePtr()) && CGM.getLangOpts().OpenCL)
+ Arg = Builder.CreateAddrSpaceCast(
Author: Sameer Sahasrabuddhe
Date: 2020-01-16T15:15:38+05:30
New Revision: ed181efa175d3e0acc134e6cd161914e64c7195e
URL:
https://github.com/llvm/llvm-project/commit/ed181efa175d3e0acc134e6cd161914e64c7195e
DIFF:
https://github.com/llvm/llvm-project/commit/ed181efa175d3e0acc134e6cd161914e64c7195
Author: Sameer Sahasrabuddhe
Date: 2021-06-29T00:21:07+05:30
New Revision: 280593bd3ff1db6d19ccb8182698dd9c816734e2
URL:
https://github.com/llvm/llvm-project/commit/280593bd3ff1db6d19ccb8182698dd9c816734e2
DIFF:
https://github.com/llvm/llvm-project/commit/280593bd3ff1db6d19ccb8182698dd9c816734e
Author: Sameer Sahasrabuddhe
Date: 2022-12-12T16:32:58+05:30
New Revision: bb48aa20e761e26226c6f909a07246781d68ba41
URL:
https://github.com/llvm/llvm-project/commit/bb48aa20e761e26226c6f909a07246781d68ba41
DIFF:
https://github.com/llvm/llvm-project/commit/bb48aa20e761e26226c6f909a07246781d68ba4
Author: Sameer Sahasrabuddhe
Date: 2022-12-13T11:18:39+05:30
New Revision: cd50f910f4d1a6bb54fd8968f067febbc7320f28
URL:
https://github.com/llvm/llvm-project/commit/cd50f910f4d1a6bb54fd8968f067febbc7320f28
DIFF:
https://github.com/llvm/llvm-project/commit/cd50f910f4d1a6bb54fd8968f067febbc7320f2
@@ -178,17 +181,29 @@ RValue
CodeGenFunction::EmitNVPTXDevicePrintfCallExpr(const CallExpr *E) {
E, this, GetVprintfDeclaration(CGM.getModule()), false);
}
+// Deterimines if an argument is a string
+static bool isString(const clang::Type *argXTy) {
ssa
@@ -198,15 +213,31 @@ RValue
CodeGenFunction::EmitAMDGPUDevicePrintfCallExpr(const CallExpr *E) {
}
llvm::Value *Arg = A.getRValue(*this).getScalarVal();
+if (isString(A.getType().getTypePtr()) && CGM.getLangOpts().OpenCL)
+ Arg = Builder.CreateAddrSpaceCast(
@@ -199,15 +214,31 @@ RValue
CodeGenFunction::EmitAMDGPUDevicePrintfCallExpr(const CallExpr *E) {
}
llvm::Value *Arg = A.getRValue(*this).getScalarVal();
+if (isString(A.getType().getTypePtr()) && CGM.getLangOpts().OpenCL)
ssahasra wrote:
The typ
ssahasra wrote:
> > @jayfoad's testcase fails and the same test should be repeated for all 3
> > intrinsics
>
> added MIR tests for 3 intrinsics. The issue is that Im not able to attach the
> glue nodes to newly created laneop pieces since they fail at selection.
> #87509 should enable this,
@@ -0,0 +1,46 @@
+# RUN: not --crash llc -mtriple=amdgcn -run-pass=none -verify-machineinstrs -o
/dev/null %s 2>&1 | FileCheck %s
ssahasra wrote:
All it needs is one new file in `test/CodeGen/AMDGPU` where 64-bit lane ops are
used with a convergence tokens. Mar
@@ -18365,6 +18366,30 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned
BuiltinID,
return nullptr;
}
+void CodeGenFunction::AddAMDGCNAddressSpaceMMRA(llvm::Instruction *Inst,
+const CallExpr *E,
+
@@ -18365,6 +18366,30 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned
BuiltinID,
return nullptr;
}
+void CodeGenFunction::AddAMDGCNAddressSpaceMMRA(llvm::Instruction *Inst,
+const CallExpr *E,
+
@@ -4408,6 +4409,54 @@ Target-Specific Extensions
Clang supports some language features conditionally on some targets.
+AMDGPU Language Extensions
+--
+
+__builtin_amdgcn_fence
+^^
+
+``__builtin_amdgcn_fence`` emits a fence for all
ssahasra wrote:
> Should we also rename the MMRA to `amdgpu-fence-as` (remove OpenCL from the
> name) ?
Even the "fence" prefix is not entirely correct. The same tags also make sense
on a load-acquire or store-release, which are "fence like" instructions, or
"operations with implicit fences".
https://github.com/ssahasra approved this pull request.
The frontend changes and the MMRA emitted in LLVM IR look good to me. The
backend changes also look okay, but please see if anyone else has comments
about that.
https://github.com/llvm/llvm-project/pull/78572
_
@@ -4408,6 +4409,42 @@ Target-Specific Extensions
Clang supports some language features conditionally on some targets.
+AMDGPU Language Extensions
+--
+
+__builtin_amdgcn_fence
+^^
+
+``__builtin_amdgcn_fence`` emits a fence.
+
+* `
https://github.com/ssahasra edited
https://github.com/llvm/llvm-project/pull/78572
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@@ -18365,6 +18366,28 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned
BuiltinID,
return nullptr;
}
+void CodeGenFunction::AddAMDGCNFenceAddressSpaceMMRA(llvm::Instruction *Inst,
ssahasra wrote:
The function immediately below this uses "AMDGPU" in i
@@ -678,6 +679,59 @@ class SIMemoryLegalizer final : public MachineFunctionPass
{
bool runOnMachineFunction(MachineFunction &MF) override;
};
+static std::array, 3> ASNames = {{
+{"global", SIAtomicAddrSpace::GLOBAL},
+{"local", SIAtomicAddrSpace::LDS},
+{"image
@@ -18365,6 +18366,28 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned
BuiltinID,
return nullptr;
}
+void CodeGenFunction::AddAMDGCNFenceAddressSpaceMMRA(llvm::Instruction *Inst,
+ const CallExpr *E) {
+ constexpr
@@ -678,6 +680,54 @@ class SIMemoryLegalizer final : public MachineFunctionPass
{
bool runOnMachineFunction(MachineFunction &MF) override;
};
+static std::array, 3> ASNames = {{
ssahasra wrote:
Use StringMap for this?
https://github.com/llvm/llvm-project/
@@ -678,6 +680,54 @@ class SIMemoryLegalizer final : public MachineFunctionPass
{
bool runOnMachineFunction(MachineFunction &MF) override;
};
+static std::array, 3> ASNames = {{
+{"global", SIAtomicAddrSpace::GLOBAL},
+{"local", SIAtomicAddrSpace::LDS},
+{"image
https://github.com/ssahasra edited
https://github.com/llvm/llvm-project/pull/78572
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@@ -678,6 +680,50 @@ class SIMemoryLegalizer final : public MachineFunctionPass
{
bool runOnMachineFunction(MachineFunction &MF) override;
};
+static const StringMap ASNames = {{
+{"global", SIAtomicAddrSpace::GLOBAL},
+{"local", SIAtomicAddrSpace::LDS},
+{"imag
https://github.com/ssahasra approved this pull request.
Looks good to me. But I have no opinion about that discussion with whether
"image" should be available for explicit use!
https://github.com/llvm/llvm-project/pull/78572
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ssahasra wrote:
> > Please also update the documentation for the attribute and the release
> > notes.
>
> It looks like you may have overlooked the request to add release notes for
> this new feature.
@darkbuck, please revert and address the documentation!
https://github.com/llvm/llvm-projec
https://github.com/ssahasra created
https://github.com/llvm/llvm-project/pull/111636
These tests were failing spuriously with unrelated changes under development.
>From 107a8819e02c9a5eaf7db5a520543666ea3c3a91 Mon Sep 17 00:00:00 2001
From: Sameer Sahasrabuddhe
Date: Wed, 9 Oct 2024 11:30:37 +
https://github.com/ssahasra closed
https://github.com/llvm/llvm-project/pull/111636
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https://github.com/ssahasra created
https://github.com/llvm/llvm-project/pull/121738
None
>From e1611a9dbfe7a8239b93b84fa7682e68dc727f0f Mon Sep 17 00:00:00 2001
From: Sameer Sahasrabuddhe
Date: Mon, 6 Jan 2025 14:01:49 +0530
Subject: [PATCH] [clang][NFC] clean up the handling of convergence c
https://github.com/ssahasra closed
https://github.com/llvm/llvm-project/pull/121738
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https://github.com/llvm/llvm-project/pull/121736
>From 2cae10eb0b1e94729c26299af018216e729607de Mon Sep 17 00:00:00 2001
From: Sameer Sahasrabuddhe
Date: Thu, 2 Jan 2025 14:30:07 +0530
Subject: [PATCH 1/2] [clang] explicitly check if ParentMap contains key
T
https://github.com/ssahasra updated
https://github.com/llvm/llvm-project/pull/121736
>From 2cae10eb0b1e94729c26299af018216e729607de Mon Sep 17 00:00:00 2001
From: Sameer Sahasrabuddhe
Date: Thu, 2 Jan 2025 14:30:07 +0530
Subject: [PATCH 1/2] [clang] explicitly check if ParentMap contains key
T
@@ -78,7 +78,7 @@ static void BuildParentMap(MapTy& M, Stmt* S,
// The right thing to do is to give the OpaqueValueExpr its syntactic
// parent, then not reassign that when traversing the semantic expressions.
OpaqueValueExpr *OVE = cast(S);
-if (OVMode == OV_Tr
@@ -34,13 +34,13 @@ static void BuildParentMap(MapTy& M, Stmt* S,
case Stmt::PseudoObjectExprClass: {
PseudoObjectExpr *POE = cast(S);
-if (OVMode == OV_Opaque && M[POE->getSyntacticForm()])
+if (OVMode == OV_Opaque && M.contains(POE->getSyntacticForm()))
---
https://github.com/ssahasra created
https://github.com/llvm/llvm-project/pull/121736
The implementation of ParentMap assumes that the key is absent if it is mapped
to nullptr. This breaks when trying to store a tuple as the value type. Remove
this assumption by explicit uses of `contains()` an
https://github.com/ssahasra edited
https://github.com/llvm/llvm-project/pull/121736
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Author: Sameer Sahasrabuddhe
Date: 2025-01-08T12:03:25+05:30
New Revision: 61b806f43b2d6b3673a8f91393a28c98521472a8
URL:
https://github.com/llvm/llvm-project/commit/61b806f43b2d6b3673a8f91393a28c98521472a8
DIFF:
https://github.com/llvm/llvm-project/commit/61b806f43b2d6b3673a8f91393a28c98521472a
https://github.com/ssahasra created
https://github.com/llvm/llvm-project/pull/125627
None
>From 5d6d4fbbfabf5e33ec366ea113a0e6c93ba46bf4 Mon Sep 17 00:00:00 2001
From: Sameer Sahasrabuddhe
Date: Thu, 9 Jan 2025 13:36:20 +0530
Subject: [PATCH] [llvm] Create() functions for ConvergenceControlIns
https://github.com/ssahasra updated
https://github.com/llvm/llvm-project/pull/125627
>From 5d6d4fbbfabf5e33ec366ea113a0e6c93ba46bf4 Mon Sep 17 00:00:00 2001
From: Sameer Sahasrabuddhe
Date: Thu, 9 Jan 2025 13:36:20 +0530
Subject: [PATCH 1/2] [llvm] Create() functions for ConvergenceControlInst
https://github.com/ssahasra closed
https://github.com/llvm/llvm-project/pull/125627
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https://github.com/llvm/llvm-project/pull/125627
>From eb432f46aa1033432930e94f7db4ffc708a6f2a9 Mon Sep 17 00:00:00 2001
From: Sameer Sahasrabuddhe
Date: Thu, 9 Jan 2025 13:36:20 +0530
Subject: [PATCH] [llvm] Create() functions for ConvergenceControlInst
---
https://github.com/ssahasra closed
https://github.com/llvm/llvm-project/pull/121736
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https://github.com/ssahasra approved this pull request.
https://github.com/llvm/llvm-project/pull/128519
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@@ -1,23 +1,23 @@
-//===- AMDGPUOpenCLEnqueuedBlockLowering.h ---*-
C++-*-===//
+//===- AMDGPUExportKernelRuntimeHandles.h ---*- C++-*-===//
ssahasra wrote:
Do we need the filename and the emacs marking on the first line a
https://github.com/ssahasra edited
https://github.com/llvm/llvm-project/pull/128519
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@@ -1734,6 +1735,29 @@ define amdgpu_kernel void @unknown_addrspace_kernarg(ptr
addrspace(12345) %ptr)
ret void
}
+; Make sure the device_enqueue_symbol is not reported
+; CHECK: - .args: []
+; CHECK-NEXT: .group_segment_fixed_size: 0
+; CHECK-NEXT: .kernarg_segme
@@ -0,0 +1,110 @@
+//===- AMDGPUExportKernelRuntimeHandles.cpp - Lower enqueued block
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
https://github.com/ssahasra commented:
I don't have recent exposure to the OpenCL implementation, but generally
eyeballed the code to make sure that the changes do what is described. Is there
some confidence that the new scheme actually works? For example, maybe an
existing CodeGen test where
@@ -1,23 +1,23 @@
-//===- AMDGPUOpenCLEnqueuedBlockLowering.h ---*-
C++-*-===//
+//===- AMDGPUExportKernelRuntimeHandles.h ---*- C++-*-===//
ssahasra wrote:
The requirement was dropped from the LLVM Coding Standards, and t
ssahasra wrote:
To take this to its logical conclusion, when convergence tokens are in use, the
`convergent` attribute is redundant. All we need is a `noconvergent` attribute
for function declarations. A function definition is convergent iff the body
contains a call to the `entry` intrinsic, a
ssahasra wrote:
>From the spec for convergence control tokens:
https://llvm.org/docs/ConvergentOperations.html#inferring-non-convergence
> An optimizer may remove the convergent attribute on a function if it can
> prove that the function does not contain a call to
> `llvm.experimental.converge
ssahasra wrote:
> When a callee is marked as convergent, some targets like HLSL/SPIR-V add a
> convergent token to the call.
This is valid if both functions are marked as convergent.
I didn't understand the validity part. Why is the caller required to be
convergent in order to add a token to a
https://github.com/ssahasra created
https://github.com/llvm/llvm-project/pull/132701
When placed on a function, the ``clang::noconvergent`` attribute ensures that
the function is not assumed to be convergent. But the same attribute has no
effect on function calls. A call is convergent if the c
https://github.com/ssahasra closed
https://github.com/llvm/llvm-project/pull/132701
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