@@ -2854,10 +2854,121 @@ void CodeGenFunction::EmitMultiVersionResolver(
case llvm::Triple::aarch64:
EmitAArch64MultiVersionResolver(Resolver, Options);
return;
+ case llvm::Triple::riscv32:
+ case llvm::Triple::riscv64:
+EmitRISCVMultiVersionResolver(Resolver,
https://github.com/BeMg edited https://github.com/llvm/llvm-project/pull/85786
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@@ -2854,10 +2854,121 @@ void CodeGenFunction::EmitMultiVersionResolver(
case llvm::Triple::aarch64:
EmitAArch64MultiVersionResolver(Resolver, Options);
return;
+ case llvm::Triple::riscv32:
+ case llvm::Triple::riscv64:
+EmitRISCVMultiVersionResolver(Resolver,
BeMg wrote:
Update:
1. Remove all the `__riscv_feature_bits.length` checker due to unnecessary now.
2. Rebase with origin/main for tablegen change
3. Extract some common code as helper function
4. Replace RequireFeautreBits with getExtensionBitmask and compute the concrete
bitmask inside CodeGe
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786
>From 395ce72afbf9e4b12fcbfaf9cdbda8921c9ff72a Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Tue, 23 Jul 2024 19:59:06 -0700
Subject: [PATCH 01/14] [RISCV][FMV] Support target_clones
---
.../clang/Basic/Diagnosti
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786
>From 395ce72afbf9e4b12fcbfaf9cdbda8921c9ff72a Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Tue, 23 Jul 2024 19:59:06 -0700
Subject: [PATCH 01/15] [RISCV][FMV] Support target_clones
---
.../clang/Basic/Diagnosti
https://github.com/BeMg created https://github.com/llvm/llvm-project/pull/106495
…isValidFeatureName
This patch makes unsupported target attributes emit a warning and ignore the
target attribute during semantic checks. The changes include:
1. Adding the RISCVTargetInfo::isValidFeatureName func
@@ -391,7 +391,14 @@ void RISCVTargetInfo::fillValidTuneCPUList(
static void handleFullArchString(StringRef FullArchStr,
std::vector &Features) {
- Features.push_back("__RISCV_TargetAttrNeedOverride");
+
+ // Should be full arch string.
+ if
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/106495
>From 64557cf6950c17a92b6d85980530abe1e193e111 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Wed, 28 Aug 2024 21:15:57 -0700
Subject: [PATCH 1/2] [Clang][RISCV] Recognize unsupport feature by supporting
isValidFe
@@ -391,7 +391,14 @@ void RISCVTargetInfo::fillValidTuneCPUList(
static void handleFullArchString(StringRef FullArchStr,
std::vector &Features) {
- Features.push_back("__RISCV_TargetAttrNeedOverride");
+
+ // Should be full arch string.
+ if
https://github.com/BeMg created https://github.com/llvm/llvm-project/pull/106680
This patch aims to replace the target attribute override mechanism based on
`__RISCV_TargetAttrNeedOverride` with the insertion of several negative target
features
When the target attribute uses the full architect
@@ -257,7 +257,7 @@ bool RISCVTargetInfo::initFeatureMap(
// If a target attribute specified a full arch string, override all the ISA
// extension target features.
- const auto I = llvm::find(FeaturesVec, "__RISCV_TargetAttrNeedOverride");
+ const auto I = llvm::find(Fea
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/106495
>From 64557cf6950c17a92b6d85980530abe1e193e111 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Wed, 28 Aug 2024 21:15:57 -0700
Subject: [PATCH 1/3] [Clang][RISCV] Recognize unsupport feature by supporting
isValidFe
@@ -2993,10 +2993,17 @@ bool Sema::checkTargetAttr(SourceLocation LiteralLoc,
StringRef AttrStr) {
return Diag(LiteralLoc, diag::warn_unsupported_target_attribute)
<< Unknown << Tune << ParsedAttrs.Tune << Target;
- if (Context.getTargetInfo().getTriple().isRI
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/106495
>From e8f472674e0d1e70adcd1d29b8c902f4cd80f188 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Wed, 28 Aug 2024 21:15:57 -0700
Subject: [PATCH 1/3] [Clang][RISCV] Recognize unsupport feature by supporting
isValidFe
https://github.com/BeMg edited https://github.com/llvm/llvm-project/pull/106495
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BeMg wrote:
Rebase with https://github.com/llvm/llvm-project/pull/106680 and drop the
`__RISCV_TargetAttrNeedOverride` relate code section.
https://github.com/llvm/llvm-project/pull/106495
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>From e8f472674e0d1e70adcd1d29b8c902f4cd80f188 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Wed, 28 Aug 2024 21:15:57 -0700
Subject: [PATCH 1/4] [Clang][RISCV] Recognize unsupport feature by supporting
isValidFe
https://github.com/BeMg closed https://github.com/llvm/llvm-project/pull/106680
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https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786
>From 38e5bef5d20d7e81170720eb56354c0392f5c902 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Wed, 5 Jun 2024 01:17:03 -0700
Subject: [PATCH 1/3] [RISCV] Add groupid/bitmask for RISC-V extension
Base on https://git
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786
>From 38e5bef5d20d7e81170720eb56354c0392f5c902 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Wed, 5 Jun 2024 01:17:03 -0700
Subject: [PATCH 1/4] [RISCV] Add groupid/bitmask for RISC-V extension
Base on https://git
https://github.com/BeMg ready_for_review
https://github.com/llvm/llvm-project/pull/85786
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BeMg wrote:
1. Drop the full arch string syntax due to this syntax be removed from spec.
https://github.com/llvm/llvm-project/pull/85786
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BeMg wrote:
This patch support the `target_clones` function attribute and function
multiversioning feature for RISC-V target. It will generate the ifunc resolver
function for the function that declared with target_clones attribute.
The resolver function will check the version support by runti
https://github.com/BeMg converted_to_draft
https://github.com/llvm/llvm-project/pull/85786
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BeMg wrote:
> Alongside #101449, this seems to be extending the interface beyond what is
> described in the [current draft
> spec](https://github.com/riscv-non-isa/riscv-c-api-doc/pull/74). Is there
> some other source of truth I should be looking for? Is this a proposal to
> change the spec,
https://github.com/BeMg created https://github.com/llvm/llvm-project/pull/101632
1. Add the new extension GroupID/Bitmask with latest hwprobe key.
2. Update the `initRISCVFeature `
3. Update `EmitRISCVCpuSupports` due to not only group0 now.
>From 91ebb0568f28015006e3443221ae51f92c159dfb Mon S
https://github.com/BeMg edited https://github.com/llvm/llvm-project/pull/101632
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https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/101632
>From 91ebb0568f28015006e3443221ae51f92c159dfb Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Fri, 2 Aug 2024 01:07:04 -0700
Subject: [PATCH 1/2] [RISCV] Suuport new bitmask for cpu_model
---
clang/lib/CodeGen/CG
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786
>From 708c81609c603c5ea820493e92d8c82cf4620d64 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Tue, 23 Jul 2024 19:59:06 -0700
Subject: [PATCH 1/4] [RISCV][FMV] Support target_clones
---
.../clang/Basic/DiagnosticF
BeMg wrote:
Support new syntax `Priority` to define priority for specific version from
user.
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/85
https://github.com/llvm/llvm-project/pull/85786
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https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/101632
>From 91ebb0568f28015006e3443221ae51f92c159dfb Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Fri, 2 Aug 2024 01:07:04 -0700
Subject: [PATCH 1/5] [RISCV] Suuport new bitmask for cpu_model
---
clang/lib/CodeGen/CG
@@ -1056,24 +1056,12 @@ constexpr static RISCVExtBit RISCVBitPositions[] = {
{"zcf", 1, 5},{"zcmop", 1, 6},
{"zawrs", 1, 7}};
-int RISCVISAInfo::getRISCVFeaturesBitPosition(StringRef Ext) {
+std::pair RISCVISAInfo::getRISCVFeaturesBitsInfo(StringRef Ext) {
/
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/104917
>From c8b31f1e1d1d30cb8523772d3fd15a0358c540d6 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Tue, 20 Aug 2024 04:37:20 -0700
Subject: [PATCH 1/2] [RISC-V] Make EmitRISCVCpuSupports accept multiple
features
This
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786
>From c8b31f1e1d1d30cb8523772d3fd15a0358c540d6 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Tue, 20 Aug 2024 04:37:20 -0700
Subject: [PATCH 1/4] [RISC-V] Make EmitRISCVCpuSupports accept multiple
features
This p
BeMg wrote:
Rebase and stack on https://github.com/llvm/llvm-project/pull/104917
https://github.com/llvm/llvm-project/pull/85786
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https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/104917
>From c8b31f1e1d1d30cb8523772d3fd15a0358c540d6 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Tue, 20 Aug 2024 04:37:20 -0700
Subject: [PATCH 1/5] [RISC-V] Make EmitRISCVCpuSupports accept multiple
features
This
@@ -14439,33 +14440,60 @@ Value *CodeGenFunction::EmitRISCVCpuSupports(const
CallExpr *E) {
if (!getContext().getTargetInfo().validateCpuSupports(FeatureStr))
return Builder.getFalse();
- // Note: We are making an unchecked assumption that the size of the
- // feature
@@ -32,6 +32,8 @@ struct RISCVExtensionBitmask {
};
} // namespace RISCVExtensionBitmaskTable
+static constexpr unsigned RISCVFeatureBitSize = 2;
BeMg wrote:
Now it named FeatureBitSize and place in RISCVISAInfo.h
https://github.com/llvm/llvm-project/pull/10
https://github.com/BeMg closed https://github.com/llvm/llvm-project/pull/104917
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https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786
>From 395ce72afbf9e4b12fcbfaf9cdbda8921c9ff72a Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Tue, 23 Jul 2024 19:59:06 -0700
Subject: [PATCH 1/2] [RISCV][FMV] Support target_clones
---
.../clang/Basic/DiagnosticF
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786
>From 395ce72afbf9e4b12fcbfaf9cdbda8921c9ff72a Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Tue, 23 Jul 2024 19:59:06 -0700
Subject: [PATCH 1/4] [RISCV][FMV] Support target_clones
---
.../clang/Basic/DiagnosticF
@@ -2854,10 +2854,121 @@ void CodeGenFunction::EmitMultiVersionResolver(
case llvm::Triple::aarch64:
EmitAArch64MultiVersionResolver(Resolver, Options);
return;
+ case llvm::Triple::riscv32:
+ case llvm::Triple::riscv64:
+EmitRISCVMultiVersionResolver(Resolver,
@@ -2877,10 +2877,144 @@ void CodeGenFunction::EmitMultiVersionResolver(
case llvm::Triple::aarch64:
EmitAArch64MultiVersionResolver(Resolver, Options);
return;
+ case llvm::Triple::riscv32:
+ case llvm::Triple::riscv64:
+EmitRISCVMultiVersionResolver(Resolver,
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786
>From 395ce72afbf9e4b12fcbfaf9cdbda8921c9ff72a Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Tue, 23 Jul 2024 19:59:06 -0700
Subject: [PATCH 01/11] [RISCV][FMV] Support target_clones
---
.../clang/Basic/Diagnosti
@@ -63,9 +63,55 @@ class RISCVABIInfo : public DefaultABIInfo {
CharUnits Field2Off) const;
ABIArgInfo coerceVLSVector(QualType Ty) const;
+
+ using ABIInfo::appendAttributeMangling;
+ void appendAttributeMangling(TargetClones
@@ -2877,10 +2877,144 @@ void CodeGenFunction::EmitMultiVersionResolver(
case llvm::Triple::aarch64:
EmitAArch64MultiVersionResolver(Resolver, Options);
return;
+ case llvm::Triple::riscv32:
+ case llvm::Triple::riscv64:
+EmitRISCVMultiVersionResolver(Resolver,
@@ -2877,10 +2877,144 @@ void CodeGenFunction::EmitMultiVersionResolver(
case llvm::Triple::aarch64:
EmitAArch64MultiVersionResolver(Resolver, Options);
return;
+ case llvm::Triple::riscv32:
+ case llvm::Triple::riscv64:
+EmitRISCVMultiVersionResolver(Resolver,
@@ -2877,10 +2877,144 @@ void CodeGenFunction::EmitMultiVersionResolver(
case llvm::Triple::aarch64:
EmitAArch64MultiVersionResolver(Resolver, Options);
return;
+ case llvm::Triple::riscv32:
+ case llvm::Triple::riscv64:
+EmitRISCVMultiVersionResolver(Resolver,
@@ -63,9 +63,55 @@ class RISCVABIInfo : public DefaultABIInfo {
CharUnits Field2Off) const;
ABIArgInfo coerceVLSVector(QualType Ty) const;
+
+ using ABIInfo::appendAttributeMangling;
+ void appendAttributeMangling(TargetClones
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786
>From 395ce72afbf9e4b12fcbfaf9cdbda8921c9ff72a Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Tue, 23 Jul 2024 19:59:06 -0700
Subject: [PATCH 01/12] [RISCV][FMV] Support target_clones
---
.../clang/Basic/Diagnosti
@@ -2877,10 +2877,144 @@ void CodeGenFunction::EmitMultiVersionResolver(
case llvm::Triple::aarch64:
EmitAArch64MultiVersionResolver(Resolver, Options);
return;
+ case llvm::Triple::riscv32:
+ case llvm::Triple::riscv64:
+EmitRISCVMultiVersionResolver(Resolver,
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786
>From 395ce72afbf9e4b12fcbfaf9cdbda8921c9ff72a Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Tue, 23 Jul 2024 19:59:06 -0700
Subject: [PATCH 01/13] [RISCV][FMV] Support target_clones
---
.../clang/Basic/Diagnosti
BeMg wrote:
ping
https://github.com/llvm/llvm-project/pull/85786
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https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786
>From 937fecdd1a95baf99ca42ea832efac885aef720e Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Wed, 5 Jun 2024 01:17:03 -0700
Subject: [PATCH 1/2] [RISCV] Add groupid/bitmask for RISC-V extension
---
.../llvm/Targe
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786
>From 395ce72afbf9e4b12fcbfaf9cdbda8921c9ff72a Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Tue, 23 Jul 2024 19:59:06 -0700
Subject: [PATCH 01/18] [RISCV][FMV] Support target_clones
---
.../clang/Basic/Diagnosti
https://github.com/BeMg closed https://github.com/llvm/llvm-project/pull/85786
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https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/99040
>From 54b5d6833a52271dfd1ca3912d5d9e886b1970c2 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Tue, 19 Mar 2024 02:02:35 -0700
Subject: [PATCH] [RISCV][FMV] Support target_version
---
clang/lib/AST/ASTContext.cpp
BeMg wrote:
Rebase to main
https://github.com/llvm/llvm-project/pull/99040
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https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/99040
>From 54b5d6833a52271dfd1ca3912d5d9e886b1970c2 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Tue, 19 Mar 2024 02:02:35 -0700
Subject: [PATCH 1/2] [RISCV][FMV] Support target_version
---
clang/lib/AST/ASTContext.c
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/99040
>From 54b5d6833a52271dfd1ca3912d5d9e886b1970c2 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Tue, 19 Mar 2024 02:02:35 -0700
Subject: [PATCH 1/3] [RISCV][FMV] Support target_version
---
clang/lib/AST/ASTContext.c
@@ -10319,8 +10319,10 @@ Sema::ActOnFunctionDeclarator(Scope *S, Declarator &D,
DeclContext *DC,
// Handle attributes.
ProcessDeclAttributes(S, NewFD, D);
const auto *NewTVA = NewFD->getAttr();
- if (NewTVA && !NewTVA->isDefaultVersion() &&
- !Context.getTargetInfo
https://github.com/BeMg closed https://github.com/llvm/llvm-project/pull/111333
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https://github.com/BeMg created https://github.com/llvm/llvm-project/pull/112161
Ensure that target_version and target_clones do not accept negative numbers for
the priority feature.
Base on discussion on https://github.com/riscv-non-isa/riscv-c-api-doc/pull/85.
>From d7a00a878b472e1ba7abad1b
@@ -111,3 +111,9 @@ __attribute__((target_version("default"))) int
invalidVerson4(void) { return 2;
__attribute__((target_version("priority=1"))) int prioriyWithoutArch(void) {
return 2; }
// expected-error@+1 {{redefinition of 'prioriyWithoutArch'}}
__attribute__((target_ver
https://github.com/BeMg edited https://github.com/llvm/llvm-project/pull/112161
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https://github.com/BeMg created https://github.com/llvm/llvm-project/pull/111333
Fix the buildbot failure caused by heap use-after-free error.
Origin message:
This patch enable `target_version` attribute for RISC-V target.
The proposal of `target_version` syntax can be found at the
https://github.com/BeMg closed https://github.com/llvm/llvm-project/pull/111096
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>From d7a00a878b472e1ba7abad1b915cb57c4b0a5ca3 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Sun, 6 Oct 2024 22:19:07 -0700
Subject: [PATCH 1/2] [RISCV][FMV] Remove support for negative priority
---
clang/lib/Co
https://github.com/BeMg closed https://github.com/llvm/llvm-project/pull/112161
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@@ -2909,18 +2909,16 @@ static int getPriorityFromAttrString(StringRef AttrStr)
{
AttrStr.split(Attrs, ';');
BeMg wrote:
Sure.
https://github.com/llvm/llvm-project/pull/112161
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https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/112161
>From d7a00a878b472e1ba7abad1b915cb57c4b0a5ca3 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Sun, 6 Oct 2024 22:19:07 -0700
Subject: [PATCH 1/4] [RISCV][FMV] Remove support for negative priority
---
clang/lib/Co
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/112161
>From d7a00a878b472e1ba7abad1b915cb57c4b0a5ca3 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Sun, 6 Oct 2024 22:19:07 -0700
Subject: [PATCH 1/5] [RISCV][FMV] Remove support for negative priority
---
clang/lib/Co
https://github.com/BeMg approved this pull request.
LGTM. Thanks for fix this issue!
https://github.com/llvm/llvm-project/pull/112827
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https://github.com/BeMg closed https://github.com/llvm/llvm-project/pull/99040
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https://github.com/BeMg created https://github.com/llvm/llvm-project/pull/111096
Reverts llvm/llvm-project#99040 to fix
https://lab.llvm.org/buildbot/#/builders/190/builds/7052
>From 32174720649068de7c4ef97a484d777dba72e65c Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Fri, 4 Oct 2024 11:55:
https://github.com/BeMg created https://github.com/llvm/llvm-project/pull/115981
Base on https://github.com/riscv-non-isa/riscv-c-api-doc/pull/94.
This patch support the `norelax` attribute for RISC-V target in clang.
>From 9dc14ca1e5d026c05390c728c9512994e05d8be7 Mon Sep 17 00:00:00 2001
From:
https://github.com/BeMg created https://github.com/llvm/llvm-project/pull/115991
Address https://github.com/llvm/llvm-project/issues/115000.
This patch constrains the target_version feature to work only on RISC-V and
AArch64 to prevent crashes in Clang.
>From 28f7a2adc055ec6f30790e1e9535c7124
@@ -3056,6 +3056,45 @@ bool Sema::checkTargetVersionAttr(SourceLocation
LiteralLoc, Decl *D,
enum SecondParam { None };
enum ThirdParam { Target, TargetClones, TargetVersion };
llvm::SmallVector Features;
+ if (Context.getTargetInfo().getTriple().isRISCV()) {
+
+llv
https://github.com/BeMg edited https://github.com/llvm/llvm-project/pull/99040
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@@ -3056,6 +3056,45 @@ bool Sema::checkTargetVersionAttr(SourceLocation
LiteralLoc, Decl *D,
enum SecondParam { None };
enum ThirdParam { Target, TargetClones, TargetVersion };
llvm::SmallVector Features;
+ if (Context.getTargetInfo().getTriple().isRISCV()) {
+
+llv
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/99040
>From 54b5d6833a52271dfd1ca3912d5d9e886b1970c2 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Tue, 19 Mar 2024 02:02:35 -0700
Subject: [PATCH 1/9] [RISCV][FMV] Support target_version
---
clang/lib/AST/ASTContext.c
@@ -14270,9 +14270,16 @@ void
ASTContext::getFunctionFeatureMap(llvm::StringMap &FeatureMap,
Target->initFeatureMap(FeatureMap, getDiagnostics(), TargetCPU,
Features);
}
} else if (const auto *TV = FD->getAttr()) {
-llvm::SmallVector Feats;
-TV->getFeature
@@ -4268,8 +4268,12 @@ void CodeGenModule::emitMultiVersionFunctions() {
} else if (const auto *TVA = CurFD->getAttr()) {
if (TVA->isDefaultVersion() && IsDefined)
ShouldEmitResolver = true;
-TVA->getFeatures(Feats);
@@ -15501,8 +15511,10 @@ Decl *Sema::ActOnStartOfFunctionDef(Scope
*FnBodyScope, Decl *D,
FD->setInvalidDecl();
}
if (const auto *Attr = FD->getAttr()) {
-if (!Context.getTargetInfo().hasFeature("fmv") &&
-!Attr->isDefaultVersion()) {
+if (Context.getTa
@@ -3056,6 +3056,45 @@ bool Sema::checkTargetVersionAttr(SourceLocation
LiteralLoc, Decl *D,
enum SecondParam { None };
enum ThirdParam { Target, TargetClones, TargetVersion };
llvm::SmallVector Features;
+ if (Context.getTargetInfo().getTriple().isRISCV()) {
+
+llv
https://github.com/BeMg created https://github.com/llvm/llvm-project/pull/110098
This patch add a condition that check the `__riscv_feature_bits.length` before
access `__riscv_feature_bits.features`.
It updates the resolver function as the following structure.
```
if (__riscv_feature_bits.fe
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/110098
>From 838c6669d2f4464b9b528b0d633ad363b92e3b57 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Thu, 26 Sep 2024 02:16:56 -0700
Subject: [PATCH 1/2] [FMV][RISCV] Check FeatureBits.length before test all
version
---
BeMg wrote:
There is misunderstand here. Close it now and reopen when it ready.
https://github.com/llvm/llvm-project/pull/110098
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https://github.com/BeMg closed https://github.com/llvm/llvm-project/pull/110098
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@@ -3056,6 +3056,47 @@ bool Sema::checkTargetVersionAttr(SourceLocation
LiteralLoc, Decl *D,
enum SecondParam { None };
enum ThirdParam { Target, TargetClones, TargetVersion };
llvm::SmallVector Features;
+ if (Context.getTargetInfo().getTriple().isRISCV()) {
+
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/99040
>From 54b5d6833a52271dfd1ca3912d5d9e886b1970c2 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Tue, 19 Mar 2024 02:02:35 -0700
Subject: [PATCH 1/5] [RISCV][FMV] Support target_version
---
clang/lib/AST/ASTContext.c
@@ -11027,13 +11029,27 @@ static bool CheckMultiVersionValue(Sema &S, const
FunctionDecl *FD) {
}
if (TVA) {
-llvm::SmallVector Feats;
-TVA->getFeatures(Feats);
-for (const auto &Feat : Feats) {
- if (!TargetInfo.validateCpuSupports(Feat)) {
-S.Di
BeMg wrote:
Seem we don't support this attribute.
https://github.com/llvm/llvm-project/pull/115981
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https://github.com/BeMg closed https://github.com/llvm/llvm-project/pull/115981
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https://github.com/BeMg approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/116257
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BeMg wrote:
Fix the merge conflict
https://github.com/llvm/llvm-project/pull/115991
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https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/115991
>From 28f7a2adc055ec6f30790e1e9535c71241a08e29 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Tue, 12 Nov 2024 20:56:47 -0800
Subject: [PATCH 1/7] [TargetVersion] Only enable on RISC-V and AArch64
---
clang/inclu
@@ -3040,6 +3040,11 @@ bool Sema::checkTargetVersionAttr(SourceLocation
LiteralLoc, Decl *D,
enum FirstParam { Unsupported };
enum SecondParam { None };
enum ThirdParam { Target, TargetClones, TargetVersion };
+
+ if (!Context.getTargetInfo().getTriple().isRISCV() &&
+
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