@@ -16920,6 +16920,58 @@ Value *CodeGenFunction::EmitX86BuiltinExpr(unsigned
BuiltinID,
// instruction, but it will create a memset that won't be optimized away.
return Builder.CreateMemSet(Ops[0], Ops[1], Ops[2], Align(1), true);
}
+ // Corresponding to intrisics w
@@ -5189,6 +5193,33 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
ReplaceNode(Node, CNode);
return;
}
+case Intrinsic::x86_tileloaddrs64_internal:
+case Intrinsic::x86_tileloaddrst164_internal: {
+ if (!Subtarget->hasAMXMOVRS())
+break;
--
https://github.com/phoebewang edited
https://github.com/llvm/llvm-project/pull/115151
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@@ -27291,6 +27291,13 @@ static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op,
const X86Subtarget &Subtarget,
return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), SetCC,
Operation.getValue(1));
}
+case Intrinsic::x86_t2rpntlvwz0rs_inter
@@ -558,6 +558,15 @@ bool X86ExpandPseudo::expandMI(MachineBasicBlock &MBB,
MI.setDesc(TII->get(GET_EGPR_IF_ENABLED(X86::LDTILECFG)));
return true;
}
+ case X86::PTILELOADDRSV:
+ case X86::PTILELOADDRST1V: {
+for (unsigned i = 2; i > 0; --i)
+ MI.removeOper
@@ -687,6 +696,32 @@ bool X86ExpandPseudo::expandMI(MachineBasicBlock &MBB,
MI.setDesc(TII->get(Opc));
return true;
}
+ case X86::PT2RPNTLVWZ0RSV:
+ case X86::PT2RPNTLVWZ0RST1V:
+ case X86::PT2RPNTLVWZ1RSV:
+ case X86::PT2RPNTLVWZ1RST1V: {
phoebew
@@ -5342,9 +5411,45 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
SDValue Disp = CurDAG->getTargetConstant(0, dl, MVT::i32);
SDValue Segment = CurDAG->getRegister(0, MVT::i16);
SDValue Chain = Node->getOperand(0);
- MachineSDNode *CNode;
SDValue
@@ -5307,6 +5338,44 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
ReplaceNode(Node, CNode);
return;
}
+case Intrinsic::x86_tileloaddrs64:
+case Intrinsic::x86_tileloaddrst164: {
phoebewang wrote:
ditto.
https://github.com/llvm/llvm-p
@@ -369,3 +369,94 @@ let Predicates = [HasAMXTRANSPOSE, In64BitMode] in {
}
}
} // HasAMXTILE, HasAMXTRANSPOSE
+
+let Predicates = [HasAMXMOVRS, HasAMXTRANSPOSE, In64BitMode], SchedRW =
[WriteSystem] in {
+ def T2RPNTLVWZ0RS : I<0xf8, MRMSrcMemFSIB, (outs TILEPair:$ds
@@ -37605,6 +37653,39 @@
X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
MI.eraseFromParent(); // The pseudo is gone now.
return BB;
}
+ case X86::PT2RPNTLVWZ0RS:
+ case X86::PT2RPNTLVWZ0RST1:
+ case X86::PT2RPNTLVWZ1RS:
+ case X86::PT2RPNTL
@@ -37553,6 +37572,35 @@
X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
MI.eraseFromParent(); // The pseudo is gone now.
return BB;
}
+ case X86::PTILELOADDRS:
+ case X86::PTILELOADDRST1: {
phoebewang wrote:
Merge with above.
ht
@@ -6101,6 +6101,25 @@ let TargetPrefix = "x86" in {
Intrinsic<[llvm_v16i32_ty],
[llvm_i16_ty, llvm_i16_ty, llvm_x86amx_ty,
llvm_i32_ty],
[]>;
+
+ def int_x86_tmmultf32ps : ClangBuiltin<"__builtin_ia32_tmmultf32ps"
@@ -660,6 +660,10 @@ _storebe_i64(void * __P, long long __D) {
#include
#endif
+#if !defined(__SCE__) || __has_feature(modules) || defined(__AMX_TF32__)
+#include
+#endif
+
phoebewang wrote:
ditto.
https://github.com/llvm/llvm-project/pull/115625
_
@@ -151,6 +151,7 @@ set(x86_files
amxfp16intrin.h
amxfp8intrin.h
amxintrin.h
+ amxtf32intrin.h
phoebewang wrote:
Missing the new file.
https://github.com/llvm/llvm-project/pull/115625
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@@ -27291,6 +27291,13 @@ static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op,
const X86Subtarget &Subtarget,
return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), SetCC,
Operation.getValue(1));
}
+case Intrinsic::x86_t2rpntlvwz0rs_inter
https://github.com/phoebewang deleted
https://github.com/llvm/llvm-project/pull/115151
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https://github.com/llvm/llvm-project/pull/115660
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
>From f2fc493149d75f0be13207bc1893a48c7fab84a3 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Sun, 10 Nov 2024 22:37:15 +0800
Subject: [PATCH] [X86
https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/115581
Resolve compile fail without SSE2.
>From 54b3ba2bc49e04293e8543f37dae9b8f362c04e4 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Sat, 9 Nov 2024 12:48:19 +0800
Subject: [PATCH 1/2] Reland "[X86][AMX] Su
@@ -37686,6 +37686,28 @@
X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
MI.eraseFromParent(); // The pseudo is gone now.
return BB;
}
+ case X86::PTMMULTF32PS:
+ case X86::PTTMMULTF32PS: {
+const DebugLoc &DL = MI.getDebugLoc();
+unsigned
@@ -0,0 +1,47 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-tile,+avx512f, \
+; RUN: -mattr=+amx-tf32,+amx-transpose -verify-machineinstrs | FileCheck %s
+
+define void @test_amx(i8* %
@@ -0,0 +1,194 @@
+/*===- amxtf32intrin.h - AMX_TF32 intrinsics -*- C++ -*-===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apac
https://github.com/phoebewang commented:
Add Clang release note
Add `Features["amx-movrs"]` in Host.cpp
Add `AMX_MOVRS` in X86TargetParser.def
Add `ImpliedFeaturesAMX_MOVRS` in X86TargetParser.cpp
https://github.com/llvm/llvm-project/pull/115151
___
c
@@ -4738,6 +4738,7 @@ static bool isAMXOpcode(unsigned Opc) {
case X86::TILELOADD_EVEX:
case X86::TILESTORED_EVEX:
case X86::PTILEPAIRLOAD:
+ case X86::TILELOADDRS:
phoebewang wrote:
This is not needed.
https://github.com/llvm/llvm-project/pull/115151
https://github.com/phoebewang edited
https://github.com/llvm/llvm-project/pull/115151
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https://github.com/phoebewang approved this pull request.
Looks reasonable given
https://github.com/llvm/llvm-project/commit/a2d309912a2863dfe7286ffde67b968e8c720b07
is for ifunc only.
https://github.com/llvm/llvm-project/pull/115762
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@@ -23,7 +23,7 @@
static __inline__ __m512i __DEFAULT_FN_ATTRS
_mm512_popcnt_epi16(__m512i __A)
{
- return (__m512i) __builtin_ia32_vpopcntw_512((__v32hi) __A);
+ return (__m512i)__builtin_elementwise_popcount((__v32hi)__A);
phoebewang wrote:
hi or hu? The s
https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/109598
The `-m[no-]evex512` are nontrivial options which are used to control vector
size of other AVX512 features. Hence we expose both to flang for Fortran users.
>From d9aa2912206bb435bc830a42bc5ddd8b604c7d98 Mon
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/109598
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LGTM.
https://github.com/llvm/llvm-project/pull/109577
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@@ -144,6 +144,7 @@ add_clang_library(clangCodeGen
VarBypassDetector.cpp
DEPENDS
+ vt_gen
phoebewang wrote:
Why it depends?
https://github.com/llvm/llvm-project/pull/109342
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https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/110515
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https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/110508
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https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/110499
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https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/110535
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@@ -86,5 +98,17 @@ char pext64_0[_pext_u64(0x0123456789ABCDEFULL,
0xULL) == 0x0
char pext64_1[_pext_u64(0x0123456789ABCDEFULL, 0x00F0ULL) ==
0x000EULL ? 1 : -1];
char pext64_2[_pext_u64(0x0123456789ABCDEFULL, 0xF0F0F0F0ULL) =
https://github.com/phoebewang edited
https://github.com/llvm/llvm-project/pull/110654
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https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/110654
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phoebewang wrote:
@mahesh-attarde please solve the conflict.
https://github.com/llvm/llvm-project/pull/108537
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https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/109160
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LGTM.
https://github.com/llvm/llvm-project/pull/110668
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https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/114070
>From 587d0105e7724db0f35fc5c8179519fa6319e5c8 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Tue, 29 Oct 2024 22:29:25 +0800
Subject: [PATCH 1/2] [X86][AMX] Support AMX-AVX512
---
clang/docs/ReleaseNo
@@ -0,0 +1,381 @@
+/*===- amxavx512intrin.h - AMXAVX512
===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Ap
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/114070
>From 587d0105e7724db0f35fc5c8179519fa6319e5c8 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Tue, 29 Oct 2024 22:29:25 +0800
Subject: [PATCH] [X86][AMX] Support AMX-AVX512
---
clang/docs/ReleaseNotes.
@@ -559,12 +559,68 @@ bool X86ExpandPseudo::expandMI(MachineBasicBlock &MBB,
return true;
}
case X86::PTILELOADDV:
- case X86::PTILELOADDT1V: {
+ case X86::PTILELOADDT1V:
+ case X86::PTCVTROWD2PSrreV:
+ case X86::PTCVTROWD2PSrriV:
+ case X86::PTCVTROWPS2PBF16HrreV:
@@ -0,0 +1,381 @@
+/*===- amxavx512intrin.h - AMXAVX512
===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Ap
@@ -0,0 +1,381 @@
+/*===- amxavx512intrin.h - AMXAVX512
===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Ap
https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/113274
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LGTM.
https://github.com/llvm/llvm-project/pull/113402
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@@ -665,6 +665,9 @@ _storebe_i64(void * __P, long long __D) {
#include
#include
#include
+#if (defined(__SM4__))
phoebewang wrote:
Oh, we should use
```
#if !defined(__SCE__) || __has_feature(modules) || \
(defined(__AVX10_2_
@@ -0,0 +1,64 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-- --show-mc-encoding
-mattr=+sm4,+avx10.2-512 | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=i686-- --show-mc-enc
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/114070
>From 587d0105e7724db0f35fc5c8179519fa6319e5c8 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Tue, 29 Oct 2024 22:29:25 +0800
Subject: [PATCH 1/3] [X86][AMX] Support AMX-AVX512
---
clang/docs/ReleaseNo
@@ -133,6 +133,12 @@ TARGET_BUILTIN(__builtin_ia32_t2rpntlvwz0t1_internal,
"vUsUsUsV256i*V256i*vC*z",
TARGET_BUILTIN(__builtin_ia32_t2rpntlvwz1_internal, "vUsUsUsV256i*V256i*vC*z",
"n", "amx-transpose")
TARGET_BUILTIN(__builtin_ia32_t2rpntlvwz1t1_internal,
"vUsUsUsV256i*V256i
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/114070
>From 587d0105e7724db0f35fc5c8179519fa6319e5c8 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Tue, 29 Oct 2024 22:29:25 +0800
Subject: [PATCH 1/4] [X86][AMX] Support AMX-AVX512
---
clang/docs/ReleaseNo
@@ -133,6 +133,12 @@ TARGET_BUILTIN(__builtin_ia32_t2rpntlvwz0t1_internal,
"vUsUsUsV256i*V256i*vC*z",
TARGET_BUILTIN(__builtin_ia32_t2rpntlvwz1_internal, "vUsUsUsV256i*V256i*vC*z",
"n", "amx-transpose")
TARGET_BUILTIN(__builtin_ia32_t2rpntlvwz1t1_internal,
"vUsUsUsV256i*V256i
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/114070
>From 587d0105e7724db0f35fc5c8179519fa6319e5c8 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Tue, 29 Oct 2024 22:29:25 +0800
Subject: [PATCH 1/5] [X86][AMX] Support AMX-AVX512
---
clang/docs/ReleaseNo
@@ -0,0 +1,381 @@
+/*===- amxavx512intrin.h - AMXAVX512
===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Ap
@@ -369,3 +369,150 @@ let Predicates = [HasAMXTRANSPOSE, In64BitMode] in {
}
}
} // HasAMXTILE, HasAMXTRANSPOSE
+
+multiclass m_tcvtrowd2ps {
+ let Predicates = [HasAMXAVX512, In64BitMode] in {
phoebewang wrote:
Done, thanks!
https://github.com/llvm/ll
phoebewang wrote:
> Second, this scheme reduces the expected number of hash collisions within
> each arity, compared against the expected number of collisions (0.01383765)
> for the 32-bit hashing scheme that includes all arities. The table below
> shows the expected number of collisions for e
phoebewang wrote:
> @phoebewang and @lvwr I also noticed that there is this code in LLVM:
>
> https://github.com/llvm/llvm-project/blob/9ba6672b9f0e82a1f6d4100dc832c84447ea545c/llvm/lib/Transforms/Utils/ModuleUtils.cpp#L202-L214
>
> . As far as I can tell, this code is not triggered when I buil
https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/116257
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>From 587d0105e7724db0f35fc5c8179519fa6319e5c8 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Tue, 29 Oct 2024 22:29:25 +0800
Subject: [PATCH 1/6] [X86][AMX] Support AMX-AVX512
---
clang/docs/ReleaseNo
@@ -381,6 +389,8 @@ constexpr ProcInfo Processors[] = {
{ {"emeraldrapids"}, CK_Emeraldrapids, FEATURE_AVX512FP16,
FeaturesSapphireRapids, 'n', false },
// Clearwaterforest microarchitecture based processors.
{ {"clearwaterforest"}, CK_Lunarlake, FEATURE_AVX2,
FeaturesC
@@ -121,6 +121,7 @@ enum CPUKind {
CK_GraniterapidsD,
CK_Emeraldrapids,
CK_Clearwaterforest,
+ CK_DiamondRapids,
phoebewang wrote:
CK_Diamondrapids?
https://github.com/llvm/llvm-project/pull/113881
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@@ -1155,6 +1155,34 @@ def ProcessorFeatures {
list GNRDFeatures =
!listconcat(GNRFeatures, GNRDAdditionalFeatures);
+ // Diamond Rapids
+ list DMRAdditionalFeatures = [FeatureAVX10_2_512,
+ FeatureAMXCOMPLEX,
--
https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/113881
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https://github.com/phoebewang approved this pull request.
https://github.com/llvm/llvm-project/pull/116564
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@@ -208,10 +209,34 @@ void llvm::setKCFIType(Module &M, Function &F, StringRef
MangledType) {
std::string Type = MangledType.str();
if (M.getModuleFlag("cfi-normalize-integers"))
Type += ".normalized";
+
+ uint32_t OutHash = static_cast(llvm::xxHash64(Type));
+ auto
@@ -2139,9 +2139,9 @@ define <8 x i16> @pr59628_xmm(i16 %arg) {
; X86-LABEL: pr59628_xmm:
; X86: # %bb.0:
; X86-NEXT:movzwl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:vxorps %xmm0, %xmm0, %xmm0
+; X86-NEXT:vpxor %xmm0, %xmm0, %xmm0
; X86-NEXT:vpbroadcastw %eax, %
https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/108537
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LGTM.
https://github.com/llvm/llvm-project/pull/116181
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phoebewang wrote:
Yes, thanks for pointing out! Unfortunately, I met network problem when
committing the fix to GH. @MalaySanghi could you commit a fix instead?
https://github.com/llvm/llvm-project/pull/116181
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The network is recovered, fixed by
https://github.com/llvm/llvm-project/commit/9e1faa834173f57344a12b1a0a2f90b8e903c7bd
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@@ -208,10 +209,34 @@ void llvm::setKCFIType(Module &M, Function &F, StringRef
MangledType) {
std::string Type = MangledType.str();
if (M.getModuleFlag("cfi-normalize-integers"))
Type += ".normalized";
+
+ uint32_t OutHash = static_cast(llvm::xxHash64(Type));
+ auto
@@ -208,10 +209,34 @@ void llvm::setKCFIType(Module &M, Function &F, StringRef
MangledType) {
std::string Type = MangledType.str();
if (M.getModuleFlag("cfi-normalize-integers"))
Type += ".normalized";
+
+ uint32_t OutHash = static_cast(llvm::xxHash64(Type));
+ auto
@@ -4303,21 +4288,15 @@ void CodeGenModule::emitMultiVersionFunctions() {
continue;
llvm::Function *Func = createFunction(CurFD, I);
- StringRef Architecture;
Feats.clear();
- if (getTarget().getTriple().is
@@ -4303,21 +4288,15 @@ void CodeGenModule::emitMultiVersionFunctions() {
continue;
llvm::Function *Func = createFunction(CurFD, I);
- StringRef Architecture;
Feats.clear();
- if (getTarget().getTriple().is
@@ -4303,21 +4288,15 @@ void CodeGenModule::emitMultiVersionFunctions() {
continue;
llvm::Function *Func = createFunction(CurFD, I);
- StringRef Architecture;
Feats.clear();
- if (getTarget().getTriple().is
https://github.com/phoebewang converted_to_draft
https://github.com/llvm/llvm-project/pull/118603
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@@ -167,6 +167,8 @@ _mm512_maskz_mullo_epi64(__mmask8 __U, __m512i __A, __m512i
__B) {
(__v8di)_mm512_setzero_si512());
}
+#pragma float_control(push)
phoebewang wrote:
Thanks, this is just an experiment. Unfortun
https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/118603
Fixes: #118152
>From 6ec0b5b1e18e262c8eae131ce6f29866392494f2 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Wed, 4 Dec 2024 16:26:12 +0800
Subject: [PATCH] [X86] Do not apply fast-math to the logic int
https://github.com/phoebewang edited
https://github.com/llvm/llvm-project/pull/120670
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@@ -0,0 +1,23 @@
+// RUN: %clang %s -S --target=x86_64-unknown-linux-gnu -emit-llvm -O2
-march=x86-64-v3 -o - | FileCheck %s
phoebewang wrote:
Add a RUN line for BSD.
https://github.com/llvm/llvm-project/pull/120670
_
https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/120670
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phoebewang wrote:
This is a long existing problem and LLVM community doesn't make consensus about
it, see https://reviews.llvm.org/D53919
My point is the case of returning illegal vectors is not well defined by psABI,
and we have already warned this case in frontend. Considering the backward
@@ -2067,6 +2081,10 @@ void X86_64ABIInfo::classify(QualType Ty, uint64_t
OffsetBase, Class &Lo,
classify(I.getType(), Offset, FieldLo, FieldHi, isNamedArg);
Lo = merge(Lo, FieldLo);
Hi = merge(Hi, FieldHi);
+if (returnCXXRecordGreaterThan128InM
phoebewang wrote:
> @lvwr @maurer @rcvalle A gentle reminder to please review this PR.
@scottconstable You don't need explicit approvals from all reviewers. Let's
wait for 24 hours and land it if no objections.
https://github.com/llvm/llvm-project/pull/121070
__
https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/121070
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@@ -138,6 +142,12 @@ let Attributes = [Const, NoThrow,
RequiredVectorWidth<256>], Features = "avx" in
}
}
+// PRFCHW
+let Features = "prfchw", Header = "x86intrin.h", Attributes = [NoThrow, Const]
in {
+ def _m_prefetch : X86LibBuiltin<"void(void *)">;
ph
@@ -146,8 +146,13 @@ let Attributes = [Const, NoThrow,
RequiredVectorWidth<256>], Features = "avx" in
// current formulation is based on what was easiest to recognize from the
// pre-TableGen version.
-let Features = "mmx", Attributes = [NoThrow, Const] in {
- def _mm_prefet
phoebewang wrote:
> I proposed this at one point, and someone from Intel assured me that these
> long repetitive instructions and intrinsics are hand-maintained. It must be
> true at some level.
I believe it's not me, though I don't like the changes at the beginning either.
Anyway, with @chan
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/126390
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https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/121070
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phoebewang wrote:
/cherry-pick af522c5dd3a38cc5e11e8e62009d7dbe2cde2d86
https://github.com/llvm/llvm-project/pull/126627
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https://github.com/phoebewang milestoned
https://github.com/llvm/llvm-project/pull/126627
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https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/126627
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https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/124511
>From 806ed62f5c856ad15e5290da3b3b84ddcf9083d3 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Mon, 27 Jan 2025 14:13:22 +0800
Subject: [PATCH 1/2] [X86][AVX10] Disable m[no-]avx10.1 and switch
m[no-]avx
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