@@ -3744,6 +3744,12 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl
GD, unsigned BuiltinID,
return RValue::get(Result);
}
+ case Builtin::BI__builtin_selectvector: {
+return RValue::get(Builder.CreateSelect(EmitScalarExpr(E->getArg(2)),
@@ -3019,6 +3019,26 @@ C-style cast applied to each element of the first
argument.
Query for this feature with ``__has_builtin(__builtin_convertvector)``.
+``__builtin_selectvector``
+--
+
+``__builtin_selectvector`` is used to express generic vector
@@ -41,6 +41,22 @@ typedef long long __m512i_u
__attribute__((__vector_size__(64), __aligned__(1)))
typedef unsigned char __mmask8;
typedef unsigned short __mmask16;
+#ifdef __cplusplus
+typedef bool __vecmask2 __attribute__((__ext_vector_type__(2)));
+typedef bool __vecmask4
@@ -77,9 +77,9 @@ _mm512_cvtne2ps_pbh(__m512 __A, __m512 __B) {
///conversion of __B, and higher 256 bits come from conversion of __A.
static __inline__ __m512bh __DEFAULT_FN_ATTRS512
_mm512_mask_cvtne2ps_pbh(__m512bh __W, __mmask32 __U, __m512 __A, __m512 __B) {
- return
@@ -41,6 +41,22 @@ typedef long long __m512i_u
__attribute__((__vector_size__(64), __aligned__(1)))
typedef unsigned char __mmask8;
typedef unsigned short __mmask16;
+#ifdef __cplusplus
+typedef bool __vecmask2 __attribute__((__ext_vector_type__(2)));
+typedef bool __vecmask4
phoebewang wrote:
Please note it in release notes.
https://github.com/llvm/llvm-project/pull/92883
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@@ -9265,6 +9265,33 @@ multiclass avx512_fp28_s opc, string
OpcodeStr,X86VectorVTInfo _,
}
}
+multiclass avx512_fp28_s_ass opc, string OpcodeStr, X86VectorVTInfo _>
{
+ let ExeDomain = _.ExeDomain, hasNoSchedulingInfo = 1 in {
+ defm r : AVX512_maskable_scalar, Sched<[Wr
@@ -9325,6 +9345,43 @@ multiclass avx512_fp28_p_sae opc, string
OpcodeStr, X86VectorVTInfo _,
EVEX_B, Sched<[sched]>;
}
+multiclass avx512_fp28_p_ass opc, string OpcodeStr, X86VectorVTInfo _>
{
+ let ExeDomain = _.ExeDomain, hasNoSchedulingInfo = 1 i
@@ -9265,6 +9265,33 @@ multiclass avx512_fp28_s opc, string
OpcodeStr,X86VectorVTInfo _,
}
}
+multiclass avx512_fp28_s_ass opc, string OpcodeStr, X86VectorVTInfo _>
{
+ let ExeDomain = _.ExeDomain, hasNoSchedulingInfo = 1 in {
+ defm r : AVX512_maskable_scalar, Sched<[Wr
@@ -1,373 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
phoebewang wrote:
Why removing this?
https://github.com/llvm/llvm-project/pull/92883
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@@ -23,7 +23,7 @@
br i1 %6, label %4, label %5, !llvm.loop !9
}
- attributes #0 = { nofree norecurse nosync nounwind uwtable writeonly
mustprogress "frame-pointer"="none" "min-legal-vector-width"="0"
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target
@@ -268,30 +268,6 @@ define void @gather_qps(<8 x i64> %ind, <8 x float> %src,
ptr %base, ptr %stbuf)
ret void
}
-declare void @llvm.x86.avx512.gatherpf.qps.512(i8, <8 x i64>, ptr , i32, i32);
phoebewang wrote:
Surprise to see they were working without a
@@ -8,16 +8,12 @@ target triple = "x86_64-unknown-linux-gnu"
define dso_local i32 @main() local_unnamed_addr #0 !dbg !7 {
entry:
tail call void @llvm.prefetch(ptr inttoptr (i64 291 to ptr), i32 0, i32 0,
i32 1), !dbg !9
- tail call void @llvm.x86.avx512.gatherpf.dpd.512(i8
phoebewang wrote:
LGTM but I'd like @RKSimon to take a second look.
https://github.com/llvm/llvm-project/pull/92883
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https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/93136
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https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/101452
…nstructions
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965
>From 56b26bfaaa071dde226077531aaa46f4b671a815 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Sat, 27 Jul 2024 22:21:32 +0800
Subject
https://github.com/phoebewang edited
https://github.com/llvm/llvm-project/pull/101452
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@@ -1819,7 +1819,7 @@ const StringMap sys::getHostCPUFeatures() {
Features["avxvnniint16"] = HasLeaf7Subleaf1 && ((EDX >> 10) & 1) &&
HasAVXSave;
Features["prefetchi"] = HasLeaf7Subleaf1 && ((EDX >> 14) & 1);
Features["usermsr"] = HasLeaf7Subleaf1 && ((EDX >> 15) & 1);
@@ -0,0 +1,83 @@
+/*=== avx10_2niintrin.h - AVX10.2 new instruction intrinsics ---===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apach
@@ -162,6 +162,9 @@ bool SemaX86::CheckBuiltinRoundingOrSAE(unsigned BuiltinID,
CallExpr *TheCall) {
case X86::BI__builtin_ia32_mulps512:
case X86::BI__builtin_ia32_subpd512:
case X86::BI__builtin_ia32_subps512:
+ case X86::BI__builtin_ia32_vaddpd256_round:
@@ -0,0 +1,24 @@
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-unknown-unknown -target-feature +avx10.2-512 -emit-llvm -o - |
FileCheck %s
+
phoebewang wrote:
Added i386 test. `-flax-vector-conversions=none` is required. It
@@ -0,0 +1,105 @@
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-unknown-unknown -target-feature +avx10.2-256 -emit-llvm -o - |
FileCheck %s
+
phoebewang wrote:
Done.
https://github.com/llvm/llvm-project/pull/101452
@@ -257,6 +257,8 @@ X86_FEATURE_COMPAT(USERMSR, "usermsr",
0)
X86_FEATURE_COMPAT(AVX10_1, "avx10.1-256", 36)
X86_FEATURE_COMPAT(AVX10_1_512, "avx10.1-512", 37)
X86_FEATURE (ZU, "zu")
+X86_FEATURE_COMPAT(
@@ -111,9 +111,9 @@ class X86OpcodePrefixHelper {
// 0b11: F2
// EVEX (4 bytes)
- // +-+ +---+ ++
++
- // | 62h | | RXBR' | B'mmm | | W | | X' | pp | | z | L'L | b | v' | aaa
|
- // +-+ +---
@@ -111,9 +111,9 @@ class X86OpcodePrefixHelper {
// 0b11: F2
// EVEX (4 bytes)
- // +-+ +---+ ++
++
- // | 62h | | RXBR' | B'mmm | | W | | X' | pp | | z | L'L | b | v' | aaa
|
- // +-+ +---
@@ -131,7 +131,7 @@ class X86OpcodePrefixHelper {
// | RM (VR) | EVEX_X | EVEX_B | modrm.r/m | VR | Dest or Src |
// | RM (GPR) | EVEX_B' | EVEX_B | modrm.r/m | GPR | Dest or Src |
// | BASE | EVEX_B' | EVEX_B | modrm.r/m | GPR | MA |
- //
@@ -926,7 +951,9 @@ void DisassemblerTables::emitContextTable(raw_ostream &o,
unsigned &i) const {
else
o << "IC_VEX";
- if ((index & ATTR_EVEX) && (index & ATTR_EVEXL2))
+ if ((index & ATTR_EVEXB) && (index & ATTR_EVEXU))
+; // Ignore ATTR_VEX
@@ -575,6 +575,31 @@ static inline bool inheritsFrom(InstructionContext child,
case IC_EVEX_W_NF:
case IC_EVEX_W_B_NF:
return false;
+ case IC_EVEX_B_U:
+ case IC_EVEX_XS_B_U:
+ case IC_EVEX_XD_B_U:
+ case IC_EVEX_OPSIZE_B_U:
+ case IC_EVEX_W_B_U:
+ case IC_EVEX_W
@@ -1219,6 +1219,9 @@ static int getInstructionID(struct InternalInstruction
*insn,
attrMask |= ATTR_EVEXKZ;
if (bFromEVEX4of4(insn->vectorExtensionPrefix[3]))
attrMask |= ATTR_EVEXB;
+ if (x2FromEVEX3of4(insn->vectorExtensionPrefix[2]) &&
--
@@ -1219,6 +1219,9 @@ static int getInstructionID(struct InternalInstruction
*insn,
attrMask |= ATTR_EVEXKZ;
if (bFromEVEX4of4(insn->vectorExtensionPrefix[3]))
attrMask |= ATTR_EVEXB;
+ if (x2FromEVEX3of4(insn->vectorExtensionPrefix[2]) &&
+
@@ -111,9 +111,9 @@ class X86OpcodePrefixHelper {
// 0b11: F2
// EVEX (4 bytes)
- // +-+ +---+ ++
++
- // | 62h | | RXBR' | B'mmm | | W | | X' | pp | | z | L'L | b | v' | aaa
|
- // +-+ +---
@@ -0,0 +1,33 @@
+//===-- X86InstrAVX10.td - AVX10 Instruction Set ---*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/101452
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@@ -223,6 +227,10 @@ InstructionContext RecognizableInstr::insnContext() const {
insnContext = EVEX_KB_U(IC_EVEX_XD);
else if (OpPrefix == X86Local::PS)
insnContext = EVEX_KB_U(IC_EVEX);
+else {
+ errs() << "Instruction does not use
phoebewang wrote:
> Is this fail related to your PR?
>
> ```
> LLVM-Unit :: tools/llvm-cfi-verify/./CFIVerifyTests/2/49
> ```
I think so, investigating..
https://github.com/llvm/llvm-project/pull/101616
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@@ -978,8 +978,20 @@ static void getAvailableFeatures(unsigned ECX, unsigned
EDX, unsigned MaxLeaf,
bool HasLeaf24 =
MaxLevel >= 0x24 && !getX86CpuIDAndInfo(0x24, &EAX, &EBX, &ECX, &EDX);
- if (HasLeaf7Subleaf1 && ((EDX >> 19) & 1) && HasLeaf24 && ((EBX >> 18) & 1))
@@ -223,6 +227,10 @@ InstructionContext RecognizableInstr::insnContext() const {
insnContext = EVEX_KB_U(IC_EVEX_XD);
else if (OpPrefix == X86Local::PS)
insnContext = EVEX_KB_U(IC_EVEX);
+else {
+ errs() << "Instruction does not use
@@ -223,6 +227,10 @@ InstructionContext RecognizableInstr::insnContext() const {
insnContext = EVEX_KB_U(IC_EVEX_XD);
else if (OpPrefix == X86Local::PS)
insnContext = EVEX_KB_U(IC_EVEX);
+else {
+ errs() << "Instruction does not use
phoebewang wrote:
> > Is this fail related to your PR?
> > ```
> > LLVM-Unit :: tools/llvm-cfi-verify/./CFIVerifyTests/2/49
> > ```
>
> I think so, investigating..
This is an interesting issue. The problem is due to
https://github.com/llvm/llvm-project/blob/main/llvm/unittests/tools/llvm-cfi-v
@@ -223,6 +227,10 @@ InstructionContext RecognizableInstr::insnContext() const {
insnContext = EVEX_KB_U(IC_EVEX_XD);
else if (OpPrefix == X86Local::PS)
insnContext = EVEX_KB_U(IC_EVEX);
+else {
+ errs() << "Instruction does not use
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/101616
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@@ -0,0 +1,219 @@
+/*===--- avx10_2_512minmaxintrin.h - AVX10_2_512MINMAX intrinsics
+ *-===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-Li
@@ -2022,6 +2022,22 @@ TARGET_BUILTIN(__builtin_ia32_vsm4key4256,
"V8UiV8UiV8Ui", "nV:256:", "sm4")
TARGET_BUILTIN(__builtin_ia32_vsm4rnds4128, "V4UiV4UiV4Ui", "nV:128:", "sm4")
TARGET_BUILTIN(__builtin_ia32_vsm4rnds4256, "V8UiV8UiV8Ui", "nV:256:", "sm4")
+// AVX10-MINMAX
---
@@ -0,0 +1,219 @@
+/*===--- avx10_2_512minmaxintrin.h - AVX10_2_512MINMAX intrinsics
+ *-===
phoebewang wrote:
Make it one line.
https://github.com/llvm/llvm-project/pull/101598
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@@ -0,0 +1,188 @@
+/*===--- avx10_2minmaxintrin.h - AVX10_2MINMAX intrinsics
+ *-===
phoebewang wrote:
ditto.
https://github.com/llvm/llvm-project/pull/101598
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@@ -0,0 +1,219 @@
+/*===--- avx10_2_512minmaxintrin.h - AVX10_2_512MINMAX intrinsics
+ *-===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-Li
@@ -0,0 +1,210 @@
+// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding
-triple=x86_64 -target-feature +avx10.2-512 \
+// RUN: -emit-llvm -o - -Wno-invalid-feature-combination -Wall -Werror |
FileCheck %s
+// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffrees
@@ -2022,6 +2022,22 @@ TARGET_BUILTIN(__builtin_ia32_vsm4key4256,
"V8UiV8UiV8Ui", "nV:256:", "sm4")
TARGET_BUILTIN(__builtin_ia32_vsm4rnds4128, "V4UiV4UiV4Ui", "nV:128:", "sm4")
TARGET_BUILTIN(__builtin_ia32_vsm4rnds4256, "V8UiV8UiV8Ui", "nV:256:", "sm4")
+// AVX10-MINMAX
+TA
@@ -0,0 +1,648 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown
--show-mc-encoding -mattr=+avx10.2-512 | FileCheck %s --check-prefixes=X64
+; RUN: llc < %s -verify-machineinstr
@@ -0,0 +1,188 @@
+/*===--- avx10_2minmaxintrin.h - AVX10_2MINMAX intrinsics
+ *-===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Id
@@ -0,0 +1,219 @@
+/*===--- avx10_2_512minmaxintrin.h - AVX10_2_512MINMAX intrinsics
+ *-===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-Li
@@ -0,0 +1,244 @@
+// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding
-triple=x86_64 -target-feature +avx10.2-512 \
+// RUN: -emit-llvm -o - -Wno-invalid-feature-combination -Wall -Werror |
FileCheck %s
+// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffrees
@@ -388,12 +388,27 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
X86_INTRINSIC_DATA(avx_vpermilvar_ps, INTR_TYPE_2OP, X86ISD::VPERMILPV, 0),
X86_INTRINSIC_DATA(avx_vpermilvar_ps_256, INTR_TYPE_2OP, X86ISD::VPERMILPV,
0),
+X86_INTR
phoebewang wrote:
> ⚠️ C/C++ code formatter, clang-format found issues in your code. ⚠️
>
> You can test this locally with the following command:
> View the diff from clang-format here.
The clang-format seems problematic, and isn't compatible with previous version.
It looks like a bug to me.
@@ -785,9 +785,9 @@ void DisassemblerTables::emitModRMDecision(raw_ostream &o1,
raw_ostream &o2,
break;
}
- // We assume that the index can fit into uint16_t.
- assert(sEntryNumber < 65536U &&
- "Index into ModRMDecision is too large for uint16_t!");
+ // We
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/101825
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@@ -0,0 +1,210 @@
+// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding
-triple=x86_64 -target-feature +avx10.2-512 \
+// RUN: -emit-llvm -o - -Wno-invalid-feature-combination -Wall -Werror |
FileCheck %s
+// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffrees
https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/101598
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@@ -417,3 +417,173 @@ defm VMINMAXSH : avx10_minmax_scalar<"vminmaxsh",
v8f16x_info, X86vminmaxs, X86v
AVX512PSIi8Base, VEX_LIG, EVEX, , EVEX_CD8<16, CD8VT1>,
TA;
defm VMINMAXSS : avx10_minmax_scalar<"vminmaxss", v4f32x_info, X86vminmaxs,
X86vminmaxsSae>,
@@ -821,6 +821,88 @@ def X86vpdpbuuds : SDNode<"X86ISD::VPDPBUUDS", SDTVnni>;
def X86Vmpsadbw : SDNode<"X86ISD::MPSADBW", SDTX86PSADBW>;
+def SDTAVX10SATCVT_BF162I : SDTypeProfile<1, 1, [
+ SDTCVecEltisVT<0, i16>, SDTCVecEltisVT<1, bf16>
+]>;
+
+def SDTAVX10SATCVT_PH2I : SDT
@@ -417,3 +417,173 @@ defm VMINMAXSH : avx10_minmax_scalar<"vminmaxsh",
v8f16x_info, X86vminmaxs, X86v
AVX512PSIi8Base, VEX_LIG, EVEX, , EVEX_CD8<16, CD8VT1>,
TA;
defm VMINMAXSS : avx10_minmax_scalar<"vminmaxss", v4f32x_info, X86vminmaxs,
X86vminmaxsSae>,
@@ -149,7 +149,9 @@ set(x86_files
amxintrin.h
avx10_2_512minmaxintrin.h
avx10_2_512niintrin.h
+ avx10_2_512satcvtintrin.h
avx10_2minmaxintrin.h
+ avx10_2satcvtintrin.h
phoebewang wrote:
Alphabetical order.
https://github.com/llvm/llvm-project/pull/
@@ -821,6 +821,88 @@ def X86vpdpbuuds : SDNode<"X86ISD::VPDPBUUDS", SDTVnni>;
def X86Vmpsadbw : SDNode<"X86ISD::MPSADBW", SDTX86PSADBW>;
+def SDTAVX10SATCVT_BF162I : SDTypeProfile<1, 1, [
+ SDTCVecEltisVT<0, i16>, SDTCVecEltisVT<1, bf16>
+]>;
+
+def SDTAVX10SATCVT_PH2I : SDT
@@ -6898,3 +6898,115 @@ def int_x86_avx10_mask_vminmaxss_round :
ClangBuiltin<"__builtin_ia32_vminmaxss_
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty, llvm_i32_ty,
llvm_v4f32_ty, llvm_i8_ty, llvm_i32_ty],
[IntrNoMem, ImmArg>, ImmArg>]>;
}
@@ -313,7 +313,7 @@ def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
def v32f16_info : X86VectorVTInfo<32, f16, VR512, "ph">;
-def v32bf16_info: X86VectorVTInf
@@ -821,6 +821,88 @@ def X86vpdpbuuds : SDNode<"X86ISD::VPDPBUUDS", SDTVnni>;
def X86Vmpsadbw : SDNode<"X86ISD::MPSADBW", SDTX86PSADBW>;
+def SDTAVX10SATCVT_BF162I : SDTypeProfile<1, 1, [
+ SDTCVecEltisVT<0, i16>, SDTCVecEltisVT<1, bf16>
+]>;
+
+def SDTAVX10SATCVT_PH2I : SDT
@@ -821,6 +821,88 @@ def X86vpdpbuuds : SDNode<"X86ISD::VPDPBUUDS", SDTVnni>;
def X86Vmpsadbw : SDNode<"X86ISD::MPSADBW", SDTX86PSADBW>;
+def SDTAVX10SATCVT_BF162I : SDTypeProfile<1, 1, [
+ SDTCVecEltisVT<0, i16>, SDTCVecEltisVT<1, bf16>
+]>;
+
+def SDTAVX10SATCVT_PH2I : SDT
@@ -417,3 +417,173 @@ defm VMINMAXSH : avx10_minmax_scalar<"vminmaxsh",
v8f16x_info, X86vminmaxs, X86v
AVX512PSIi8Base, VEX_LIG, EVEX, , EVEX_CD8<16, CD8VT1>,
TA;
defm VMINMAXSS : avx10_minmax_scalar<"vminmaxss", v4f32x_info, X86vminmaxs,
X86vminmaxsSae>,
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/101783
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@@ -417,3 +417,173 @@ defm VMINMAXSH : avx10_minmax_scalar<"vminmaxsh",
v8f16x_info, X86vminmaxs, X86v
AVX512PSIi8Base, VEX_LIG, EVEX, , EVEX_CD8<16, CD8VT1>,
TA;
defm VMINMAXSS : avx10_minmax_scalar<"vminmaxss", v4f32x_info, X86vminmaxs,
X86vminmaxsSae>,
@@ -821,6 +821,88 @@ def X86vpdpbuuds : SDNode<"X86ISD::VPDPBUUDS", SDTVnni>;
def X86Vmpsadbw : SDNode<"X86ISD::MPSADBW", SDTX86PSADBW>;
+def SDTAVX10SATCVT_BF162I : SDTypeProfile<1, 1, [
+ SDTCVecEltisVT<0, i16>, SDTCVecEltisVT<1, bf16>
+]>;
+
+def SDTAVX10SATCVT_PH2I : SDT
@@ -821,6 +821,88 @@ def X86vpdpbuuds : SDNode<"X86ISD::VPDPBUUDS", SDTVnni>;
def X86Vmpsadbw : SDNode<"X86ISD::MPSADBW", SDTX86PSADBW>;
+def SDTAVX10SATCVT_BF162I : SDTypeProfile<1, 1, [
+ SDTCVecEltisVT<0, i16>, SDTCVecEltisVT<1, bf16>
+]>;
+
+def SDTAVX10SATCVT_PH2I : SDT
@@ -0,0 +1,327 @@
+/*===-- avx10_2_512satcvtintrin.h - AVX10_2_512SATCVT intrinsics ---===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apac
@@ -0,0 +1,198 @@
+// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding
-triple=x86_64 -target-feature +avx10.2-512 \
+// RUN: -emit-llvm -Wall -Werror -verify
+// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding
-triple=i386 -target-feature +avx10.2
https://github.com/phoebewang approved this pull request.
LGTM with one nit.
https://github.com/llvm/llvm-project/pull/101599
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@@ -417,3 +417,168 @@ defm VMINMAXSH : avx10_minmax_scalar<"vminmaxsh",
v8f16x_info, X86vminmaxs, X86v
AVX512PSIi8Base, VEX_LIG, EVEX, , EVEX_CD8<16, CD8VT1>,
TA;
defm VMINMAXSS : avx10_minmax_scalar<"vminmaxss", v4f32x_info, X86vminmaxs,
X86vminmaxsSae>,
https://github.com/phoebewang edited
https://github.com/llvm/llvm-project/pull/101599
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Author: Joao Moreira
Date: 2022-01-21T10:55:34+08:00
New Revision: 82af95029ec947fed8b9c516f04d4f217bd87930
URL:
https://github.com/llvm/llvm-project/commit/82af95029ec947fed8b9c516f04d4f217bd87930
DIFF:
https://github.com/llvm/llvm-project/commit/82af95029ec947fed8b9c516f04d4f217bd87930.diff
Author: Phoebe Wang
Date: 2022-01-23T09:58:46+08:00
New Revision: 37d1d02200b9472082304c191f396f0489d00e05
URL:
https://github.com/llvm/llvm-project/commit/37d1d02200b9472082304c191f396f0489d00e05
DIFF:
https://github.com/llvm/llvm-project/commit/37d1d02200b9472082304c191f396f0489d00e05.diff
L
Author: Phoebe Wang
Date: 2022-03-08T11:19:05+08:00
New Revision: 4de9a752d6affb7427d53c50bb64c94c3014b3f0
URL:
https://github.com/llvm/llvm-project/commit/4de9a752d6affb7427d53c50bb64c94c3014b3f0
DIFF:
https://github.com/llvm/llvm-project/commit/4de9a752d6affb7427d53c50bb64c94c3014b3f0.diff
L
Author: Phoebe Wang
Date: 2022-01-12T17:50:37+08:00
New Revision: 1bb0caf561688681be67cc91560348c9e43fcbf3
URL:
https://github.com/llvm/llvm-project/commit/1bb0caf561688681be67cc91560348c9e43fcbf3
DIFF:
https://github.com/llvm/llvm-project/commit/1bb0caf561688681be67cc91560348c9e43fcbf3.diff
L
Author: Phoebe Wang
Date: 2022-01-15T10:54:38+08:00
New Revision: f63a805a4e9924002a9533b335ab29a8b5c7a9ac
URL:
https://github.com/llvm/llvm-project/commit/f63a805a4e9924002a9533b335ab29a8b5c7a9ac
DIFF:
https://github.com/llvm/llvm-project/commit/f63a805a4e9924002a9533b335ab29a8b5c7a9ac.diff
L
Author: Phoebe Wang
Date: 2021-12-08T09:50:26+08:00
New Revision: 4a2c827b178f89d4cdeb56153d9440ad4ba786a3
URL:
https://github.com/llvm/llvm-project/commit/4a2c827b178f89d4cdeb56153d9440ad4ba786a3
DIFF:
https://github.com/llvm/llvm-project/commit/4a2c827b178f89d4cdeb56153d9440ad4ba786a3.diff
L
Author: Phoebe Wang
Date: 2021-12-10T09:29:38+08:00
New Revision: d7c07f60b35f901f5bd9153b11807124a9bdde60
URL:
https://github.com/llvm/llvm-project/commit/d7c07f60b35f901f5bd9153b11807124a9bdde60
DIFF:
https://github.com/llvm/llvm-project/commit/d7c07f60b35f901f5bd9153b11807124a9bdde60.diff
L
Author: Phoebe Wang
Date: 2021-12-10T10:31:09+08:00
New Revision: 925ec98d000a9df7749e93e8831282cbbb5839b2
URL:
https://github.com/llvm/llvm-project/commit/925ec98d000a9df7749e93e8831282cbbb5839b2
DIFF:
https://github.com/llvm/llvm-project/commit/925ec98d000a9df7749e93e8831282cbbb5839b2.diff
L
Author: Phoebe Wang
Date: 2021-12-23T11:46:03+08:00
New Revision: 682d01a1c1c52bd95d3d06267d6017395770256b
URL:
https://github.com/llvm/llvm-project/commit/682d01a1c1c52bd95d3d06267d6017395770256b
DIFF:
https://github.com/llvm/llvm-project/commit/682d01a1c1c52bd95d3d06267d6017395770256b.diff
L
Author: Phoebe Wang
Date: 2021-12-23T12:44:33+08:00
New Revision: a954558e878ed9e97e99036229e99af8c6b6c881
URL:
https://github.com/llvm/llvm-project/commit/a954558e878ed9e97e99036229e99af8c6b6c881
DIFF:
https://github.com/llvm/llvm-project/commit/a954558e878ed9e97e99036229e99af8c6b6c881.diff
L
Author: Phoebe Wang
Date: 2021-12-24T17:42:51+08:00
New Revision: 24c68ea1eb4fc0d0e782424ddb02da9e8c53ddf5
URL:
https://github.com/llvm/llvm-project/commit/24c68ea1eb4fc0d0e782424ddb02da9e8c53ddf5
DIFF:
https://github.com/llvm/llvm-project/commit/24c68ea1eb4fc0d0e782424ddb02da9e8c53ddf5.diff
L
https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/104781
E.g.: https://godbolt.org/z/G8zK5svjK
Based on Evgenii's work.
>From 9a0c15c9b0bb3d1df3902dcfe62d659803cba516 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Mon, 19 Aug 2024 22:09:13 +0800
Subject: [PA
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/104781
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https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/101600
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@@ -0,0 +1,105 @@
+// RUN: %clang_cc1 -triple i386-unknown-unknown -target-feature +mmx \
+// RUN: -target-feature +sse2 -O0 -emit-llvm %s -o - | FileCheck %s
+
+// Test that mmx/sse2 shift intrinsics map to the expected builtins.
+
+// Don't include mm_malloc.h, it's system spec
@@ -0,0 +1,387 @@
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -fsyntax-only \
phoebewang wrote:
Move it to clang/test/CodeGen/X86?
https://github.com/llvm/llvm-project/pull/105852
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@@ -21,10 +21,29 @@ typedef int __v2si __attribute__((__vector_size__(8)));
typedef short __v4hi __attribute__((__vector_size__(8)));
typedef char __v8qi __attribute__((__vector_size__(8)));
+/* Unsigned types */
+typedef unsigned long long __v1du __attribute__ ((__vector_size
@@ -2539,9 +2536,8 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS
_mm_sub_epi32(__m128i __a,
///A 64-bit integer vector containing the subtrahend.
/// \returns A 64-bit integer vector containing the difference of the values in
///the operands.
-static __inline__ __m64
@@ -21,10 +21,29 @@ typedef int __v2si __attribute__((__vector_size__(8)));
typedef short __v4hi __attribute__((__vector_size__(8)));
typedef char __v8qi __attribute__((__vector_size__(8)));
+/* Unsigned types */
+typedef unsigned long long __v1du __attribute__ ((__vector_size
@@ -337,10 +363,10 @@ _mm_unpacklo_pi32(__m64 __m1, __m64 __m2)
///A 64-bit integer vector of [8 x i8].
/// \returns A 64-bit integer vector of [8 x i8] containing the sums of both
///parameters.
-static __inline__ __m64 __DEFAULT_FN_ATTRS
+static __inline__ __m64 __DEF
@@ -242,10 +243,11 @@ _mm_hadd_epi32(__m128i __a, __m128i __b)
///destination.
/// \returns A 64-bit vector of [4 x i16] containing the horizontal sums of
both
///operands.
-static __inline__ __m64 __DEFAULT_FN_ATTRS_MMX
+static __inline__ __m64 __DEFAULT_FN_ATTRS
_mm
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