https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/82422
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https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/97525
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@@ -1710,15 +1710,17 @@ VendorSignatures getVendorSignature(unsigned *MaxLeaf) {
#if defined(__i386__) || defined(_M_IX86) || \
defined(__x86_64__) || defined(_M_X64)
-bool sys::getHostCPUFeatures(StringMap &Features) {
+std::optional> sys::getHostCPUFeatures() {
unsign
https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/97939
This is how MSVC handles it. https://godbolt.org/z/Eav3vx7cd
>From cf19ec8d705434ca6d989a72069dba1040c360ca Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Sun, 7 Jul 2024 13:14:59 +0800
Subject: [PATCH] [X8
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/97939
>From cf19ec8d705434ca6d989a72069dba1040c360ca Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Sun, 7 Jul 2024 13:14:59 +0800
Subject: [PATCH 1/2] [X86][vectorcall] Do not consume register for indirect
retur
phoebewang wrote:
> It looks like MSVC also applies this rule to fastcall.
Good catch, done!
> Maybe put a boolean in the "state" to try to group together the code for
> specific conventions, instead of directly checking the CC.
There are 3 special conventions here: vectorcall, fastcall and
phoebewang wrote:
> I meant, at the beginning of X86_32ABIInfo::computeInfo there's a chain of if
> statements that set up the properties of different calling conventions, and
> maybe some bits could be set there. If you don't think that makes sense,
> though, it's fine.
Thanks @efriedma-quic
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/97939
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@@ -2122,6 +2122,36 @@ TARGET_BUILTIN(__builtin_ia32_vpdpwuud256,
"V8iV8iV8iV8i", "nV:256:", "avxvnniin
TARGET_BUILTIN(__builtin_ia32_vpdpwuuds128, "V4iV4iV4iV4i", "nV:128:",
"avxvnniint16|avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vpdpwuuds256, "V8iV8iV8iV8i", "nV:256:",
"a
@@ -0,0 +1,447 @@
+/*===--- avx10_2satcvtdsintrin.h - AVX512SATCVTDS intrinsics
===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Ap
@@ -0,0 +1,183 @@
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=i386-unknown-unknown -target-feature +avx10.2-512 -emit-llvm -o - |
FileCheck %s
+
+#include
+#include
+
+int test_mm_cvttssd_i32(__m128d __A) {
+ // CHECK-LABEL: @test_mm_cvttssd_i3
@@ -0,0 +1,183 @@
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=i386-unknown-unknown -target-feature +avx10.2-512 -emit-llvm -o - |
FileCheck %s
phoebewang wrote:
Remoe `-unknown-unknown` and add `-triple=x86_64`
https://github.co
@@ -0,0 +1,220 @@
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=i386-unknown-unknown -target-feature +avx10.2-256 -emit-llvm -o - |
FileCheck %s
phoebewang wrote:
Remoe `-unknown-unknown` and add `-triple=x86_64`
https://github.co
@@ -0,0 +1,443 @@
+/*===--- avx10_2satcvtdsintrin.h - AVX512SATCVTDS intrinsics
===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Ap
@@ -0,0 +1,443 @@
+/*===--- avx10_2satcvtdsintrin.h - AVX512SATCVTDS intrinsics
===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Ap
@@ -0,0 +1,443 @@
+/*===--- avx10_2satcvtdsintrin.h - AVX512SATCVTDS intrinsics
===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Ap
@@ -625,6 +625,317 @@ defm VCVTTPS2IUBS : avx10_sat_cvt_base<0x6a,
"vcvttps2iubs", SchedWriteVecIMul,
X86vcvttp2iubsSAE>,
AVX512PDIi8Base, T_MAP5, EVEX_CD8<32, CD8VF>;
+//---
@@ -625,6 +625,317 @@ defm VCVTTPS2IUBS : avx10_sat_cvt_base<0x6a,
"vcvttps2iubs", SchedWriteVecIMul,
X86vcvttp2iubsSAE>,
AVX512PDIi8Base, T_MAP5, EVEX_CD8<32, CD8VF>;
+//---
@@ -625,6 +625,317 @@ defm VCVTTPS2IUBS : avx10_sat_cvt_base<0x6a,
"vcvttps2iubs", SchedWriteVecIMul,
X86vcvttp2iubsSAE>,
AVX512PDIi8Base, T_MAP5, EVEX_CD8<32, CD8VF>;
+//---
@@ -625,6 +625,317 @@ defm VCVTTPS2IUBS : avx10_sat_cvt_base<0x6a,
"vcvttps2iubs", SchedWriteVecIMul,
X86vcvttp2iubsSAE>,
AVX512PDIi8Base, T_MAP5, EVEX_CD8<32, CD8VF>;
+//---
@@ -625,6 +625,317 @@ defm VCVTTPS2IUBS : avx10_sat_cvt_base<0x6a,
"vcvttps2iubs", SchedWriteVecIMul,
X86vcvttp2iubsSAE>,
AVX512PDIi8Base, T_MAP5, EVEX_CD8<32, CD8VF>;
+//---
@@ -625,6 +625,317 @@ defm VCVTTPS2IUBS : avx10_sat_cvt_base<0x6a,
"vcvttps2iubs", SchedWriteVecIMul,
X86vcvttp2iubsSAE>,
AVX512PDIi8Base, T_MAP5, EVEX_CD8<32, CD8VF>;
+//---
@@ -0,0 +1,526 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 3
+; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown
--show-mc-encoding -mattr=+avx10.2-512 | FileCheck %s --check-prefixes=CHECK,X64
+; RUN:
@@ -0,0 +1,526 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 3
+; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown
--show-mc-encoding -mattr=+avx10.2-512 | FileCheck %s --check-prefixes=CHECK,X64
+; RUN:
@@ -5520,6 +5520,106 @@ let TargetPrefix = "x86" in {
[IntrNoMem, ImmArg>]>;
}
+// conversion with saturation
+let TargetPrefix = "x86" in {
+ def int_x86_avx512_vcvttss2sis :
ClangBuiltin<"__builtin_ia32_vcvttss2sis32">,
phoebewa
@@ -0,0 +1,443 @@
+/*===--- avx10_2satcvtdsintrin.h - AVX512SATCVTDS intrinsics
===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Ap
@@ -0,0 +1,478 @@
+/*===--- avx10_2satcvtdsintrin.h - AVX512SATCVTDS intrinsics
===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Ap
https://github.com/phoebewang edited
https://github.com/llvm/llvm-project/pull/102592
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@@ -0,0 +1,297 @@
+/*===- avx10_2_512satcvtdsintrin.h - AVX10_2_512SATCVTDS intrinsics ===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apac
https://github.com/phoebewang approved this pull request.
LGTM with one nit.
https://github.com/llvm/llvm-project/pull/102592
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@@ -2122,6 +2122,36 @@ TARGET_BUILTIN(__builtin_ia32_vpdpwuud256,
"V8iV8iV8iV8i", "nV:256:", "avxvnniin
TARGET_BUILTIN(__builtin_ia32_vpdpwuuds128, "V4iV4iV4iV4i", "nV:128:",
"avxvnniint16|avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vpdpwuuds256, "V8iV8iV8iV8i", "nV:256:",
"a
https://github.com/phoebewang deleted
https://github.com/llvm/llvm-project/pull/102592
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@@ -324,7 +324,14 @@ X86TargetLowering::X86TargetLowering(const
X86TargetMachine &TM,
}
}
- if (Subtarget.hasSSE2()) {
+ if (Subtarget.hasAVX10_2() || Subtarget.hasAVX10_2_512()) {
+setOperationAction(ISD::FP_TO_UINT_SAT, MVT::i32, Legal);
+setOperationAction(
@@ -150,9 +150,11 @@ set(x86_files
avx10_2_512minmaxintrin.h
avx10_2_512niintrin.h
avx10_2_512satcvtintrin.h
+ avx10_2_512satcvtdsintrin.h
phoebewang wrote:
Alphanumeric order.
https://github.com/llvm/llvm-project/pull/102592
__
@@ -99,6 +99,12 @@ TARGET_BUILTIN(__builtin_ia32_vcvttsh2si64, "OiV8xIi",
"ncV:128:", "avx512fp16")
TARGET_BUILTIN(__builtin_ia32_vcvttsh2usi64, "UOiV8xIi", "ncV:128:",
"avx512fp16")
TARGET_BUILTIN(__builtin_ia32_directstore_u64, "vULi*ULi", "n", "movdiri")
+// AVX10.2 SATCV
@@ -0,0 +1,453 @@
+/*===--- avx10_2satcvtdsintrin.h - AVX512SATCVTDS intrinsics
===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Ap
@@ -2122,6 +2122,36 @@ TARGET_BUILTIN(__builtin_ia32_vpdpwuud256,
"V8iV8iV8iV8i", "nV:256:", "avxvnniin
TARGET_BUILTIN(__builtin_ia32_vpdpwuuds128, "V4iV4iV4iV4i", "nV:128:",
"avxvnniint16|avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vpdpwuuds256, "V8iV8iV8iV8i", "nV:256:",
"a
@@ -0,0 +1,184 @@
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-unknown-unknown -target-feature +avx10.2-512 -emit-llvm -o - |
FileCheck %s
+
+#include
+#include
+
+long long test_mm_cvttssd_si64(__m128d __A) {
+ // CHECK-LABEL: @test_mm_c
@@ -150,9 +150,11 @@ set(x86_files
avx10_2_512minmaxintrin.h
avx10_2_512niintrin.h
avx10_2_512satcvtintrin.h
+ avx10_2_512satcvtdsintrin.h
avx10_2minmaxintrin.h
avx10_2niintrin.h
avx10_2satcvtintrin.h
+ avx10_2satcvtdsintrin.h
phoebewang wrote:
@@ -0,0 +1,453 @@
+/*===--- avx10_2satcvtdsintrin.h - AVX512SATCVTDS intrinsics
===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Ap
@@ -0,0 +1,302 @@
+/*===- avx10_2_512satcvtdsintrin.h - AVX10_2_512SATCVTDS intrinsics ===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apac
@@ -324,7 +324,14 @@ X86TargetLowering::X86TargetLowering(const
X86TargetMachine &TM,
}
}
- if (Subtarget.hasSSE2()) {
+ if (Subtarget.hasAVX10_2() || Subtarget.hasAVX10_2_512()) {
phoebewang wrote:
Check `Subtarget.hasAVX10_2()` is enough.
https://
@@ -0,0 +1,453 @@
+/*===--- avx10_2satcvtdsintrin.h - AVX512SATCVTDS intrinsics
===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Ap
@@ -0,0 +1,115 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-linux -mattr=+avx10.2-256 | FileCheck %s
--check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-linux -mattr=+avx10.2-256 | FileCheck %s
--check-prefix=X6
https://github.com/phoebewang commented:
Just found I didn't publish the comments..
https://github.com/llvm/llvm-project/pull/101600
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@@ -624,3 +624,440 @@ defm VCVTTPS2IUBS : avx10_sat_cvt_base<0x6a,
"vcvttps2iubs", SchedWriteVecIMul,
avx512vl_i32_info, avx512vl_f32_info,
X86vcvttp2iubsSAE>,
AVX512PDIi8Base, T_MA
@@ -0,0 +1,286 @@
+/*===- avx10_2_512convertintrin.h - AVX10_2_512CONVERT -===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apac
@@ -0,0 +1,286 @@
+/*===- avx10_2_512convertintrin.h - AVX10_2_512CONVERT -===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apac
@@ -624,3 +624,440 @@ defm VCVTTPS2IUBS : avx10_sat_cvt_base<0x6a,
"vcvttps2iubs", SchedWriteVecIMul,
avx512vl_i32_info, avx512vl_f32_info,
X86vcvttp2iubsSAE>,
AVX512PDIi8Base, T_MA
@@ -0,0 +1,286 @@
+/*===- avx10_2_512convertintrin.h - AVX10_2_512CONVERT -===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apac
@@ -624,3 +624,440 @@ defm VCVTTPS2IUBS : avx10_sat_cvt_base<0x6a,
"vcvttps2iubs", SchedWriteVecIMul,
avx512vl_i32_info, avx512vl_f32_info,
X86vcvttp2iubsSAE>,
AVX512PDIi8Base, T_MA
@@ -2217,6 +2217,50 @@ TARGET_BUILTIN(__builtin_ia32_vcvttps2ibs512_mask,
"V16UiV16fV16UiUsIi", "nV:512
TARGET_BUILTIN(__builtin_ia32_vcvttps2iubs128_mask, "V4UiV4fV4UiUc",
"nV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvttps2iubs256_mask, "V8UiV8fV8UiUcIi",
"nV:25
@@ -0,0 +1,286 @@
+/*===- avx10_2_512convertintrin.h - AVX10_2_512CONVERT -===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apac
@@ -1185,6 +1189,9 @@ Currently, only the following parameter attributes are
defined:
value should be sign-extended to the extent required by the target's
ABI (which is usually 32-bits) by the caller (for a parameter) or
the callee (for a return value).
+``noext``
@@ -1185,6 +1189,9 @@ Currently, only the following parameter attributes are
defined:
value should be sign-extended to the extent required by the target's
ABI (which is usually 32-bits) by the caller (for a parameter) or
the callee (for a return value).
+``noext``
@@ -847,6 +847,91 @@ def X86vcvttp2iubs : SDNode<"X86ISD::CVTTP2IUBS",
SDTFloatToInt>;
def X86vcvttp2ibsSAE : SDNode<"X86ISD::CVTTP2IBS_SAE", SDTFloatToInt>;
def X86vcvttp2iubsSAE : SDNode<"X86ISD::CVTTP2IUBS_SAE", SDTFloatToInt>;
+def SDTAVX10CONVERT_I82F16 : SDTypeProfile<
@@ -847,6 +847,91 @@ def X86vcvttp2iubs : SDNode<"X86ISD::CVTTP2IUBS",
SDTFloatToInt>;
def X86vcvttp2ibsSAE : SDNode<"X86ISD::CVTTP2IBS_SAE", SDTFloatToInt>;
def X86vcvttp2iubsSAE : SDNode<"X86ISD::CVTTP2IUBS_SAE", SDTFloatToInt>;
+def SDTAVX10CONVERT_I82F16 : SDTypeProfile<
@@ -7089,3 +7089,133 @@ def int_x86_avx10_mask_vcvttps2iubs512 :
ClangBuiltin<"__builtin_ia32_vcvttps2iu
DefaultAttrsIntrinsic<[llvm_v16i32_ty], [llvm_v16f32_ty,
llvm_v16i32_ty, llvm_i16_ty, llvm_i32_ty],
[IntrNoMem, ImmArg>]>;
}
+
+//===
@@ -847,6 +847,91 @@ def X86vcvttp2iubs : SDNode<"X86ISD::CVTTP2IUBS",
SDTFloatToInt>;
def X86vcvttp2ibsSAE : SDNode<"X86ISD::CVTTP2IBS_SAE", SDTFloatToInt>;
def X86vcvttp2iubsSAE : SDNode<"X86ISD::CVTTP2IUBS_SAE", SDTFloatToInt>;
+def SDTAVX10CONVERT_I82F16 : SDTypeProfile<
@@ -847,6 +847,91 @@ def X86vcvttp2iubs : SDNode<"X86ISD::CVTTP2IUBS",
SDTFloatToInt>;
def X86vcvttp2ibsSAE : SDNode<"X86ISD::CVTTP2IBS_SAE", SDTFloatToInt>;
def X86vcvttp2iubsSAE : SDNode<"X86ISD::CVTTP2IUBS_SAE", SDTFloatToInt>;
+def SDTAVX10CONVERT_I82F16 : SDTypeProfile<
@@ -624,3 +624,328 @@ defm VCVTTPS2IUBS : avx10_sat_cvt_base<0x6a,
"vcvttps2iubs", SchedWriteVecIMul,
avx512vl_i32_info, avx512vl_f32_info,
X86vcvttp2iubsSAE>,
AVX512PDIi8Base, T_MA
@@ -617,7 +617,7 @@ constexpr FeatureBitset ImpliedFeaturesAVX10_1 =
FeatureAVX512CD | FeatureAVX512VBMI | FeatureAVX512IFMA |
FeatureAVX512VNNI | FeatureAVX512BF16 | FeatureAVX512VPOPCNTDQ |
FeatureAVX512VBMI2 | FeatureAVX512BITALG | FeatureVAES | FeatureVPCLMULQDQ
@@ -847,6 +847,91 @@ def X86vcvttp2iubs : SDNode<"X86ISD::CVTTP2IUBS",
SDTFloatToInt>;
def X86vcvttp2ibsSAE : SDNode<"X86ISD::CVTTP2IBS_SAE", SDTFloatToInt>;
def X86vcvttp2iubsSAE : SDNode<"X86ISD::CVTTP2IUBS_SAE", SDTFloatToInt>;
+def SDTAVX10CONVERT_I82F16 : SDTypeProfile<
Author: Phoebe Wang
Date: 2024-04-03T16:10:19+08:00
New Revision: cd7517859eef14d8b38cec2d52c0625a58c645a2
URL:
https://github.com/llvm/llvm-project/commit/cd7517859eef14d8b38cec2d52c0625a58c645a2
DIFF:
https://github.com/llvm/llvm-project/commit/cd7517859eef14d8b38cec2d52c0625a58c645a2.diff
L
https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/87987
This relands #87149.
The previous commit exposed failures on some targets. The reason is only a few
targets support COFF ObjectFormatType on Windows:
https://github.com/llvm/llvm-project/blob/main/llvm/lib/T
https://github.com/phoebewang edited
https://github.com/llvm/llvm-project/pull/87987
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https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/88101
Fixes #62449
>From 66c4383e58cab7cf893edfa3f3507be166116fa6 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Tue, 9 Apr 2024 16:08:55 +0800
Subject: [PATCH] [SEH] Ignore async exception flag when the environm
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/87987
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Author: Phoebe Wang
Date: 2024-04-10T14:40:07+08:00
New Revision: 299b636a8f1c9cb2382f9dce4cdf6ec6330a79c6
URL:
https://github.com/llvm/llvm-project/commit/299b636a8f1c9cb2382f9dce4cdf6ec6330a79c6
DIFF:
https://github.com/llvm/llvm-project/commit/299b636a8f1c9cb2382f9dce4cdf6ec6330a79c6.diff
L
https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/88245
This is a second try to reland https://github.com/llvm/llvm-project/pull/87149.
The previous commit exposed failures on some targets. The reason is only a few
targets support COFF ObjectFormatType on Windows:
https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/95890
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https://github.com/llvm/llvm-project/pull/93774
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https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/93774
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@@ -63,6 +63,91 @@ unsigned __int64 test__emulu(unsigned int a, unsigned int b)
{
// CHECK: [[RES:%[0-9]+]] = mul nuw i64 [[Y]], [[X]]
// CHECK: ret i64 [[RES]]
+//
+// CHECK-I386-LABEL: define dso_local noundef i32 @test_outp(
+// CHECK-I386-SAME: i16 noundef zeroext [[PORT:
@@ -63,6 +63,91 @@ unsigned __int64 test__emulu(unsigned int a, unsigned int b)
{
// CHECK: [[RES:%[0-9]+]] = mul nuw i64 [[Y]], [[X]]
// CHECK: ret i64 [[RES]]
+//
+// CHECK-I386-LABEL: define dso_local noundef i32 @test_outp(
+// CHECK-I386-SAME: i16 noundef zeroext [[PORT:
@@ -63,6 +63,91 @@ unsigned __int64 test__emulu(unsigned int a, unsigned int b)
{
// CHECK: [[RES:%[0-9]+]] = mul nuw i64 [[Y]], [[X]]
// CHECK: ret i64 [[RES]]
+//
+// CHECK-I386-LABEL: define dso_local noundef i32 @test_outp(
+// CHECK-I386-SAME: i16 noundef zeroext [[PORT:
@@ -348,6 +348,20 @@ static inline unsigned long _inpd(unsigned short port) {
return ret;
}
+static inline int _outp(unsigned short port, int data) {
+ __asm__ volatile("outb %b0, %w1" : : "a"(data), "Nd"(port));
+ return data;
phoebewang wrote:
Return th
@@ -63,6 +63,91 @@ unsigned __int64 test__emulu(unsigned int a, unsigned int b)
{
// CHECK: [[RES:%[0-9]+]] = mul nuw i64 [[Y]], [[X]]
// CHECK: ret i64 [[RES]]
+//
+// CHECK-I386-LABEL: define dso_local noundef i32 @test_outp(
+// CHECK-I386-SAME: i16 noundef zeroext [[PORT:
@@ -63,6 +63,91 @@ unsigned __int64 test__emulu(unsigned int a, unsigned int b)
{
// CHECK: [[RES:%[0-9]+]] = mul nuw i64 [[Y]], [[X]]
// CHECK: ret i64 [[RES]]
+//
+// CHECK-I386-LABEL: define dso_local noundef i32 @test_outp(
+// CHECK-I386-SAME: i16 noundef zeroext [[PORT:
@@ -348,6 +348,20 @@ static inline unsigned long _inpd(unsigned short port) {
return ret;
}
+static inline int _outp(unsigned short port, int data) {
phoebewang wrote:
Can we change it to `__outbyte` instead?
https://github.com/llvm/llvm-project/pull/93774
https://github.com/phoebewang edited
https://github.com/llvm/llvm-project/pull/93774
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@@ -330,24 +330,35 @@ static __inline__ void __DEFAULT_FN_ATTRS __halt(void) {
__asm__ volatile("hlt");
}
-static inline int _inp(unsigned short port) {
- int ret;
+static inline unsigned char __inbyte(unsigned short port) {
+ unsigned char ret;
__asm__ volatile("inb %w
https://github.com/phoebewang commented:
LGTM.
https://github.com/llvm/llvm-project/pull/93774
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https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/93774
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https://github.com/phoebewang commented:
This is much like what we have removed for KNL intrinsics/instructions., so
general LGTM. But I'd like Simon to sign off given I'm not familar with 3DNOW
instructions.
https://github.com/llvm/llvm-project/pull/96246
_
@@ -329,6 +329,26 @@ static __inline__ void __DEFAULT_FN_ATTRS __stosq(unsigned
__int64 *__dst,
static __inline__ void __DEFAULT_FN_ATTRS __halt(void) {
__asm__ volatile("hlt");
}
+
+static __inline__ int __DEFAULT_FN_ATTRS _outp(unsigned short port, int data) {
+ __asm__ v
@@ -329,6 +329,26 @@ static __inline__ void __DEFAULT_FN_ATTRS __stosq(unsigned
__int64 *__dst,
static __inline__ void __DEFAULT_FN_ATTRS __halt(void) {
__asm__ volatile("hlt");
}
+
+static __inline__ int __DEFAULT_FN_ATTRS _outp(unsigned short port, int data) {
+ __asm__ v
@@ -63,6 +63,82 @@ unsigned __int64 test__emulu(unsigned int a, unsigned int b)
{
// CHECK: [[RES:%[0-9]+]] = mul nuw i64 [[Y]], [[X]]
// CHECK: ret i64 [[RES]]
+
+int test_inp(unsigned short port) {
+ return _inp(port);
+}
+// CHECK-I386-LABEL: define dso_local i32 @test_in
@@ -63,6 +63,82 @@ unsigned __int64 test__emulu(unsigned int a, unsigned int b)
{
// CHECK: [[RES:%[0-9]+]] = mul nuw i64 [[Y]], [[X]]
// CHECK: ret i64 [[RES]]
+
+int test_inp(unsigned short port) {
+ return _inp(port);
+}
+// CHECK-I386-LABEL: define dso_local i32 @test_in
@@ -63,6 +63,82 @@ unsigned __int64 test__emulu(unsigned int a, unsigned int b)
{
// CHECK: [[RES:%[0-9]+]] = mul nuw i64 [[Y]], [[X]]
// CHECK: ret i64 [[RES]]
+
+int test_inp(unsigned short port) {
+ return _inp(port);
+}
+// CHECK-I386-LABEL: define dso_local i32 @test_in
@@ -329,6 +329,28 @@ static __inline__ void __DEFAULT_FN_ATTRS __stosq(unsigned
__int64 *__dst,
static __inline__ void __DEFAULT_FN_ATTRS __halt(void) {
__asm__ volatile("hlt");
}
+
+static inline int _inp(unsigned short port) {
+ int ret;
+ __asm__ volatile("inb %b1, %b0"
@@ -329,6 +329,28 @@ static __inline__ void __DEFAULT_FN_ATTRS __stosq(unsigned
__int64 *__dst,
static __inline__ void __DEFAULT_FN_ATTRS __halt(void) {
__asm__ volatile("hlt");
}
+
+static inline int _inp(unsigned short port) {
+ int ret;
+ __asm__ volatile("inb %b1, %b0"
@@ -63,6 +63,47 @@ unsigned __int64 test__emulu(unsigned int a, unsigned int b)
{
// CHECK: [[RES:%[0-9]+]] = mul nuw i64 [[Y]], [[X]]
// CHECK: ret i64 [[RES]]
+
+int test_inp(unsigned short port) {
+ return _inp(port);
+}
+// CHECK-LABEL: i32 @test_inp(i16 noundef
+// CHEC
@@ -329,6 +329,28 @@ static __inline__ void __DEFAULT_FN_ATTRS __stosq(unsigned
__int64 *__dst,
static __inline__ void __DEFAULT_FN_ATTRS __halt(void) {
__asm__ volatile("hlt");
}
+
+static inline int _inp(unsigned short port) {
+ int ret;
+ __asm__ volatile("inb %w1, %b0"
@@ -329,6 +329,25 @@ static __inline__ void __DEFAULT_FN_ATTRS __stosq(unsigned
__int64 *__dst,
static __inline__ void __DEFAULT_FN_ATTRS __halt(void) {
__asm__ volatile("hlt");
}
+
+static inline int _inp(unsigned short port) {
+ int ret;
+ __asm__ volatile("inb %w1, %b0"
@@ -329,6 +329,25 @@ static __inline__ void __DEFAULT_FN_ATTRS __stosq(unsigned
__int64 *__dst,
static __inline__ void __DEFAULT_FN_ATTRS __halt(void) {
__asm__ volatile("hlt");
}
+
+static inline int _inp(unsigned short port) {
+ int ret;
+ __asm__ volatile("inb %w1, %b0"
https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/93804
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https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/93804
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@@ -298,15 +298,15 @@
// FioRACE2: "-E"
// FioRACE2: "-o" "foo.x"
-// RUN: %clang_cl /Z7 /Foa.obj -### -- %s 2>&1 | FileCheck
-check-prefix=ABSOLUTE_OBJPATH %s
+// RUN: %clang_cl -target x86_64-windows /Z7 /Foa.obj -### -- %s 2>&1 |
FileCheck -check-prefix=ABSOLUTE_OBJPATH %
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