[clang] [llvm] [RISCV] Add `zihintpause` LLVM/Clang intrinsic (PR #139519)

@@ -1886,6 +1886,12 @@ let TargetPrefix = "riscv" in { def int_riscv_vsm3me : RISCVBinaryAAXUnMasked; } // TargetPrefix = "riscv" +// Zihintpause extensions +//===--===// +let TargetPrefix = "riscv" in { -

[clang] [llvm] [RISCV] Add `zihintpause` LLVM/Clang intrinsic (PR #139519)

@@ -147,6 +147,13 @@ def ntl_load : RISCVBuiltin<"void(...)">; def ntl_store : RISCVBuiltin<"void(...)">; } // Features = "zihintntl", Attributes = [CustomTypeChecking] +//===--===// +// Zihintpause extension.

[clang] [llvm] [RISCV] Add `zihintpause` LLVM/Clang intrinsic (PR #139519)

@@ -2198,6 +2198,15 @@ def : Pat<(binop_allwusers GPR:$rs1, immop_oneuse:$rs2), def : Pat<(i64 (add GPR:$rs1, negImm:$rs2)), (SUB GPR:$rs1, negImm:$rs2)>; } +//===--===// +// Zihintpause +//===---

[clang] [llvm] [RISCV][MC] Add support for Q extension (PR #139369)

@@ -0,0 +1,153 @@ +//===-- RISCVInstrInfoQ.td - RISC-V 'Q' instructions ---*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [RISC-V] Allow intrinsics to be used with any pointer type. (PR #139634)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/139634 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add `zihintpause` LLVM/Clang intrinsic (PR #139519)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/139519 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add `zihintpause` LLVM/Clang intrinsic (PR #139519)

@@ -0,0 +1,14 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple riscv32 -target-feature +zihintpause -emit-llvm %s -o - \ wangpc-pp wrote: riscv64 RUN as well. https://github.com/llvm/llvm-project/pull

[clang] [llvm] [RISCV] Add `zihintpause` LLVM/Clang intrinsic (PR #139519)

https://github.com/wangpc-pp commented: Do we need a header for it (just like others in https://github.com/riscv-non-isa/riscv-c-api-doc/blob/main/src/c-api.adoc#intrinsic-functions)? https://github.com/llvm/llvm-project/pull/139519 ___ cfe-commits ma

[clang] [llvm] [RISCV] Add `zihintpause` LLVM/Clang intrinsic (PR #139519)

@@ -0,0 +1,14 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple riscv32 -target-feature +zihintpause -emit-llvm %s -o - \ +// RUN: | FileCheck %s + +#include wangpc-pp wrote: Remove this include.

[clang] [llvm] [RISCV] Add `zihintpause` LLVM/Clang intrinsic (PR #139519)

@@ -0,0 +1,17 @@ +//===-- RISCVInstrInfoZihintpause.td ---*- tablegen -*-===// wangpc-pp wrote: This file is too small, we may not need a standalone file for `Zihintpause`. You can put this pattern to llvm/lib/Target/RISCV/RISCVInstrInfo.td

[clang] [llvm] [RISCV] Add `zihintpause` LLVM/Clang intrinsic (PR #139519)

@@ -147,6 +147,13 @@ def ntl_load : RISCVBuiltin<"void(...)">; def ntl_store : RISCVBuiltin<"void(...)">; } // Features = "zihintntl", Attributes = [CustomTypeChecking] +//===--===// +// Zihintpause extension.

[clang] [llvm] [RISCV] Add `zihintpause` LLVM/Clang intrinsic (PR #139519)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/139519 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][MC] Add support for Q extension (PR #139369)

@@ -291,6 +291,13 @@ def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">, AssemblerPredicate<(all_of FeatureStdExtD), "'D' (Double-Precision Floating-Point)">; +def FeatureStdExtQ +: RISCVExtension<2, 2, "Quad-Precisio

[clang] [llvm] [RISCV] Add MC layer support for XSfmm*. (PR #133031)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/133031 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Handle target features correctly in CheckBuiltinFunctionCall (PR #141548)

@@ -0,0 +1,11 @@ +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +zvknha %s -fsyntax-only -verify + +#include + +// expected-no-diagnostics + +__attribute__((target("arch=+zvl128b"))) +void test_zvk_features(vuint32m1_t vd, vuint32m1_t v

[clang] [clang][RISCV] Handle target features correctly in CheckBuiltinFunctionCall (PR #141548)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/141548 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

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