@@ -5553,6 +5553,14 @@ static SDValue getSVEPredicateBitCast(EVT VT, SDValue
Op, SelectionDAG &DAG) {
if (InVT == VT)
return Op;
+ // Look through casts to when their input has more lanes than
+ // VT. This will increase the chances of removing casts that introduce n
@@ -953,9 +953,20 @@ Intrinsic::Intrinsic(StringRef Name, StringRef Proto,
uint64_t MergeTy,
SVEEmitter &Emitter, StringRef SVEGuard,
StringRef SMEGuard)
: Name(Name.str()), LLVMName(LLVMName), Proto(Proto.str()),
- BaseTypeSp
https://github.com/paulwalker-arm closed
https://github.com/llvm/llvm-project/pull/110281
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https://github.com/llvm/llvm-project/pull/109420
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https://github.com/paulwalker-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/114271
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https://github.com/paulwalker-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/112687
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@@ -36,16 +36,23 @@
/* Verify that the correct vector library is passed to LTO flags. */
// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fveclib=LIBMVEC -flto
%s 2>&1 | FileCheck --check-prefix=CHECK-LTO-LIBMVEC %s
+// CHECK-LTO-LIBMVEC: "-fmath-errno"
// CHECK-LTO-LI
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https://github.com/llvm/llvm-project/pull/99865
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@@ -2580,6 +2580,8 @@ void NeonEmitter::runVectorTypes(raw_ostream &OS) {
OS << "typedef __fp16 float16_t;\n";
OS << "#if defined(__aarch64__) || defined(__arm64ec__)\n";
+ OS << "typedef __MFloat8x8_t mfloat8x8_t;\n";
+ OS << "typedef __MFloat8x16_t mfloat8x16_t;\n";
--
https://github.com/paulwalker-arm commented:
I can be persuaded if there are good reasons for the `TypeSpec` side to wait,
but the the current placement of the typedefs looks wrong.
https://github.com/llvm/llvm-project/pull/99865
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@@ -36,16 +36,23 @@
/* Verify that the correct vector library is passed to LTO flags. */
// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fveclib=LIBMVEC -flto
%s 2>&1 | FileCheck --check-prefix=CHECK-LTO-LIBMVEC %s
+// CHECK-LTO-LIBMVEC: "-fmath-errno"
// CHECK-LTO-LI
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paulwalker-arm wrote:
I've pushed
https://github.com/llvm/llvm-project/commit/246b57cb2086b22ad8b41051c77e86ef478053a1
to fix the failing PowerPC tests. For what it's worth I think the tests are
overly restricted to only run on PowerPC machines, hence the reason they only
failed after the PR
paulwalker-arm wrote:
Thanks @CarolineConcatto this is structurally more what I had in mind. The
non-fp8 neon types make use of general vector support within clang but the fp8
based types are completely target specific and so I'd rather keep their spread
within common code to a minimum. Neon
@@ -490,6 +490,16 @@ void tools::AddLinkerInputs(const ToolChain &TC, const
InputInfoList &Inputs,
else
A.renderAsInput(Args, CmdArgs);
}
+ if (const Arg *A = Args.getLastArg(options::OPT_fveclib)) {
+if (A->getNumValues() == 1) {
+ StringRef V = A->getVa
paulwalker-arm wrote:
The flags are only intended to control the C++ representation of constant
splats and do not affect the parsing[1] or printing.
After this PR the expected behaviour is to unify the textual representation of
constant splats. I did not anticipate there being a need to contr
https://github.com/paulwalker-arm approved this pull request.
Looks good but please remember to update the commit message to reflect the PR
as it stands today.
https://github.com/llvm/llvm-project/pull/114804
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paulwalker-arm wrote:
What's the advantage of moving away from the current implementation? From what
I can see we're now having to add knowledge about what's essentially a target
specific type across common code, which the current implementation avoids.
https://github.com/llvm/llvm-project/pu
@@ -490,6 +490,16 @@ void tools::AddLinkerInputs(const ToolChain &TC, const
InputInfoList &Inputs,
else
A.renderAsInput(Args, CmdArgs);
}
+ if (const Arg *A = Args.getLastArg(options::OPT_fveclib)) {
+if (A->getNumValues() == 1) {
+ StringRef V = A->getVa
https://github.com/paulwalker-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/114983
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https://github.com/llvm/llvm-project/pull/118272
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@@ -0,0 +1,23 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 2
+// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu
-target-feature +sve -emit-llvm -o - %s | FileCheck %s
+
+#include
+
+using vec_t =
@@ -0,0 +1,23 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 2
+// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu
-target-feature +sve -emit-llvm -o - %s | FileCheck %s
+
+#include
+
+using vec_t =
@@ -1738,6 +1738,12 @@ SDValue SelectionDAGBuilder::getValueImpl(const Value
*V) {
if (const auto *NC = dyn_cast(C))
return getValue(NC->getGlobalValue());
+if (VT == MVT::aarch64svcount) {
+ assert(C->isNullValue() && "Can only zero this target type!");
+
https://github.com/paulwalker-arm created
https://github.com/llvm/llvm-project/pull/120443
I revisited 58690 and was puzzled why the obvious combines do not fire. I
believe the reason is combines that end with replaceOperand, because they can
introduce duplicate expression trees (albeit tiny o
https://github.com/paulwalker-arm updated
https://github.com/llvm/llvm-project/pull/120443
>From 35989b3a5b78f1eacc13104d9fdb806eb92ac7ae Mon Sep 17 00:00:00 2001
From: Paul Walker
Date: Wed, 18 Dec 2024 13:17:13 +
Subject: [PATCH 1/3] Add test to show missing CSE.
---
.../post-vectorisat
@@ -1306,6 +1306,10 @@ void PassBuilder::addVectorPasses(OptimizationLevel
Level,
}
// Cleanup after the loop optimization passes.
FPM.addPass(InstCombinePass());
+ // InstCombine can create CSE opportunities when it cleans the result of loop
+ // vectorization. They o
https://github.com/paulwalker-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/120753
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https://github.com/llvm/llvm-project/pull/116856
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https://github.com/paulwalker-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/118956
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paulwalker-arm wrote:
I see what you mean. I was concerned because the SVE variant makes special
mention of it but when looking as the pseudo code for the NEON variants I agree
they look consistent. Sorry for the confusion.
https://github.com/llvm/llvm-project/pull/127837
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@@ -2993,6 +2993,22 @@ let Predicates = [HasSVE_or_SME] in {
defm : unpred_loadstore_bitcast;
defm : unpred_loadstore_bitcast;
+ // Allow using LDR/STR to avoid the predicate dependence.
+ let Predicates = [IsLE, AllowMisalignedMemAccesses] in
+foreach Ty = [ nxv16i8
@@ -2993,6 +2993,22 @@ let Predicates = [HasSVE_or_SME] in {
defm : unpred_loadstore_bitcast;
defm : unpred_loadstore_bitcast;
+ // Allow using LDR/STR to avoid the predicate dependence.
+ let Predicates = [IsLE, AllowMisalignedMemAccesses] in
+foreach Ty = [ nxv16i8
https://github.com/paulwalker-arm edited
https://github.com/llvm/llvm-project/pull/127837
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https://github.com/paulwalker-arm approved this pull request.
Based on the previous conversation I'm happy enough. I don't think the
existing bug needs to hold up this PR and I can take a look at fixing it once
this lands.
Please keep an ear out for any performance regression reports just in
@@ -2993,6 +2993,22 @@ let Predicates = [HasSVE_or_SME] in {
defm : unpred_loadstore_bitcast;
defm : unpred_loadstore_bitcast;
+ // Allow using LDR/STR to avoid the predicate dependence.
+ let Predicates = [IsLE, AllowMisalignedMemAccesses] in
paulwalker
https://github.com/paulwalker-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/125097
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@@ -26,11 +26,15 @@ typedef vbool64_t fixed_bool64_t
__attribute__((riscv_rvv_vector_bits(__riscv_v_
//
// CHECK-128-LABEL: @call_bool32_ff(
// CHECK-128-NEXT: entry:
+// CHECK-128-NEXT:[[SAVED_VALUE:%.*]] = alloca <1 x i8>, align 1
paulwalker-arm wrote:
https://github.com/paulwalker-arm updated
https://github.com/llvm/llvm-project/pull/130973
>From 487a823a9ec35df1a93109ef03630738bdc39ab1 Mon Sep 17 00:00:00 2001
From: Paul Walker
Date: Fri, 7 Mar 2025 11:54:20 +
Subject: [PATCH] [LLVM][SROA] Teach SROA how to "bitcast" between fixed and
https://github.com/paulwalker-arm created
https://github.com/llvm/llvm-project/pull/130973
For function whose vscale_range is limited to a single value we can size
scalable vectors. This aids SROA by allowing scalable vector load and store
operations to be considered for replacement whereby bi
@@ -0,0 +1,362 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve
-aarch64-sve-vector-bits-min=128 -aarc
@@ -7380,17 +7380,31 @@ bool
AArch64DAGToDAGISel::SelectAddrModeIndexedSVE(SDNode *Root, SDValue N,
return false;
SDValue VScale = N.getOperand(1);
- if (VScale.getOpcode() != ISD::VSCALE)
+ std::optional MulImm;
+ if (VScale.getOpcode() == ISD::VSCALE) {
+MulImm
@@ -7380,12 +7380,26 @@ bool
AArch64DAGToDAGISel::SelectAddrModeIndexedSVE(SDNode *Root, SDValue N,
return false;
SDValue VScale = N.getOperand(1);
- if (VScale.getOpcode() != ISD::VSCALE)
+ int64_t MulImm = std::numeric_limits::max();
+ if (VScale.getOpcode() == ISD
@@ -405,6 +405,17 @@ class AArch64Subtarget final : public
AArch64GenSubtargetInfo {
return MinSVEVectorSizeInBits;
}
+ // Return the known bit length of SVE data registers. A value of 0 means the
+ // length is unkown beyond what's implied by the architecture.
+ uns
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https://github.com/llvm/llvm-project/pull/129732
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@@ -405,6 +405,17 @@ class AArch64Subtarget final : public
AArch64GenSubtargetInfo {
return MinSVEVectorSizeInBits;
}
+ // Return the known bit length of SVE data registers. A value of 0 means the
+ // length is unkown beyond what's implied by the architecture.
+ uns
@@ -7380,17 +7380,31 @@ bool
AArch64DAGToDAGISel::SelectAddrModeIndexedSVE(SDNode *Root, SDValue N,
return false;
SDValue VScale = N.getOperand(1);
- if (VScale.getOpcode() != ISD::VSCALE)
+ std::optional MulImm;
+ if (VScale.getOpcode() == ISD::VSCALE) {
+MulImm
https://github.com/paulwalker-arm approved this pull request.
Other than a potentially erroneous assert this looks good to me.
https://github.com/llvm/llvm-project/pull/129732
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paulwalker-arm wrote:
@pawosm-arm - I've removed the reviewers because it is not quite ready yet. I
need to investigate the potential regressions shown by the RISCV tests.
https://github.com/llvm/llvm-project/pull/130973
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paulwalker-arm wrote:
Sorry for the delay and thanks for the investigation @rj-jesus. This is so
not intentional behaviour. VLS based auto vectorisation was implemented before
the VLS ACLE extensions and by that time it's likely fixed length calls to
`llvm.vscale()` were constant folded a
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@@ -473,6 +473,14 @@ std::optional Attribute::getVScaleRangeMax()
const {
return unpackVScaleRangeArgs(pImpl->getValueAsInt()).second;
}
+unsigned Attribute::getVScaleValue() const {
+ std::optional VScale = getVScaleRangeMax();
+ if (VScale && *VScale == getVScaleRangeMi
https://github.com/paulwalker-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/130625
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@@ -2034,6 +2071,18 @@ static Value *convertValue(const DataLayout &DL,
IRBuilderTy &IRB, Value *V,
}
}
+ if (isa(NewTy) && isa(OldTy)) {
+auto *Ty = VectorType::getWithSizeAndScalar(cast(NewTy),
OldTy);
+V = IRB.CreateInsertVector(Ty, PoisonValue::get(Ty), V,
https://github.com/paulwalker-arm updated
https://github.com/llvm/llvm-project/pull/130973
>From 32a2805a41dc3ff02bff9df26f4665923445b488 Mon Sep 17 00:00:00 2001
From: Paul Walker
Date: Thu, 20 Mar 2025 14:58:51 +
Subject: [PATCH 1/2] Add SROA tests for casts between fixed and scalable
ty
https://github.com/paulwalker-arm commented:
I'll take a closer look later but here are some stylistic things to streamline
the patch a little.
https://github.com/llvm/llvm-project/pull/135016
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ht
@@ -1492,9 +1492,17 @@ static bool isAllActivePredicate(Value *Pred) {
if (cast(Pred->getType())->getMinNumElements() <=
cast(UncastedPred->getType())->getMinNumElements())
Pred = UncastedPred;
+ if (match(Pred, m_Intrinsic(
+ m_ConstantI
@@ -2641,6 +2641,20 @@ static std::optional
instCombineDMB(InstCombiner &IC,
return std::nullopt;
}
+static std::optional instCombinePTrue(InstCombiner &IC,
+ IntrinsicInst &II) {
+ IRBuilder<> Builder(&II);
+ auto Type
https://github.com/paulwalker-arm edited
https://github.com/llvm/llvm-project/pull/135016
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@@ -2641,6 +2641,20 @@ static std::optional
instCombineDMB(InstCombiner &IC,
return std::nullopt;
}
+static std::optional instCombinePTrue(InstCombiner &IC,
+ IntrinsicInst &II) {
+ IRBuilder<> Builder(&II);
+ auto Type
@@ -1990,21 +2028,56 @@ static bool canConvertValue(const DataLayout &DL, Type
*OldTy, Type *NewTy) {
static Value *convertValue(const DataLayout &DL, IRBuilderTy &IRB, Value *V,
Type *NewTy) {
Type *OldTy = V->getType();
- assert(canConvertValue(
@@ -554,6 +554,22 @@ class VectorType : public Type {
return VectorType::get(VTy->getElementType(), EltCnt * 2);
}
+ /// This static method returns a VectorType with the same size-in-bits as
+ /// SizeTy but with an element type that matches the scalar type of EltTy.
+
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