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@@ -225,7 +225,7 @@ def IsStreamingCompatible :
FlagType<0x40>;
def IsReadZA: FlagType<0x80>;
def IsWriteZA : FlagType<0x100>;
def IsReductionQV : FlagType<0x200>;
-def Is
@@ -561,16 +561,61 @@ SemaARM::ArmStreamingType getArmStreamingFnType(const
FunctionDecl *FD) {
static void checkArmStreamingBuiltin(Sema &S, CallExpr *TheCall,
const FunctionDecl *FD,
- SemaARM::ArmStre
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https://github.com/paulwalker-arm created
https://github.com/llvm/llvm-project/pull/89762
We only use common intrinsics for operations that treat their element type as a
container of bits.
>From ed27a2d1406dccf70e7189578cd6950b61961c1b Mon Sep 17 00:00:00 2001
From: Paul Walker
Date: Tue, 23
paulwalker-arm wrote:
Is it possible to use TargetExtType for the scalar type given this is a target
specific type. I fully expect LLVM not to support vector's of TargetExtType
but I wonder if that can be relaxed given our only use case is to pass them to
intrinsics. For anything more exotic
paulwalker-arm wrote:
Sorry for the noise but I think I've a more wellformed question this time.
Is it be possible to use `AArch64SVEACLETypes.def` to reduce some of the
boilerplate changes? I'm not sure how much of this is tied to SVE (or rather
scalable types) but I'm wondering if clang can
https://github.com/paulwalker-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/100740
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https://github.com/llvm/llvm-project/pull/88748
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@@ -135,6 +135,8 @@ enum NodeType : unsigned {
UDIV_PRED,
UMAX_PRED,
UMIN_PRED,
+ FAMAX_PRED,
+ FAMIN_PRED,
paulwalker-arm wrote:
Yep, the latter. We use it here because the ISD node exists for other reasons
and so was convenient to reuse here.
In ge
https://github.com/paulwalker-arm edited
https://github.com/llvm/llvm-project/pull/99042
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A couple of suggestions but otherwise this looks good to me.
https://github.com/llvm/llvm-project/pull/99042
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@@ -0,0 +1,115 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc -mattr=+sve2 < %s | FileCheck %s
+; RUN: llc -mattr=+sme2 -force-streaming < %s | FileCheck %s
+
+target triple = "aarch64-linux"
+
+define @famin_f
@@ -717,6 +717,11 @@ let Predicates = [HasSVEorSME] in {
defm FDIV_ZPZZ : sve_fp_bin_pred_hfd;
} // End HasSVEorSME
+let Predicates = [HasSVE2orSME2, HasFAMINMAX] in {
+ defm FAMAX_ZPZZ : sve_fp_bin_pred_hfd;
+ defm FAMIN_ZPZZ : sve_fp_bin_pred_hfd;
+}
+
https://github.com/paulwalker-arm requested changes to this pull request.
As discussed offline, I don't think we want to be this strict. As demonstrated
by the changes to the ACLE tests, this change makes it impossible to distribute
a library in binary form that can work for both SVE and InStr
https://github.com/paulwalker-arm edited
https://github.com/llvm/llvm-project/pull/91356
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@@ -9,6 +9,12 @@
#include
+#if defined __ARM_FEATURE_SME
+#define MODE_ATTR __arm_streaming
+#else
+#define MODE_ATTR __arm_streaming_compatible
paulwalker-arm wrote:
Do you need to use `__arm_streaming_compatible` here? Now we've agreed this
keyword has
@@ -8982,11 +8982,18 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD)
{
const FunctionDecl *FD = cast(CurContext);
llvm::StringMap CallerFeatureMap;
Context.getFunctionFeatureMap(CallerFeatureMap, FD);
-if (!Builtin::evaluateRequiredTargetFeatures(
-
https://github.com/paulwalker-arm commented:
After further discussion I know understand the `__arm_streaming_compatible`
keyword has no affect on the target features in play and only tells the
compiler not to emit any SM state changing instructions as part of the calling
convention.
https://g
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@@ -221,6 +221,10 @@ FLOATING_TYPE(Float128, Float128Ty)
// '__ibm128'
FLOATING_TYPE(Ibm128, Ibm128Ty)
+
+// '__fpm8'
paulwalker-arm wrote:
__mfp8
https://github.com/llvm/llvm-project/pull/97277
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@@ -1139,6 +1139,7 @@ class ASTContext : public RefCountedBase {
CanQualType SatShortFractTy, SatFractTy, SatLongFractTy;
CanQualType SatUnsignedShortFractTy, SatUnsignedFractTy,
SatUnsignedLongFractTy;
+ CanQualType MFloat8Ty;
paulwalker-arm wrote:
@@ -3197,6 +3197,13 @@ void CastOperation::CheckCStyleCast() {
}
}
+ if ((DestType->isMFloat8Type() && !SrcType->isMFloat8Type()) ||
+ (!DestType->isMFloat8Type() && SrcType->isMFloat8Type())) {
paulwalker-arm wrote:
`DestType->isMFloat8Type() !=
paulwalker-arm wrote:
Just to add the commit message needs updating to reflect the updated
specification.
https://github.com/llvm/llvm-project/pull/97277
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https://github.com/paulwalker-arm approved this pull request.
This is certainly a step in the right direction.
https://github.com/llvm/llvm-project/pull/96482
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@@ -69,7 +69,7 @@
#ifndef SVE_VECTOR_TYPE_BFLOAT
#define SVE_VECTOR_TYPE_BFLOAT(Name, MangledName, Id, SingletonId, NumEls,
ElBits, NF) \
- SVE_VECTOR_TYPE_DETAILS(Name, MangledName, Id, SingletonId, NumEls, ElBits,
NF, false, false, true)
+ SVE_VECTOR_TYPE_DETAILS(Name, M
@@ -4419,6 +4419,13 @@ QualType ASTContext::getScalableVectorType(QualType
EltTy, unsigned NumElts,
EltTySize == ElBits && NumElts == (NumEls * NF) && NumFields == 1) {
\
return SingletonId;
\
}
+#define
@@ -4072,6 +4078,30 @@ static Value *upgradeX86IntrinsicCall(StringRef Name,
CallBase *CI, Function *F,
return Rep;
}
+static Value *upgradeAArch64IntrinsicCall(StringRef Name, CallBase *CI,
+ Function *F, IRBuilder<> &Builder) {
+
@@ -5553,6 +5553,14 @@ static SDValue getSVEPredicateBitCast(EVT VT, SDValue
Op, SelectionDAG &DAG) {
if (InVT == VT)
return Op;
+ // Look through casts to when their input has more lanes than
paulwalker-arm wrote:
Done, plus removed another redundan
@@ -1003,6 +998,13 @@ defm SVFCVT_F32_F64 : SInstCvtMXZ<"svcvt_f32[_f64]",
"MMPd", "MPd", "d", "aarc
defm SVFCVT_F64_F16 : SInstCvtMXZ<"svcvt_f64[_f16]", "ddPO", "dPO", "d",
"aarch64_sve_fcvt_f64f16">;
defm SVFCVT_F64_F32 : SInstCvtMXZ<"svcvt_f64[_f32]", "ddPM", "dPM", "
https://github.com/paulwalker-arm updated
https://github.com/llvm/llvm-project/pull/110281
>From 7fd66c7630ec03db05203c7ffdf8e36e23e30d93 Mon Sep 17 00:00:00 2001
From: Paul Walker
Date: Thu, 26 Sep 2024 18:07:52 +0100
Subject: [PATCH 1/2] [AArch64][SVE] Fix definition of bfloat fcvt intrinsics
@@ -97,6 +97,17 @@
SVE_TYPE(Name, Id, SingletonId)
#endif
+#ifndef AARCH64_VECTOR_TYPE
paulwalker-arm wrote:
I agree. Carol and I discussed this previously and I asked her to ignore the
obvious structural/naming issues and focus on adding the new types in
@@ -502,6 +502,10 @@ def err_sls_hardening_arm_not_supported : Error<
def warn_drv_large_data_threshold_invalid_code_model: Warning<
"'%0' only applies to medium and large code models">,
InGroup;
+def warn_drv_math_errno_reenabled_after_veclib: Warning<
+ "math errno re-en
@@ -2960,6 +2969,12 @@ static void RenderFloatingPointOptions(const ToolChain
&TC, const Driver &D,
}
for (const Arg *A : Args) {
+auto CheckMathErrnoForVecLib =
+llvm::make_scope_exit([&, MathErrnoBeforeArg = MathErrno] {
+ if (NoMathErrnoWasImpliedB
@@ -2960,6 +2969,12 @@ static void RenderFloatingPointOptions(const ToolChain
&TC, const Driver &D,
}
for (const Arg *A : Args) {
+auto CheckMathErrnoForVecLib =
+llvm::make_scope_exit([&, MathErrnoBeforeArg = MathErrno] {
+ if (NoMathErrnoWasImpliedB
@@ -3125,6 +3140,13 @@ static void RenderFloatingPointOptions(const ToolChain
&TC, const Driver &D,
TrappingMathPresent = true;
FPExceptionBehavior = "strict";
break;
+case options::OPT_fveclib:
+ VecLibArg = A;
+ if (llvm::is_contained(VecLibIm
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@@ -36,16 +36,23 @@
/* Verify that the correct vector library is passed to LTO flags. */
// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fveclib=LIBMVEC -flto
%s 2>&1 | FileCheck --check-prefix=CHECK-LTO-LIBMVEC %s
+// CHECK-LTO-LIBMVEC: "-fmath-errno"
// CHECK-LTO-LI
@@ -3125,6 +3129,10 @@ static void RenderFloatingPointOptions(const ToolChain
&TC, const Driver &D,
TrappingMathPresent = true;
FPExceptionBehavior = "strict";
break;
+case options::OPT_fveclib:
+ if (llvm::is_contained(VecLibImpliesNoMathErrno, A->g
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@@ -69,6 +69,11 @@
#ifndef SVE_VECTOR_TYPE_BFLOAT
#define SVE_VECTOR_TYPE_BFLOAT(Name, MangledName, Id, SingletonId, NumEls,
ElBits, NF) \
+ SVE_VECTOR_TYPE_DETAILS(Name, MangledName, Id, SingletonId, NumEls, ElBits,
NF, true, false, true)
+#endif
+
+#ifndef SVE_VECTOR_TYPE
https://github.com/paulwalker-arm commented:
Not sure if there's enough support to update all of them but, but many of the
following should be extended to cover the new types:
clang/test/CodeGenCXX/aarch64-sve-vector-init.cpp
clang/test/CodeGenCXX/aarch64-mangle-sve-fixed-vectors.cpp
clang/test
@@ -4339,7 +4339,6 @@ ASTContext::getBuiltinVectorTypeInfo(const BuiltinType
*Ty) const {
switch (Ty->getKind()) {
default:
llvm_unreachable("Unsupported builtin vector type");
-
paulwalker-arm wrote:
Please can we keep these blank lines. With all th
@@ -87,6 +87,10 @@ class SVEType {
bool isDefault() const { return DefaultType; }
bool isFloat() const { return Float && !BFloat; }
bool isBFloat() const { return BFloat && !Float; }
+ bool isMFloat() const {
+return MFloat && !BFloat && !Float;
+;
--
@@ -454,6 +458,8 @@ std::string SVEType::builtin_str() const {
else if (isBFloat()) {
assert(ElementBitwidth == 16 && "Not a valid BFloat.");
S += "y";
+ } else if (isMFloat()) {
+S += "m";
paulwalker-arm wrote:
Perhaps worth adding `assert(Elem
@@ -4354,12 +4353,16 @@ ASTContext::getBuiltinVectorTypeInfo(const BuiltinType
*Ty) const {
ElBits, NF)
\
case BuiltinType::Id:
\
return {BFloat16T
@@ -87,6 +87,10 @@ class SVEType {
bool isDefault() const { return DefaultType; }
bool isFloat() const { return Float && !BFloat; }
bool isBFloat() const { return BFloat && !Float; }
paulwalker-arm wrote:
To be consistent I think these need updating to i
@@ -526,6 +526,11 @@ llvm::Type *CodeGenTypes::ConvertType(QualType T) {
}
case BuiltinType::SveCount:
return llvm::TargetExtType::get(getLLVMContext(), "aarch64.svcount");
+case BuiltinType::ArmMFloat8:
+ ResultType =
+ llvm::VectorType::get(l
@@ -5828,6 +5832,7 @@ bool Parser::isKnownToBeTypeSpecifier(const Token &Tok)
const {
case tok::kw__ExtInt:
case tok::kw__BitInt:
case tok::kw___bf16:
+ case tok::kw___mfp8:
paulwalker-arm wrote:
Do you know why this and the similar changes are needed?
@@ -2218,6 +2219,11 @@ TypeInfo ASTContext::getTypeInfoImpl(const Type *T)
const {
Width = 0;
\
Align = 16;
\
break;
+#define AARCH64_SC
@@ -1391,7 +1391,8 @@ void ASTContext::InitBuiltinTypes(const TargetInfo
&Target,
}
if (Target.hasAArch64SVETypes() ||
- (AuxTarget && AuxTarget->hasAArch64SVETypes())) {
+ (AuxTarget && AuxTarget->hasAArch64SVETypes()) ||
+ Target.hasArmMFloat8Type()) {
--
@@ -3437,8 +3445,8 @@ StringRef BuiltinType::getName(const PrintingPolicy
&Policy) const {
case Id: \
return #ExtType;
#include "clang/Basic/OpenCLExtensionTypes.def"
-#define SVE_TYPE(Name, Id, SingletonId) \
- case Id: \
+#define SVE_TYPE(Name, Id, SingletonId)
@@ -700,6 +701,9 @@ class TargetInfo : public TransferrableTargetInfo,
return HasBFloat16 || HasFullBFloat16;
}
+ /// Determine whether the _mfp8 type is supported on this target.
+ virtual bool hasArmMFloat8Type() const { return HasMFloat8; }
paulwalk
@@ -476,7 +476,6 @@ llvm::Type *CodeGenTypes::ConvertType(QualType T) {
Context.getFloatTypeSemantics(T),
/* UseNativeHalf = */ false);
break;
-
paulwalker-arm wrote:
Unnecessary whi
@@ -4302,6 +4308,7 @@ ASTContext::getBuiltinVectorTypeInfo(const BuiltinType
*Ty) const {
case BuiltinType::Id:
\
return {BoolTy, llvm::ElementCount::getScalable(NumEls), NF};
#define SVE_OPAQUE_TYPE(Name, MangledNa
@@ -1687,6 +1692,46 @@ static void WriteConstantInternal(raw_ostream &Out,
const Constant *CV,
return;
}
+ // When in the mode where Constant{Int,FP} do not support vector types the
+ // "splat(Ty val)" syntax is interpreted as a ConstantDataVector. Maintaining
+ //
paulwalker-arm wrote:
FYI: I've separated the code changes into a separate (first) commit to aid
review.
https://github.com/llvm/llvm-project/pull/112548
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@@ -2580,6 +2580,8 @@ void NeonEmitter::runVectorTypes(raw_ostream &OS) {
OS << "typedef __fp16 float16_t;\n";
OS << "#if defined(__aarch64__) || defined(__arm64ec__)\n";
+ OS << "typedef __MFloat8x8_t mfloat8x8_t;\n";
+ OS << "typedef __MFloat8x16_t mfloat8x16_t;\n";
--
@@ -2580,6 +2580,8 @@ void NeonEmitter::runVectorTypes(raw_ostream &OS) {
OS << "typedef __fp16 float16_t;\n";
OS << "#if defined(__aarch64__) || defined(__arm64ec__)\n";
+ OS << "typedef __MFloat8x8_t mfloat8x8_t;\n";
+ OS << "typedef __MFloat8x16_t mfloat8x16_t;\n";
--
@@ -2580,6 +2580,8 @@ void NeonEmitter::runVectorTypes(raw_ostream &OS) {
OS << "typedef __fp16 float16_t;\n";
OS << "#if defined(__aarch64__) || defined(__arm64ec__)\n";
+ OS << "typedef __MFloat8x8_t mfloat8x8_t;\n";
+ OS << "typedef __MFloat8x16_t mfloat8x16_t;\n";
--
@@ -107,6 +107,15 @@
AARCH64_VECTOR_TYPE(Name, MangledName, Id, SingletonId)
#endif
+#ifndef AARCH64_SCALAR_TYPE
+#define AARCH64_SCALAR_TYPE(Name, MangledName, Id, SingletonId) \
+ SVE_TYPE(Name, Id, SingletonId)
+#endif
+
+#ifndef AARCH64_SCALAR_TYPE_MFLOAT
+#define AARCH
@@ -2590,6 +2590,7 @@ void NeonEmitter::runVectorTypes(raw_ostream &OS) {
OS << "#if defined(__aarch64__) || defined(__arm64ec__)\n";
OS << "typedef __MFloat8x8_t mfloat8x8_t;\n";
OS << "typedef __MFloat8x16_t mfloat8x16_t;\n";
+ OS << "typedef __MFloat8_t __mfp8;\n";
--
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paulwalker-arm wrote:
> Yet we see a value in the change proposed here too hence a good reason for
> merging it.
I've clearly misunderstood the context of the rebase. What is the value in
merging this change if the original issue has already been resolved? I guess
this fix is simpler and
@@ -1690,6 +1690,23 @@ static void WriteConstantInternal(raw_ostream &Out,
const Constant *CV,
if (isa(CV) || isa(CV)) {
auto *CVVTy = cast(CV->getType());
Type *ETy = CVVTy->getElementType();
+
+// Use the same shorthand for splat vector (i.e. "splat(Ty val)") a
@@ -1690,6 +1690,23 @@ static void WriteConstantInternal(raw_ostream &Out,
const Constant *CV,
if (isa(CV) || isa(CV)) {
auto *CVVTy = cast(CV->getType());
Type *ETy = CVVTy->getElementType();
+
+// Use the same shorthand for splat vector (i.e. "splat(Ty val)") a
https://github.com/paulwalker-arm approved this pull request.
The change looks reasonable to me and consistent within an existing solution to
a similar problem. Worse case, the new code should be removed when we're at a
point that instruction fast math flags are sufficiently preserved/propagat
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@@ -0,0 +1,91 @@
+// RUN: %clang_cc1 -std=c++11 -triple aarch64-arm-none-eabi -target-feature
-fp8 -ast-dump %s | \
+// RUN: FileCheck %s --strict-whitespace
+
+// REQUIRES: aarch64-registered-target || arm-registered-target
+
+/* Various contexts where type __mfp8 can appear.
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@@ -4302,6 +4308,7 @@ ASTContext::getBuiltinVectorTypeInfo(const BuiltinType
*Ty) const {
case BuiltinType::Id:
\
return {BoolTy, llvm::ElementCount::getScalable(NumEls), NF};
#define SVE_OPAQUE_TYPE(Name, MangledNa
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https://github.com/paulwalker-arm approved this pull request.
Whilst I understand the rational for requesting an alternate solution, it feels
unfair. If the PR was to add a new OS or Vendor I'd have more sympathy but
here we're talking about extending the existing OS-Vendor support to cover
a
https://github.com/paulwalker-arm edited
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@@ -2986,6 +2986,14 @@ void CastOperation::CheckCStyleCast() {
return;
}
+ if ((DestType->isArmMFloat8Type() && !SrcType->isArmMFloat8Type()) ||
+ (!DestType->isArmMFloat8Type() && SrcType->isArmMFloat8Type())) {
paulwalker-arm wrote:
`DestType->i
@@ -2218,6 +2219,12 @@ TypeInfo ASTContext::getTypeInfoImpl(const Type *T)
const {
Width = 0;
\
Align = 16;
\
break;
+#define AARCH64_OP
https://github.com/paulwalker-arm commented:
Sorry, my comments are a bit all over the place, but I'm concerned we've not
defined enough (and/or I need to understand what it means to be a storage only
type) for me to confidently accept this PR.
If possible, my suggestion is to detach the scala
@@ -782,6 +782,13 @@ llvm::DIType *CGDebugInfo::CreateType(const BuiltinType
*BT) {
#define SVE_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
#include "clang/Basic/AArch64SVEACLETypes.def"
{
+ if (BT->getKind() == BuiltinType::ArmMFloat8) {
+Encoding = llv
@@ -97,6 +97,12 @@
SVE_TYPE(Name, Id, SingletonId)
#endif
+#ifndef AARCH64_OPAQUE_TYPE
+#define AARCH64_OPAQUE_TYPE(Name, MangledName, Id, SingletonId, NumEls, \
+ElBits, NF) \
+ SVE_TYPE(Name, Id, SingletonId)
+#endif
+
paulwalk
@@ -3437,9 +3446,19 @@ StringRef BuiltinType::getName(const PrintingPolicy
&Policy) const {
case Id: \
return #ExtType;
#include "clang/Basic/OpenCLExtensionTypes.def"
-#define SVE_TYPE(Name, Id, SingletonId) \
- case Id: \
+#define SVE_VECTOR_TYPE(Name, MangledName, Id
@@ -325,6 +325,8 @@ class DeclSpec {
#define HLSL_INTANGIBLE_TYPE(Name, Id, SingletonId)
\
static const TST TST_##Name = clang::TST_##Name;
#include "clang/Basic/HLSLIntangibleTypes.def"
+ // AARCH64_OPAQUE_TYPE
+ static const TST TST_ArmMFloat8_
@@ -2644,6 +2644,8 @@ class alignas(TypeAlignment) Type : public
ExtQualsTypeCommonBase {
bool isQueueT() const;// OpenCL queue_t
bool isReserveIDT() const;// OpenCL reserve_id_t
+ bool isArmMFloat8Type() const; // AARCH64_OPAQ
https://github.com/paulwalker-arm edited
https://github.com/llvm/llvm-project/pull/97277
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@@ -1802,9 +1854,29 @@ void SVEEmitter::createStreamingAttrs(raw_ostream &OS,
ACLEKind Kind) {
if (Def->isFlagSet(IsStreamingFlag))
StreamingMap["ArmStreaming"].insert(Def->getMangledName());
-else if (Def->isFlagSet(VerifyRuntimeMode))
+else if (Def->isFlag
@@ -1802,9 +1854,29 @@ void SVEEmitter::createStreamingAttrs(raw_ostream &OS,
ACLEKind Kind) {
if (Def->isFlagSet(IsStreamingFlag))
StreamingMap["ArmStreaming"].insert(Def->getMangledName());
-else if (Def->isFlagSet(VerifyRuntimeMode))
+else if (Def->isFlag
https://github.com/paulwalker-arm closed
https://github.com/llvm/llvm-project/pull/109423
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https://github.com/paulwalker-arm created
https://github.com/llvm/llvm-project/pull/110281
Affected intrinsics:
llvm.aarch64.sve.fcvt.bf16f32
llvm.aarch64.sve.fcvtnt.bf16f32
The named intrinsics took a predicate based on the smallest element type when
it should be based on the largest.
@@ -567,23 +567,28 @@ static bool checkArmStreamingBuiltin(Sema &S, CallExpr
*TheCall,
// * When compiling for SVE only, the caller must be in non-streaming mode.
// * When compiling for both SVE and SME, the caller can be in either mode.
if (BuiltinType == SemaARM::Veri
https://github.com/paulwalker-arm edited
https://github.com/llvm/llvm-project/pull/109420
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@@ -5553,6 +5553,14 @@ static SDValue getSVEPredicateBitCast(EVT VT, SDValue
Op, SelectionDAG &DAG) {
if (InVT == VT)
return Op;
+ // Look through casts to when their input has more lanes than
paulwalker-arm wrote:
I knew something was odd when I was
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