Author: nemanjai
Date: Thu Jul 19 05:44:15 2018
New Revision: 337449
URL: http://llvm.org/viewvc/llvm-project?rev=337449&view=rev
Log:
[PowerPC] Handle __builtin_xxpermdi the same way as GCC does
The codegen for this builtin was initially implemented to match GCC.
However, due to interest from us
Author: nemanjai
Date: Thu Jul 19 05:49:27 2018
New Revision: 337451
URL: http://llvm.org/viewvc/llvm-project?rev=337451&view=rev
Log:
NFC: Remove extraneous semicolons as pointed out in the differential review
The commit for
https://reviews.llvm.org/D49424
missed the comment about the extraneous
Author: nemanjai
Date: Mon Nov 26 06:35:38 2018
New Revision: 347556
URL: http://llvm.org/viewvc/llvm-project?rev=347556&view=rev
Log:
[PowerPC] Vector load/store builtins overstate alignment of pointers
A number of builtins in altivec.h load/store vectors from pointers to scalar
types. Currently
Author: nemanjai
Date: Wed Mar 13 16:54:52 2019
New Revision: 356111
URL: http://llvm.org/viewvc/llvm-project?rev=356111&view=rev
Log:
Fix invocation of Gold plugin with LTO after r355331
The above commit breaks the usage of PGO and LTO when -fprofile-use is
supplied without a path. This patch ch
Author: nemanjai
Date: Tue May 7 19:03:32 2019
New Revision: 360220
URL: http://llvm.org/viewvc/llvm-project?rev=360220&view=rev
Log:
Fix buildbot break after r360195
Modified:
cfe/trunk/test/Modules/preprocess-umbrella.cpp
Modified: cfe/trunk/test/Modules/preprocess-umbrella.cpp
URL:
http
Author: nemanjai
Date: Tue Feb 5 04:05:53 2019
New Revision: 353163
URL: http://llvm.org/viewvc/llvm-project?rev=353163&view=rev
Log:
[NFC] Explicitly add -std=c++14 option to tests that rely on the C++14 default
When Clang/LLVM is built with the CLANG_DEFAULT_STD_CXX CMake macro that sets
the d
Author: nemanjai
Date: Wed Feb 20 12:27:33 2019
New Revision: 354512
URL: http://llvm.org/viewvc/llvm-project?rev=354512&view=rev
Log:
Make predefined FLT16 macros conditional on support for the type
We unconditionally predefine these macros. However, they may be used to
determine if the type is
Author: nemanjai
Date: Tue Jun 4 18:57:57 2019
New Revision: 362571
URL: http://llvm.org/viewvc/llvm-project?rev=362571&view=rev
Log:
Initial support for vectorization using MASSV (IBM MASS vector library)
Part 2 (the Clang portion) of D59881.
This patch (first of two patches) enables the vecto
I think what she is referring to was that the build seemed to be triggered
by a commit to a project that shouldn't trigger builds on a libcxx bot
(i.e. the change was in llvm).
I have a somewhat orthogonal but related question. In the past, commits to
compiler-rt did not trigger builds on llvm/cla
Author: Nemanja Ivanovic
Date: 2020-05-22T07:59:21-05:00
New Revision: aede24ecaa08db806fb173faf2de9cff95df8cee
URL:
https://github.com/llvm/llvm-project/commit/aede24ecaa08db806fb173faf2de9cff95df8cee
DIFF:
https://github.com/llvm/llvm-project/commit/aede24ecaa08db806fb173faf2de9cff95df8cee.di
Author: Nemanja Ivanovic
Date: 2020-05-28T06:55:49-05:00
New Revision: f9e94eb8688d1fe1727360462e957fbbfb754e59
URL:
https://github.com/llvm/llvm-project/commit/f9e94eb8688d1fe1727360462e957fbbfb754e59
DIFF:
https://github.com/llvm/llvm-project/commit/f9e94eb8688d1fe1727360462e957fbbfb754e59.di
Author: Nemanja Ivanovic
Date: 2020-05-28T15:48:15-05:00
New Revision: 9021ce9576e438ae5a6fdb574327d30ea6b67fa8
URL:
https://github.com/llvm/llvm-project/commit/9021ce9576e438ae5a6fdb574327d30ea6b67fa8
DIFF:
https://github.com/llvm/llvm-project/commit/9021ce9576e438ae5a6fdb574327d30ea6b67fa8.di
Author: nemanjai
Date: Tue Sep 27 05:45:22 2016
New Revision: 282481
URL: http://llvm.org/viewvc/llvm-project?rev=282481&view=rev
Log:
[Power9] Builtins for ELF v.2 ABI conformance - front end portion
This patch corresponds to review:
https://reviews.llvm.org/D24397
It adds the __POWER9_VECTOR__
nemanjai closed this revision.
nemanjai added a comment.
Committed revision 282481.
Repository:
rL LLVM
https://reviews.llvm.org/D24397
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-com
nemanjai added a comment.
In https://reviews.llvm.org/D24397#555057, @bjope wrote:
> This test/CodeGen/builtins-ppc-p9vector.c test will fail together with this
> upcoming LLVM patch https://reviews.llvm.org/D24955
>
> Problem is that lots of your
>
> add i64 {{.*}}, 64
>
> checks will fails s
nemanjai added a comment.
In https://reviews.llvm.org/D24397#555470, @spatel wrote:
> Having a clang regression/unit test that depends on optimizer behavior is
> generally viewed as wrong. Can the tests be split into front-end (clang)
> tests and separate tests for the IR optimizer? Both x86 an
Well, I don't know much about what Clang will actually do here, but I'll
follow your advice and add -O0 and pipe to opt -S -mem2reg. I'll also add a
test case in LLVM (test/CodeGen/PowerPC) that will test that after opt and
llc, we generate the desired code for these builtins.
Thanks Sanjay and Bj
OK, I get testing that I'm fine with if I remove the -O2 and the checks for
'select i1'.
Does that change suffice for the purposes of https://reviews.llvm.org/D24955
?
Namely, do I need to account for the possible addition of nsw/nuw flags to
the add instructions even without -O2?
On Wed, Oct 5,
OK, will remove optimization and the selects and commit this now.
Sorry about the delay.
On Wed, Oct 5, 2016 at 9:16 PM, Sanjay Patel wrote:
> You should not need to account for any nsw/nuw flags if the clang test
> does not enable the optimizer.
> Ie, D24955 should not be running at -O0.
>
> On
Author: nemanjai
Date: Wed Oct 5 14:11:36 2016
New Revision: 283363
URL: http://llvm.org/viewvc/llvm-project?rev=283363&view=rev
Log:
Removing optimization from the RUN lines and adjusting the checks
to not rely on optimization.
Modified:
cfe/trunk/test/CodeGen/builtins-ppc-p9vector.c
Modif
Committed revision 283363.
On Wed, Oct 5, 2016 at 9:18 PM, Nemanja Ivanovic
wrote:
> OK, will remove optimization and the selects and commit this now.
> Sorry about the delay.
>
> On Wed, Oct 5, 2016 at 9:16 PM, Sanjay Patel
> wrote:
>
>> You should not need to account for any nsw/nuw flags if
nemanjai wrote:
> @nemanjai I'm curious if you have an interest / need to support RVE or not?
I most certainly do. Thank you for alerting me to this PR.
https://github.com/llvm/llvm-project/pull/76777
___
cfe-commits mailing list
cfe-commits@lists.llv
https://github.com/nemanjai commented:
It is not my intent to hold up approval of this patch. In addition to the minor
comments I added, I plan to do some local testing but even if the testing
reveals issues, they can be fixed on subsequent commits.
https://github.com/llvm/llvm-project/pull/76
https://github.com/nemanjai edited
https://github.com/llvm/llvm-project/pull/76777
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
@@ -38,3 +40,14 @@ def CSR_XLEN_F32_Interrupt: CalleeSavedRegs<(add
CSR_Interrupt,
// Same as CSR_Interrupt, but including all 64-bit FP registers.
def CSR_XLEN_F64_Interrupt: CalleeSavedRegs<(add CSR_Interrupt,
(sequence "F%u_D", 0
@@ -83,13 +88,14 @@ RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction
*MF) const {
}
BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
+ const RISCVSubtarget &STI = MF.getSubtarget();
nemanjai wrote:
Why was this adde
@@ -985,9 +1003,10 @@ void
RISCVFrameLowering::determineCalleeSaves(MachineFunction &MF,
};
for (auto Reg : CSRegs)
- SavedRegs.set(Reg);
+ if (Reg < RISCV::X16 || !Subtarget.isRVE())
nemanjai wrote:
What happens if we are using `ilp32e/lp6
@@ -17,6 +17,13 @@ def HasStdExtZicsr :
Predicate<"Subtarget->hasStdExtZicsr()">,
AssemblerPredicate<(all_of FeatureStdExtZicsr),
"'Zicsr' (CSRs)">;
+def FeatureStdExtI
+: SubtargetFeature<"i", "HasStdExtI",
@@ -179,6 +180,11 @@ Assembly Support
Supported
Fully supported by the compiler. This includes everything in Assembly
Support, along with - if relevant - C language intrinsics for the instructions
and pattern matching by the compiler to recognize idiomatic patterns which ca
@@ -50,11 +50,14 @@ void RISCVTargetStreamer::setTargetABI(RISCVABI::ABI ABI) {
void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI,
bool EmitStackAlign) {
- if (STI.hasFeature(RISCV::FeatureRVE))
-repor
@@ -985,9 +1003,10 @@ void
RISCVFrameLowering::determineCalleeSaves(MachineFunction &MF,
};
for (auto Reg : CSRegs)
- SavedRegs.set(Reg);
+ if (Reg < RISCV::X16 || !Subtarget.isRVE())
nemanjai wrote:
Sounds good. Maybe just a little comment
https://github.com/nemanjai approved this pull request.
My comments have been addressed, so this LGTM. I'll of course defer to @asb and
@topperc for final approval.
https://github.com/llvm/llvm-project/pull/76777
___
cfe-commits mailing list
cfe-commi
https://github.com/nemanjai updated
https://github.com/llvm/llvm-project/pull/68919
>From 71f1352bf00d6a9eefa3f199859d47d093f272f8 Mon Sep 17 00:00:00 2001
From: Nemanja Ivanovic
Date: Thu, 12 Oct 2023 14:08:42 -0400
Subject: [PATCH 1/3] [PowerPC][X86] Make cpu id builtins target independent
a
@@ -2110,6 +2110,66 @@ static bool checkFPMathBuiltinElementType(Sema &S,
SourceLocation Loc,
return false;
}
+/// SemaBuiltinCpuSupports - Handle __builtin_cpu_supports(char *).
+/// This checks that the target supports __builtin_cpu_supports and
+/// that the string argum
@@ -0,0 +1,80 @@
+#ifndef PPC_FEATURE
nemanjai wrote:
Sounds good.
https://github.com/llvm/llvm-project/pull/68919
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo
@@ -1830,6 +1830,10 @@ void PPCLinuxAsmPrinter::emitEndOfAsmFile(Module &M) {
PPCTargetStreamer *TS =
static_cast(OutStreamer->getTargetStreamer());
+ if (static_cast(TM).hasGlibcHWCAPAccess())
nemanjai wrote:
Ha ha, more as in "any"?
https://github
@@ -1,11 +1,16 @@
-// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -emit-llvm < %s| FileCheck %s
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -emit-llvm < %s | FileCheck %s \
+// RUN: --check-prefix=CHECK-X86
+// RUN: %clang_cc1 -triple ppc64le-linux-gnu -emit-llvm < %s | File
@@ -210,6 +210,12 @@ let TargetPrefix = "ppc" in { // All intrinsics start
with "llvm.ppc.".
[llvm_float_ty],
[llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_vararg_ty],
[IntrNoMem]>;
+ // Load of a value provided by the system library
@@ -2110,6 +2110,66 @@ static bool checkFPMathBuiltinElementType(Sema &S,
SourceLocation Loc,
return false;
}
+/// SemaBuiltinCpuSupports - Handle __builtin_cpu_supports(char *).
+/// This checks that the target supports __builtin_cpu_supports and
+/// that the string argum
@@ -32,6 +32,7 @@ class PPCTargetMachine final : public LLVMTargetMachine {
std::unique_ptr TLOF;
PPCABI TargetABI;
Endian Endianness = Endian::NOT_DETECTED;
+ mutable bool HasGlibcHWCAPAccess = false;
nemanjai wrote:
Target machine is not modifiable wh
@@ -2110,6 +2110,66 @@ static bool checkFPMathBuiltinElementType(Sema &S,
SourceLocation Loc,
return false;
}
+/// SemaBuiltinCpuSupports - Handle __builtin_cpu_supports(char *).
+/// This checks that the target supports __builtin_cpu_supports and
+/// that the string argum
@@ -2110,6 +2110,66 @@ static bool checkFPMathBuiltinElementType(Sema &S,
SourceLocation Loc,
return false;
}
+/// SemaBuiltinCpuSupports - Handle __builtin_cpu_supports(char *).
+/// This checks that the target supports __builtin_cpu_supports and
+/// that the string argum
@@ -359,6 +359,13 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public
TargetInfo {
bool isSPRegName(StringRef RegName) const override {
return RegName.equals("r1") || RegName.equals("x1");
}
+
+ // We support __builtin_cpu_supports/__builtin_cpu_is on targets that
@@ -873,3 +873,17 @@ ArrayRef PPCTargetInfo::getTargetBuiltins()
const {
return llvm::ArrayRef(BuiltinInfo,
clang::PPC::LastTSBuiltin - Builtin::FirstTSBuiltin);
}
+
+bool PPCTargetInfo::validateCpuSupports(StringRef FeatureStr) const {
--
@@ -15,38 +20,57 @@ int main(void) {
if (__builtin_cpu_supports("sse4.2"))
a("sse4.2");
- // CHECK: [[LOAD:%[^ ]+]] = load i32, ptr getelementptr inbounds ({ i32,
i32, i32, [1 x i32] }, ptr @__cpu_model, i32 0, i32 3, i32 0)
- // CHECK: [[AND:%[^ ]+]] = and i32 [[LOAD
@@ -3124,6 +3125,36 @@ bool PPCInstrInfo::expandPostRAPseudo(MachineInstr &MI)
const {
.addReg(Reg);
return true;
}
+ case PPC::PPCLdFixedAddr: {
+assert(Subtarget.isTargetLinux() &&
+ "Only Linux target is expected to contain PPCLdFixedAddr");
+
@@ -15,38 +20,57 @@ int main(void) {
if (__builtin_cpu_supports("sse4.2"))
a("sse4.2");
- // CHECK: [[LOAD:%[^ ]+]] = load i32, ptr getelementptr inbounds ({ i32,
i32, i32, [1 x i32] }, ptr @__cpu_model, i32 0, i32 3, i32 0)
- // CHECK: [[AND:%[^ ]+]] = and i32 [[LOAD
@@ -2110,6 +2110,66 @@ static bool checkFPMathBuiltinElementType(Sema &S,
SourceLocation Loc,
return false;
}
+/// SemaBuiltinCpuSupports - Handle __builtin_cpu_supports(char *).
+/// This checks that the target supports __builtin_cpu_supports and
+/// that the string argum
nemanjai wrote:
> > Individual implementations will provide different sets of CSR's and need a
> > way to read/write them. Of course, this can be done with inline asm, but
> > doing such things with inline asm has its limitations (no error checking,
>
> Wouldn't the assembler error check the c
nemanjai wrote:
> I have always been unconvinced that these are a good idea to have / add
> significant value over using inline assembly. IIRC Arm has them but nobody
> uses them?
Is this a comment about the general concept of builtins to produce specific
instructions or about these specific
@@ -20,6 +20,12 @@ class RISCVBuiltin :
TargetBuiltin {
let Attributes = [NoThrow, Const] in {
//===--===//
+// Zicsr extension.
+//===--==
@@ -74,6 +74,21 @@ let TargetPrefix = "riscv" in {
} // TargetPrefix = "riscv"
+let TargetPrefix = "riscv" in {
+ // Zicsr
+ def int_riscv_csrr :
+DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty],
+ [IntrNoMem, IntrHasSideEffects,
ImmArg>]>;
https://github.com/nemanjai closed
https://github.com/llvm/llvm-project/pull/85063
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
nemanjai wrote:
Ah, I missed the fact that there is an option `-riscv-add-build-attributes`
that the clang driver passes when invoking `cc1as`. Perhaps that option should
default to `true`? Thanks and sorry for the noise.
https://github.com/llvm/llvm-project/pull/85063
___
nemanjai wrote:
> > > I have always been unconvinced that these are a good idea to have / add
> > > significant value over using inline assembly. IIRC Arm has them but
> > > nobody uses them?
...
> If it’s not a constant integer for inline assembly then how would it
> magically be a constant
nemanjai wrote:
> You can just use `({ ... })` to achieve that same goal with inline assembly
> (and write doesn't even need that, you can do it with a single statement).
> I'm not convinced the intrinsics gain you anything.
Hmm... I think there's a bit of a disconnect here between the point I
nemanjai wrote:
> > Should we use strings like ARM does so we can get register by name?
>
> Good point! We may provide two kinds of builtins: one by name, and another by
> CSR number. We should continue @lenary's proposal and discuss it in
> https://github.com/riscv-non-isa/riscv-toolchain-con
https://github.com/nemanjai commented:
Do we really want to support only `__builtin_cpu_is` on AIX? It doesn't seem
like this would achieve the desired goal. Most users will use these builtins to
test for some capability on the target machine. It almost never really matters
to a user whether t
https://github.com/nemanjai edited
https://github.com/llvm/llvm-project/pull/80069
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
@@ -10347,6 +10347,8 @@ def err_x86_builtin_tile_arg_duplicate : Error<
def err_builtin_target_unsupported : Error<
"builtin is not supported on this target">;
+def err_builtin_aix_os_unsupported : Error<
+ "this builtin is available only in AIX 7.2 and later operating syst
@@ -16542,22 +16542,75 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
Intrinsic::ID ID = Intrinsic::not_intrinsic;
+#include "llvm/TargetParser/PPCTargetParser.def"
nemanjai wrote:
This is getting a bit tangled. Can you please provide t
@@ -362,8 +362,18 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public
TargetInfo {
// We support __builtin_cpu_supports/__builtin_cpu_is on targets that
// have Glibc since it is Glibc that provides the HWCAP[2] in the auxv.
+#define MINIMUM_AIX_OS_MAJOR 7
---
@@ -16542,22 +16542,75 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
Intrinsic::ID ID = Intrinsic::not_intrinsic;
+#include "llvm/TargetParser/PPCTargetParser.def"
+ auto GetOpRes = [&](Value *FieldValue, unsigned Mask, unsigned Op,
+
@@ -16542,22 +16542,75 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
Intrinsic::ID ID = Intrinsic::not_intrinsic;
+#include "llvm/TargetParser/PPCTargetParser.def"
+ auto GetOpRes = [&](Value *FieldValue, unsigned Mask, unsigned Op,
+
@@ -2540,6 +2540,10 @@ def ffp_contract : Joined<["-"], "ffp-contract=">,
Group,
HelpText<"Form fused FP ops (e.g. FMAs)">,
Values<"fast,on,off,fast-honor-pragmas">;
+def fcomplex_ppc_gnu_abi : Flag<["-"], "fcomplex-ppc-gnu-abi">,
Group, Visibility<[ClangOption, CC1Optio
@@ -78,6 +78,13 @@ class CodeGenOptions : public CodeGenOptionsBase {
SRCK_InRegs// Small structs in registers (-freg-struct-return).
};
+ enum ComplexArgumentConventionKind {
+CMPLX_Default,
+CMPLX_OnStack,
+CMPLX_OnGPR, // if ppc32 -fcomplex-ppc-gnu-ab
@@ -486,7 +486,8 @@ std::unique_ptr
createAIXTargetCodeGenInfo(CodeGenModule &CGM, bool Is64Bit);
std::unique_ptr
-createPPC32TargetCodeGenInfo(CodeGenModule &CGM, bool SoftFloatABI);
+createPPC32TargetCodeGenInfo(CodeGenModule &CGM, bool SoftFloatABI,
+
nemanjai wrote:
My review is not complete, I just submitted what I have so far so at least we
can get started on answering the questions I have so far.
https://github.com/llvm/llvm-project/pull/77732
___
cfe-commits mailing list
cfe-commits@lists.llvm
@@ -141,23 +149,30 @@ PPC_LNX_CPU("power10",47)
#define AIX_BUILTIN_PPC_TRUE 1
#define AIX_BUILTIN_PPC_FALSE 0
#define USE_SYS_CONF 2
+ #define SYS_CALL 3
// Supported COMPARE_OP values.
#define COMP_EQ 0
+ #define COMP_GT 1
+ #define COMP_GE 2
+ #define COMP
@@ -16570,32 +16570,72 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
#include "llvm/TargetParser/PPCTargetParser.def"
auto GenAIXPPCBuiltinCpuExpr = [&](unsigned SupportMethod, unsigned FieldIdx,
nemanjai wrote:
This is now a very large
@@ -0,0 +1,171 @@
+// RUN: echo "int main() { return __builtin_cpu_supports(\"4xxmac\");}" > %t.c
nemanjai wrote:
This is an interesting way of testing, where we create each test on the fly. I
am not against it if it works on all platforms (including Windows). H
@@ -141,23 +149,30 @@ PPC_LNX_CPU("power10",47)
#define AIX_BUILTIN_PPC_TRUE 1
#define AIX_BUILTIN_PPC_FALSE 0
#define USE_SYS_CONF 2
+ #define SYS_CALL 3
// Supported COMPARE_OP values.
#define COMP_EQ 0
+ #define COMP_GT 1
+ #define COMP_GE 2
+ #define COMP
@@ -364,7 +364,14 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public
TargetInfo {
// have Glibc since it is Glibc that provides the HWCAP[2] in the auxv.
static constexpr int MINIMUM_AIX_OS_MAJOR = 7;
static constexpr int MINIMUM_AIX_OS_MINOR = 2;
- bool supportsCp
https://github.com/nemanjai created
https://github.com/llvm/llvm-project/pull/85063
In order to make assembly programming more convenient, emit macro
__riscv_cmdline_arch_string that will be defined to the arch string based on
the command line arguments. This string may differ from the actual
https://github.com/nemanjai edited
https://github.com/llvm/llvm-project/pull/85063
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
nemanjai wrote:
This is a suggestion born out of a request from a user to have a way to emit
the ISA attributes into objects produced from pre-processed asm files. Perhaps
there is already a method to do this that I'm not aware of, but if not, I think
this is a convenient and lightweight way t
https://github.com/nemanjai created
https://github.com/llvm/llvm-project/pull/85091
To facilitate proper range checking and better error messages if an attempt is
made to call these with non-litaral arguments, we provide builtins to emit the
read/write CSR instructions.
>From 543086dd6a208527
nemanjai wrote:
Individual implementations will provide different sets of CSR's and need a way
to read/write them. Of course, this can be done with inline asm, but doing such
things with inline asm has its limitations (no error checking, if a user
attempts to wrap the asm in a function, they w
nemanjai wrote:
Sorry, I'll put up a patch for review shortly to fix this problem.
https://github.com/llvm/llvm-project/pull/68919
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
https://github.com/nemanjai created
https://github.com/llvm/llvm-project/pull/80058
My recent commit (67c1c1d) made the CPU ID builtins target-independent so they
can be used on PPC as well. However, that had the unintended consequence of
changing the behaviour of __has_builtin in that it repo
nemanjai wrote:
Fix in https://github.com/llvm/llvm-project/pull/80058
https://github.com/llvm/llvm-project/pull/68919
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
https://github.com/nemanjai closed
https://github.com/llvm/llvm-project/pull/80058
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
@@ -210,6 +210,15 @@ let TargetPrefix = "ppc" in { // All intrinsics start
with "llvm.ppc.".
[llvm_float_ty],
[llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_vararg_ty],
[IntrNoMem]>;
+ // Load of a value provided by the system library
@@ -16086,6 +16086,41 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
switch (BuiltinID) {
default: return nullptr;
+ case Builtin::BI__builtin_cpu_is: {
+const Expr *CPUExpr = E->getArg(0)->IgnoreParenCasts();
+StringRef CPUStr = cast(CPUExpr)-
@@ -359,6 +359,13 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public
TargetInfo {
bool isSPRegName(StringRef RegName) const override {
return RegName.equals("r1") || RegName.equals("x1");
}
+
+ // We support __builtin_cpu_supports/__builtin_cpu_is on targets that
https://github.com/nemanjai updated
https://github.com/llvm/llvm-project/pull/68919
>From 65c84f2ba78efcbf92ce9c8232fc40f493414930 Mon Sep 17 00:00:00 2001
From: Nemanja Ivanovic
Date: Thu, 12 Oct 2023 14:08:42 -0400
Subject: [PATCH 1/5] [PowerPC][X86] Make cpu id builtins target independent
a
@@ -2110,6 +2110,66 @@ static bool checkFPMathBuiltinElementType(Sema &S,
SourceLocation Loc,
return false;
}
+/// SemaBuiltinCpuSupports - Handle __builtin_cpu_supports(char *).
+/// This checks that the target supports __builtin_cpu_supports and
+/// that the string argum
https://github.com/nemanjai updated
https://github.com/llvm/llvm-project/pull/68919
>From 71f1352bf00d6a9eefa3f199859d47d093f272f8 Mon Sep 17 00:00:00 2001
From: Nemanja Ivanovic
Date: Thu, 12 Oct 2023 14:08:42 -0400
Subject: [PATCH 1/4] [PowerPC][X86] Make cpu id builtins target independent
a
Author: Nemanja Ivanovic
Date: 2020-09-15T12:36:47-05:00
New Revision: 3bc3983f229f9277d5bea3692b691f72ab8740dd
URL:
https://github.com/llvm/llvm-project/commit/3bc3983f229f9277d5bea3692b691f72ab8740dd
DIFF:
https://github.com/llvm/llvm-project/commit/3bc3983f229f9277d5bea3692b691f72ab8740dd.di
Author: Nemanja Ivanovic
Date: 2020-09-04T13:56:39-04:00
New Revision: 54205f0bd2377503b818d7f62cc4ed63ef5b1e94
URL:
https://github.com/llvm/llvm-project/commit/54205f0bd2377503b818d7f62cc4ed63ef5b1e94
DIFF:
https://github.com/llvm/llvm-project/commit/54205f0bd2377503b818d7f62cc4ed63ef5b1e94.di
Author: Nemanja Ivanovic
Date: 2020-09-04T21:48:38-04:00
New Revision: 2d652949be4b772f2c11577621b0ad33052ac844
URL:
https://github.com/llvm/llvm-project/commit/2d652949be4b772f2c11577621b0ad33052ac844
DIFF:
https://github.com/llvm/llvm-project/commit/2d652949be4b772f2c11577621b0ad33052ac844.di
Author: Nemanja Ivanovic
Date: 2021-05-13T04:56:56-05:00
New Revision: 39e4676ca798d9aba58823515ac9d48eb64863be
URL:
https://github.com/llvm/llvm-project/commit/39e4676ca798d9aba58823515ac9d48eb64863be
DIFF:
https://github.com/llvm/llvm-project/commit/39e4676ca798d9aba58823515ac9d48eb64863be.di
Author: Nemanja Ivanovic
Date: 2021-05-14T08:02:00-05:00
New Revision: 7cd2833311ab614775bc695e7bb808159a02e2a9
URL:
https://github.com/llvm/llvm-project/commit/7cd2833311ab614775bc695e7bb808159a02e2a9
DIFF:
https://github.com/llvm/llvm-project/commit/7cd2833311ab614775bc695e7bb808159a02e2a9.di
Author: Nemanja Ivanovic
Date: 2021-09-23T18:24:39-05:00
New Revision: 76d845cb169f048cb6f2176c3e7a6534dc5af097
URL:
https://github.com/llvm/llvm-project/commit/76d845cb169f048cb6f2176c3e7a6534dc5af097
DIFF:
https://github.com/llvm/llvm-project/commit/76d845cb169f048cb6f2176c3e7a6534dc5af097.di
Author: Nemanja Ivanovic
Date: 2021-09-29T06:14:45-05:00
New Revision: c9539f957f57c0c2c59dab98f25215f241d4debf
URL:
https://github.com/llvm/llvm-project/commit/c9539f957f57c0c2c59dab98f25215f241d4debf
DIFF:
https://github.com/llvm/llvm-project/commit/c9539f957f57c0c2c59dab98f25215f241d4debf.di
Author: Nemanja Ivanovic
Date: 2021-09-29T06:34:31-05:00
New Revision: 09b67aa1c38279daa54246e3f216186e35a3e5b9
URL:
https://github.com/llvm/llvm-project/commit/09b67aa1c38279daa54246e3f216186e35a3e5b9
DIFF:
https://github.com/llvm/llvm-project/commit/09b67aa1c38279daa54246e3f216186e35a3e5b9.di
Author: Nemanja Ivanovic
Date: 2021-09-30T05:58:22-05:00
New Revision: fad14a17a490b1825b0c7c40ace7e83c91af4b8a
URL:
https://github.com/llvm/llvm-project/commit/fad14a17a490b1825b0c7c40ace7e83c91af4b8a
DIFF:
https://github.com/llvm/llvm-project/commit/fad14a17a490b1825b0c7c40ace7e83c91af4b8a.di
Author: Nemanja Ivanovic
Date: 2021-10-01T08:27:15-05:00
New Revision: 369d785574f5a22c086d0c40268a39a64bdd7217
URL:
https://github.com/llvm/llvm-project/commit/369d785574f5a22c086d0c40268a39a64bdd7217
DIFF:
https://github.com/llvm/llvm-project/commit/369d785574f5a22c086d0c40268a39a64bdd7217.di
Author: Nemanja Ivanovic
Date: 2021-06-24T18:42:44-05:00
New Revision: ef906573a127cffef7cae75d5155c15a8a2a3a5e
URL:
https://github.com/llvm/llvm-project/commit/ef906573a127cffef7cae75d5155c15a8a2a3a5e
DIFF:
https://github.com/llvm/llvm-project/commit/ef906573a127cffef7cae75d5155c15a8a2a3a5e.di
Author: Nemanja Ivanovic
Date: 2021-07-30T14:37:24-05:00
New Revision: 9019b55b605a26cb5389399eceb34fa9ea0f
URL:
https://github.com/llvm/llvm-project/commit/9019b55b605a26cb5389399eceb34fa9ea0f
DIFF:
https://github.com/llvm/llvm-project/commit/9019b55b605a26cb5389399eceb34fa9ea0f.di
1 - 100 of 213 matches
Mail list logo
