[clang] [clang-repl] Typo within InterpreterTest.cpp (PR #79119)

https://github.com/nasherm closed https://github.com/llvm/llvm-project/pull/79119 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang-repl] Typo within InterpreterTest.cpp (PR #79119)

nasherm wrote: Need to follow proper contribution process. So closing for now https://github.com/llvm/llvm-project/pull/79119 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang-repl] Typo within InterpreterTest.cpp (PR #79119)

https://github.com/nasherm created https://github.com/llvm/llvm-project/pull/79119 Recent changes to InterpreterTest.cpp (https://github.com/llvm/llvm-project/pull/76218) introduced typos within code passed to a Parse() function. This causes some tests to fail, namely IncrementalProcessing.In

[clang] [llvm] Add support for Armv9.6-A memory systems extensions (PR #112341)

https://github.com/nasherm created https://github.com/llvm/llvm-project/pull/112341 Add support for the following Armv9.6-A memory systems extensions: FEAT_LSUI - Unprivileged Load Store FEAT_OCCMO - Outer Cacheable Cache Maintenance Operation FEAT_PCDPHINT - Producer-Consumer Da

[clang] [llvm] [LLVM][MC][AArch64support for Armv9.6-A memory systems extensions (PR #112341)

https://github.com/nasherm edited https://github.com/llvm/llvm-project/pull/112341 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

https://github.com/nasherm edited https://github.com/llvm/llvm-project/pull/112341 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

https://github.com/nasherm updated https://github.com/llvm/llvm-project/pull/112341 >From a20ed3469726b53d0bff59710ad367766e839a45 Mon Sep 17 00:00:00 2001 From: Nashe Mncube Date: Fri, 4 Oct 2024 10:22:10 +0100 Subject: [PATCH] Add support for Armv9.6-A memory systems extensions Add support f

[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

@@ -4769,6 +4843,109 @@ class LoadExclusivePair sz, bit o2, bit L, bit o1, bit o0, let PostEncoderMethod = "fixLoadStoreExclusive<0,1>"; } +// Armv9.6-a load-store exclusive instructions +let hasSideEffects = 1, mayLoad = 1, mayStore = 1 in +class BaseLoadStoreExclusiveLSUI

[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

@@ -0,0 +1,14 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+occmo -mattr=+mte < %s | FileCheck %s nasherm wrote: Done https://github.com/llvm/llvm-project

[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

nasherm wrote: > Thank you for the work @nasherm . I left some comments. I am not sure if all > of them proceed. Carol Thank you for the review. I'm not sure about the instruction alias suggestions. I would've thought that although these instructions are equivalent the different execution con

[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

@@ -988,6 +988,22 @@ bool AArch64InstPrinter::printSysAlias(const MCInst *MI, Name = std::string(AT->Name); } break; +// Overlaps with AT and DC nasherm wrote: Yeah. These are for the newly introduced DC instructions https://github.com/llvm/

[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

https://github.com/nasherm edited https://github.com/llvm/llvm-project/pull/112341 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

@@ -0,0 +1,12 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+pcdphint %s | FileCheck %s nasherm wrote: Done https://github.com/llvm/llvm-project/pull/112341 _

[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

@@ -0,0 +1,395 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py nasherm wrote: Done https://github.com/llvm/llvm-project/pull/112341 ___ cfe-commits mailing list cfe-commits@lists.llvm.

[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

@@ -4020,6 +4079,33 @@ defm STNPD : StorePairNoAlloc<0b01, 1, FPR64Op, simm7s8, "stnp">; defm STNPQ : StorePairNoAlloc<0b10, 1, FPR128Op, simm7s16, "stnp">; } +// Armv9.6-a Load/store no-allocate pair (FEAT_LSUI) nasherm wrote: Thanks. Done https://github.c

[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

@@ -3736,6 +3776,8 @@ static const struct Extension { {"sme-fa64", {AArch64::FeatureSMEFA64}}, {"cpa", {AArch64::FeatureCPA}}, {"tlbiw", {AArch64::FeatureTLBIW}}, +{"lsui", {AArch64::FeatureLSUI}}, +{"occmo", {AArch64::FeatureOCCMO}}, nasher

[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

@@ -0,0 +1,395 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +// RUN: llvm-mc -triple aarch64 -mattr=+lsui -show-encoding %s | FileCheck %s nasherm wrote: Done https://github.com/llvm/llvm-project/pull/112341

[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

@@ -4020,6 +4079,33 @@ defm STNPD : StorePairNoAlloc<0b01, 1, FPR64Op, simm7s8, "stnp">; defm STNPQ : StorePairNoAlloc<0b10, 1, FPR128Op, simm7s16, "stnp">; } +// Armv9.6-a Load/store no-allocate pair (FEAT_LSUI) +let Predicates = [HasLSUI] in { + defm LDTP: LoadPairOffs

[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

@@ -4660,6 +4746,21 @@ let Predicates = [HasLOR] in { def STLLRH0 : InstAlias<"stllrh\t$Rt, [$Rn, #0]", (STLLRH GPR32: $Rt, GPR64sp:$Rn)>; } +// v9.6-a Unprivileged load store operations +let Predicates = [HasLSUI] in { +defm LDTXRW : LoadUnprivilegedLSUI<0b10, GPR32, "l

[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

@@ -4660,6 +4746,21 @@ let Predicates = [HasLOR] in { def STLLRH0 : InstAlias<"stllrh\t$Rt, [$Rn, #0]", (STLLRH GPR32: $Rt, GPR64sp:$Rn)>; } +// v9.6-a Unprivileged load store operations +let Predicates = [HasLSUI] in { +defm LDTXRW : LoadUnprivilegedLSUI<0b10, GPR32, "l

[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

@@ -4660,6 +4746,21 @@ let Predicates = [HasLOR] in { def STLLRH0 : InstAlias<"stllrh\t$Rt, [$Rn, #0]", (STLLRH GPR32: $Rt, GPR64sp:$Rn)>; } +// v9.6-a Unprivileged load store operations +let Predicates = [HasLSUI] in { +defm LDTXRW : LoadUnprivilegedLSUI<0b10, GPR32, "l

[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

@@ -2568,12 +2580,59 @@ defm CASPA : CompareAndSwapPair<1, 0, "a">; defm CASPL : CompareAndSwapPair<0, 1, "l">; defm CASPAL : CompareAndSwapPair<1, 1, "al">; +// v9.6-a atomic CAST nasherm wrote: Done https://github.com/llvm/llvm-project/pull/112341 __

[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

@@ -4660,6 +4746,21 @@ let Predicates = [HasLOR] in { def STLLRH0 : InstAlias<"stllrh\t$Rt, [$Rn, #0]", (STLLRH GPR32: $Rt, GPR64sp:$Rn)>; } +// v9.6-a Unprivileged load store operations +let Predicates = [HasLSUI] in { +defm LDTXRW : LoadUnprivilegedLSUI<0b10, GPR32, "l

[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

nasherm wrote: @CarolineConcatto I hope I answered your question. If so I'm hoping to merge this by EOD if there's no more to do https://github.com/llvm/llvm-project/pull/112341 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llv

[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

@@ -988,6 +988,22 @@ bool AArch64InstPrinter::printSysAlias(const MCInst *MI, Name = std::string(AT->Name); } break; +// Overlaps with AT and DC nasherm wrote: The newly added DC instructions map to the same case (15) as the AT instructions

[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

https://github.com/nasherm closed https://github.com/llvm/llvm-project/pull/112341 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits