@@ -1989,6 +1989,14 @@ llvm::Value *CodeGenFunction::EmitLoadOfScalar(Address
Addr, bool Volatile,
return EmitAtomicLoad(AtomicLValue, Loc).getScalarVal();
}
+ if (const auto *BIT = Ty->getAs()) {
+if (BIT->getNumBits() > 128) {
+ // Long _BitInt has array of
@@ -1989,6 +1989,14 @@ llvm::Value *CodeGenFunction::EmitLoadOfScalar(Address
Addr, bool Volatile,
return EmitAtomicLoad(AtomicLValue, Loc).getScalarVal();
}
+ if (const auto *BIT = Ty->getAs()) {
+if (BIT->getNumBits() > 128) {
+ // Long _BitInt has array of
@@ -674,3 +674,26 @@ let TargetGuard = "sme2" in {
def SVLUTI2_LANE_ZT_X2 : Inst<"svluti2_lane_zt_{d}_x2", "2.di[i",
"cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt_x2", [IsStreaming,
IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_7>]>;
def SVLUTI4_LANE_Z
https://github.com/momchil-velikov approved this pull request.
https://github.com/llvm/llvm-project/pull/88710
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
https://github.com/momchil-velikov approved this pull request.
https://github.com/llvm/llvm-project/pull/88499
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
https://github.com/momchil-velikov edited
https://github.com/llvm/llvm-project/pull/88553
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/88105
>From 2b0befb9078f8c9116ad52be937c8722045708ef Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 9 Apr 2024 10:52:41 +0100
Subject: [PATCH 1/2] [AArch64] Add intrinsics for non-widening FMOPA/FMOP
@@ -286,14 +286,26 @@ multiclass sme_outer_product_fp64
def : SME_ZA_Tile_TwoPred_TwoVec_Pat;
}
-multiclass sme2p1_fmop_tile_fp16 op,
ZPRRegOp zpr_ty>{
- def NAME : sme_fp_outer_product_inst {
+multiclass sme2p1_fmop_tile_f8f16 op> {
+ def NAME : sme_fp_outer_product_inst
@@ -1985,6 +1986,34 @@ void AArch64DAGToDAGISel::SelectMultiVectorMove(SDNode
*N, unsigned NumVecs,
CurDAG->RemoveDeadNode(N);
}
+template
+void AArch64DAGToDAGISel::SelectMultiVectorMoveZ(SDNode *N, unsigned NumVecs,
momchil-velikov wrote:
The real quest
@@ -458,6 +458,40 @@ let TargetGuard = "sme2,sme-f64f64" in {
def SVMLS_LANE_VG1x4_F64 : Inst<"svmls_lane_za64[_{d}]_vg1x4", "vm4di", "d",
MergeNone, "aarch64_sme_fmls_lane_vg1x4", [IsStreaming, IsInOutZA],
[ImmCheck<3, ImmCheck0_1>]>;
}
+let TargetGuard = "sme2p1,sme-f16f
https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/100608
None
>From bd2814249f922206e8648d58d2850f89afad4fd8 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Thu, 25 Jul 2024 18:25:40 +0100
Subject: [PATCH] [AArch64] Implement FP8 floating-point mode help
@@ -2385,3 +2385,8 @@ let SVETargetGuard = "sve2p1", SMETargetGuard = "sme2" in
{
def SVBFMLSLB_LANE : SInst<"svbfmlslb_lane[_{d}]", "dd$$i", "f", MergeNone,
"aarch64_sve_bfmlslb_lane", [IsOverloadNone, VerifyRuntimeMode], [ImmCheck<3,
ImmCheck0_7>]>;
def SVBFMLSLT_LANE :
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/99041
>From 8e0aba5bcfd0a5f861c9ebb30a28c05eb0d6dcf5 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 15 Jul 2024 17:50:43 +0100
Subject: [PATCH 1/2] [AArch64] Implement NEON vamin/vamax intrinsics
Th
@@ -5985,6 +5985,26 @@ multiclass SIMDThreeSameVectorFP
opc,
[(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
}
+let mayRaiseFPException = 1, Uses = [FPCR] in
+multiclass SIMDThreeVectorFP opc,
momchil-velikov wrote:
Removed.
momchil-velikov wrote:
> Did you consider emitting `llvm.fmin(llvm.fabs(x), llvm.fabs(y))`?
Nope. I'll have a look.
https://github.com/llvm/llvm-project/pull/99041
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/
https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/99063
This patch implements these intrinsics:
``` c
// Variants are also available for:
// [_f32_x2], [_f64_x2],
// [_f16_x4], [_f32_x4], [_f64_x4]
svfloat16x2_t svamax[_f16_x2](svfloat16x2 zd, svfloa
@@ -2832,6 +2832,23 @@ AArch64TargetLowering::EmitTileLoad(unsigned Opc,
unsigned BaseReg,
return BB;
}
+MachineBasicBlock *
+AArch64TargetLowering::EmitTileMovaz(unsigned Opc, unsigned BaseReg,
momchil-velikov wrote:
This function looks almost identical t
@@ -104,6 +104,13 @@ class sme2_move_to_tile_pseudo
+: SMEPseudo2Instr,
momchil-velikov wrote:
This is not needed.
https://github.com/llvm/llvm-project/pull/88499
___
cfe-commits mailing list
cfe-commits@lists.llvm
https://github.com/momchil-velikov edited
https://github.com/llvm/llvm-project/pull/88499
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
@@ -3387,7 +3387,7 @@ let TargetPrefix = "aarch64" in {
// Multi-vector floating point min/max number
//
- foreach instr = ["fmaxnm", "fminnm"] in {
+ foreach instr = ["fmaxnm", "bfmaxnm", "fminnm", "bfminnm"] in {
momchil-velikov wrote:
Likewise here.
@@ -3373,7 +3373,7 @@ let TargetPrefix = "aarch64" in {
// Multi-vector min/max
//
- foreach ty = ["f", "s", "u"] in {
+ foreach ty = ["bf", "f", "s", "u"] in {
momchil-velikov wrote:
You could just omit that part. Then the `bfloat` intrinsics would use
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/88266
>From 09167c5df2b50476a5073ff2e527503d090e7995 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Wed, 10 Apr 2024 11:25:50 +0100
Subject: [PATCH] [AArch64] Add intrinsics for multi-vector to ZA array v
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/88105
>From 3ea7ee0aaf7f8be8c2ee42af92ba3b13b8212645 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 9 Apr 2024 10:52:41 +0100
Subject: [PATCH 1/2] [AArch64] Add intrinsics for non-widening FMOPA/FMOP
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/88105
>From 3ea7ee0aaf7f8be8c2ee42af92ba3b13b8212645 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 9 Apr 2024 10:52:41 +0100
Subject: [PATCH 1/3] [AArch64] Add intrinsics for non-widening FMOPA/FMOP
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/88266
>From cafe0a8b70ad0189b638ec377e7d8cba9e786ecb Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Wed, 10 Apr 2024 11:25:50 +0100
Subject: [PATCH] [AArch64] Add intrinsics for multi-vector to ZA array v
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/88105
>From 74ee4857a76bc7eb5353dc22311e766ec5356514 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 9 Apr 2024 10:52:41 +0100
Subject: [PATCH 1/3] [AArch64] Add intrinsics for non-widening FMOPA/FMOP
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/99041
>From 87f1a5aa2215a9fbc1bde7905b2fd5e8d5ff859a Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 15 Jul 2024 17:50:43 +0100
Subject: [PATCH 1/2] [AArch64] Implement NEON vamin/vamax intrinsics
Th
@@ -135,6 +135,8 @@ enum NodeType : unsigned {
UDIV_PRED,
UMAX_PRED,
UMIN_PRED,
+ FAMAX_PRED,
+ FAMIN_PRED,
momchil-velikov wrote:
How about:
```
case Intrinsic::aarch64_sve_fmin_u:
return DAG.getNode(AArch64ISD::FMIN_PRED, SDLoc(N), N->getValueT
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/99042
>From aa74d04751558f3ab47d566c91fb8ad178df0dce Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 16 Jul 2024 13:37:34 +0100
Subject: [PATCH 1/2] [AArch64] Implement intrinsics for SVE FAMIN/FAMAX
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/99042
>From aa74d04751558f3ab47d566c91fb8ad178df0dce Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 16 Jul 2024 13:37:34 +0100
Subject: [PATCH 1/3] [AArch64] Implement intrinsics for SVE FAMIN/FAMAX
@@ -717,6 +717,11 @@ let Predicates = [HasSVEorSME] in {
defm FDIV_ZPZZ : sve_fp_bin_pred_hfd;
} // End HasSVEorSME
+let Predicates = [HasSVE2orSME2, HasFAMINMAX] in {
+ defm FAMAX_ZPZZ : sve_fp_bin_pred_hfd;
+ defm FAMIN_ZPZZ : sve_fp_bin_pred_hfd;
+}
+
@@ -0,0 +1,115 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc -mattr=+sve2 < %s | FileCheck %s
+; RUN: llc -mattr=+sme2 -force-streaming < %s | FileCheck %s
+
+target triple = "aarch64-linux"
+
+define @famin_f
@@ -2142,85 +2178,58 @@ void NeonEmitter::genOverloadTypeCheckCode(raw_ostream
&OS,
OS << "#endif\n\n";
}
-void NeonEmitter::genIntrinsicRangeCheckCode(raw_ostream &OS,
-SmallVectorImpl &Defs) {
- OS << "#ifdef GET_NEON_IMMEDIATE_CHE
@@ -403,142 +369,183 @@ enum ArmSMEState : unsigned {
ArmZT0Mask = 0b11 << 2
};
+bool SemaARM::CheckImmediateArg(CallExpr *TheCall, unsigned CheckTy,
+unsigned ArgIdx, unsigned EltBitWidth,
+unsigned VecBitWidth
@@ -2142,85 +2178,58 @@ void NeonEmitter::genOverloadTypeCheckCode(raw_ostream
&OS,
OS << "#endif\n\n";
}
-void NeonEmitter::genIntrinsicRangeCheckCode(raw_ostream &OS,
-SmallVectorImpl &Defs) {
- OS << "#ifdef GET_NEON_IMMEDIATE_CHE
@@ -2142,85 +2178,58 @@ void NeonEmitter::genOverloadTypeCheckCode(raw_ostream
&OS,
OS << "#endif\n\n";
}
-void NeonEmitter::genIntrinsicRangeCheckCode(raw_ostream &OS,
-SmallVectorImpl &Defs) {
- OS << "#ifdef GET_NEON_IMMEDIATE_CHE
@@ -403,142 +369,183 @@ enum ArmSMEState : unsigned {
ArmZT0Mask = 0b11 << 2
};
+bool SemaARM::CheckImmediateArg(CallExpr *TheCall, unsigned CheckTy,
+unsigned ArgIdx, unsigned EltBitWidth,
+unsigned VecBitWidth
@@ -403,6 +408,38 @@ class Intrinsic {
(Type.isScalar() && Type.isHalf()))
UseMacro = true;
}
+
+int ArgIdx, Kind, TypeArgIdx;
+std::vector ImmCheckList = R->getValueAsListOfDefs("ImmChecks");
+for (const auto *I : ImmCheckList) {
+ unsign
@@ -37,15 +37,20 @@ class SemaARM : public SemaBase {
/// flags. Do Sema checks for the runtime mode.
};
+ bool CheckImmediateArg(CallExpr *TheCall, unsigned CheckTy, unsigned ArgIdx,
+ unsigned EltBitWidth, unsigned VecBi
@@ -37,15 +37,20 @@ class SemaARM : public SemaBase {
/// flags. Do Sema checks for the runtime mode.
};
+ bool CheckImmediateArg(CallExpr *TheCall, unsigned CheckTy, unsigned ArgIdx,
+ unsigned EltBitWidth, unsigned VecBi
@@ -403,142 +369,183 @@ enum ArmSMEState : unsigned {
ArmZT0Mask = 0b11 << 2
};
+bool SemaARM::CheckImmediateArg(CallExpr *TheCall, unsigned CheckTy,
+unsigned ArgIdx, unsigned EltBitWidth,
+unsigned VecBitWidth
@@ -1541,8 +1528,9 @@ void SVEEmitter::createRangeChecks(raw_ostream &OS) {
OS << "case SVE::BI__builtin_sve_" << Def->getMangledName() << ":\n";
for (auto &Check : Def->getImmChecks())
- OS << "ImmChecks.push_back(std::make_tuple(" << Check.getArg() << ", "
-
@@ -2142,85 +2178,58 @@ void NeonEmitter::genOverloadTypeCheckCode(raw_ostream
&OS,
OS << "#endif\n\n";
}
-void NeonEmitter::genIntrinsicRangeCheckCode(raw_ostream &OS,
-SmallVectorImpl &Defs) {
- OS << "#ifdef GET_NEON_IMMEDIATE_CHE
@@ -1210,18 +1196,19 @@ void SVEEmitter::createIntrinsic(
// Collate a list of range/option checks for the immediates.
SmallVector ImmChecks;
for (auto *R : ImmCheckList) {
- int64_t Arg = R->getValueAsInt("Arg");
- int64_t EltSizeArg = R->getValueAsInt("E
@@ -2142,85 +2178,58 @@ void NeonEmitter::genOverloadTypeCheckCode(raw_ostream
&OS,
OS << "#endif\n\n";
}
-void NeonEmitter::genIntrinsicRangeCheckCode(raw_ostream &OS,
-SmallVectorImpl &Defs) {
- OS << "#ifdef GET_NEON_IMMEDIATE_CHE
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/100608
>From 17964507593a4ae3d2b13c4fe84500472705485f Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Thu, 25 Jul 2024 18:25:40 +0100
Subject: [PATCH 1/2] [AArch64] Implement FP8 floating-point mode helper
momchil-velikov wrote:
> > * passing `__arm_fpm_init()` as the `__fpm` to these CodeGen tests cannot
> > check whether the correct value is used to zero-out the target bits.
>
> Good point, in the tests where we set a field to zero we should start with a
> non-zero in that field.
Tweaked the
@@ -1774,6 +1774,18 @@ llvm::Constant
*ConstantEmitter::emitForMemory(CodeGenModule &CGM,
return Res;
}
+ if (const auto *BIT = destType->getAs()) {
+if (BIT->getNumBits() > 128) {
+ // Long _BitInt has array of bytes as in-memory type.
+ ConstantAggregat
https://github.com/momchil-velikov edited
https://github.com/llvm/llvm-project/pull/91364
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
@@ -118,6 +124,37 @@ llvm::Type *CodeGenTypes::ConvertTypeForMem(QualType T,
bool ForBitField) {
return R;
}
+bool CodeGenTypes::LLVMTypeLayoutMatchesAST(QualType ASTTy,
+llvm::Type *LLVMTy) {
+ CharUnits ASTSize = Context.getTyp
@@ -1886,6 +1896,29 @@ llvm::Constant
*ConstantEmitter::emitForMemory(CodeGenModule &CGM,
return Res;
}
+ if (destType->isBitIntType()) {
+if (CGM.getTypes().typeRequiresSplitIntoByteArray(destType, C->getType()))
{
+ // Long _BitInt has array of bytes as in-
momchil-velikov wrote:
This solves 5-6 issues we had downstream, many thanks!
https://github.com/llvm/llvm-project/pull/91364
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
@@ -3278,10 +3278,50 @@ class sme2_movt_zt_to_zt opc>
let Inst{4-0} = Zt;
}
-multiclass sme2_movt_zt_to_zt opc> {
+multiclass sme2_movt_zt_to_zt opc, SDPatternOperator
intrinsic_lane, SDPatternOperator intrinsic> {
def NAME : sme2_movt_zt_to_zt;
+ def NAME # _PSEUDO
+
momchil-velikov wrote:
Typo in commit message: `bflaot16`
> Variations other than bfloat16 had been already supported.
-> Variations other than bfloat16 are already supported.
https://github.com/llvm/llvm-project/pull/90105
___
cfe-commits mailing li
@@ -2930,17 +2939,59 @@ MachineBasicBlock
*AArch64TargetLowering::EmitInstrWithCustomInserter(
TII->get(MI.getOpcode()).TSFlags & AArch64::SMEMatrixTypeMask;
switch (SMEMatrixType) {
case (AArch64::SMEMatrixArray):
- return EmitZAInstr(SMEOrigInstr, AArch6
@@ -2883,19 +2883,28 @@ MachineBasicBlock
*AArch64TargetLowering::EmitZTInstr(MachineInstr &MI,
MachineBasicBlock *
AArch64TargetLowering::EmitZAInstr(unsigned Opc, unsigned BaseReg,
- MachineInstr &MI,
- Mac
@@ -2883,19 +2883,28 @@ MachineBasicBlock
*AArch64TargetLowering::EmitZTInstr(MachineInstr &MI,
MachineBasicBlock *
AArch64TargetLowering::EmitZAInstr(unsigned Opc, unsigned BaseReg,
- MachineInstr &MI,
- Mac
https://github.com/momchil-velikov edited
https://github.com/llvm/llvm-project/pull/88710
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
https://github.com/momchil-velikov edited
https://github.com/llvm/llvm-project/pull/88710
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
https://github.com/momchil-velikov closed
https://github.com/llvm/llvm-project/pull/88266
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/91597
Reverts llvm/llvm-project#88266 due to test failures
error: 'expected-error' diagnostics seen but not expected:
(frontend): '-fsyntax-only' action ignored; '-emit-llvm' action specified
previously
>
https://github.com/momchil-velikov closed
https://github.com/llvm/llvm-project/pull/91597
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
momchil-velikov wrote:
> Thanks for the quick revert!
>
> Is the failure due to a conflict with another commit that landed?
Perhaps, e.g. https://github.com/llvm/llvm-project/pull/91140
https://github.com/llvm/llvm-project/pull/88266
___
cfe-commits
https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/91606
[Recommit of e88ba6d975d887ca001cae30bfa0c53d91165148]
According to the specification in
https://github.com/ARM-software/acle/pull/309 this adds the intrinsics
void_svadd_za16_vg1x2_f16(uint32_t slice, s
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/88105
>From 8a63b17711d36cfeb4aab591853163119f5f167d Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 9 Apr 2024 10:52:41 +0100
Subject: [PATCH 1/4] [AArch64] Add intrinsics for non-widening FMOPA/FMOP
https://github.com/momchil-velikov commented:
LGTM, cheers!
https://github.com/llvm/llvm-project/pull/90105
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
https://github.com/momchil-velikov closed
https://github.com/llvm/llvm-project/pull/88553
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
https://github.com/momchil-velikov closed
https://github.com/llvm/llvm-project/pull/88105
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/91606
>From d3e381ac645d08b6f3b01283d47344556a163605 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Thu, 9 May 2024 15:56:31 +0100
Subject: [PATCH] [AArch64] Add intrinsics for multi-vector to ZA array ve
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/91606
>From 43fb20b7492307740c437e85c3f73af068d093cf Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Thu, 9 May 2024 15:56:31 +0100
Subject: [PATCH] [AArch64] Add intrinsics for multi-vector to ZA array ve
https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/91965
The patch at https://reviews.llvm.org/D122732 introduced using the array
subscript operator for SVE vectors, however it also causes an ICE when the
subscripting expression is used as an lvalue.
This pat
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/91965
>From 2e081d74e87ad14fdf6d950d3e3da6bed07ee723 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 13 May 2024 14:27:51 +0100
Subject: [PATCH] [Clang][AArch64][SVE] Allow write to SVE vector element
@@ -4180,8 +4180,10 @@ LValue CodeGenFunction::EmitArraySubscriptExpr(const
ArraySubscriptExpr *E,
// If the base is a vector type, then we are forming a vector element lvalue
// with this subscript.
- if (E->getBase()->getType()->isVectorType() &&
- !isa(E->getBase
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/91965
>From fd4a31c1eb48db410f5445f45243dfbc1d9d22ab Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 13 May 2024 14:27:51 +0100
Subject: [PATCH 1/2] [Clang][AArch64][SVE] Allow write to SVE vector ele
@@ -88,3 +88,13 @@ float subscript_float32(svfloat32_t a, size_t b) {
double subscript_float64(svfloat64_t a, size_t b) {
return a[b];
}
+
+// CHECK-LABEL: @subscript_write_float32(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[VECINS:%.*]] = insertelement
[[A:%.*]], float 1
https://github.com/momchil-velikov closed
https://github.com/llvm/llvm-project/pull/91606
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
@@ -0,0 +1,29 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -verify
-emit-llvm %s
momchil-velikov wrote:
Thanks!
https://github.com/llvm/llvm-project/pull/91606
___
cfe-commits mailing lis
@@ -2883,19 +2883,28 @@ MachineBasicBlock
*AArch64TargetLowering::EmitZTInstr(MachineInstr &MI,
MachineBasicBlock *
AArch64TargetLowering::EmitZAInstr(unsigned Opc, unsigned BaseReg,
- MachineInstr &MI,
- Mac
momchil-velikov wrote:
```
if (HasTile) {
MIB.addReg(BaseReg + MI.getOperand(0).getImm(), RegState::Define);
MIB.addReg(BaseReg + MI.getOperand(0).getImm());
StartIdx = 1;
} else
MIB.addReg(BaseReg, RegState::Define).addReg(BaseReg);
}
```
Needs extra braces aro
@@ -2939,59 +2922,18 @@ MachineBasicBlock
*AArch64TargetLowering::EmitInstrWithCustomInserter(
TII->get(MI.getOpcode()).TSFlags & AArch64::SMEMatrixTypeMask;
switch (SMEMatrixType) {
case (AArch64::SMEMatrixArray):
- return EmitZAInstr(SMEOrigInstr, AArch6
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/91965
>From 435f3104e68ef278196417c293093131258c549d Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 20 May 2024 15:43:31 +0100
Subject: [PATCH 1/3] [Clang][Sema] Refactor handling of vector subscript
https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/92778
None
>From 435f3104e68ef278196417c293093131258c549d Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 20 May 2024 15:43:31 +0100
Subject: [PATCH] [Clang][Sema] Refactor handling of vector subscri
@@ -4180,8 +4180,10 @@ LValue CodeGenFunction::EmitArraySubscriptExpr(const
ArraySubscriptExpr *E,
// If the base is a vector type, then we are forming a vector element lvalue
// with this subscript.
- if (E->getBase()->getType()->isVectorType() &&
- !isa(E->getBase
https://github.com/momchil-velikov edited
https://github.com/llvm/llvm-project/pull/92778
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
https://github.com/momchil-velikov closed
https://github.com/llvm/llvm-project/pull/92778
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/91965
>From b1b69ffcaf4525a66dde1ae7f1a022c85204a579 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 20 May 2024 16:25:43 +0100
Subject: [PATCH 1/2] [Clang][AArch64][SVE] Allow write to SVE vector ele
momchil-velikov wrote:
Rebased.
https://github.com/llvm/llvm-project/pull/91965
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
https://github.com/momchil-velikov closed
https://github.com/llvm/llvm-project/pull/91965
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Author: Momchil Velikov
Date: 2021-05-10T16:28:46+01:00
New Revision: 5c7b43aa8298a389b906d72c792941a0ce57782e
URL:
https://github.com/llvm/llvm-project/commit/5c7b43aa8298a389b906d72c792941a0ce57782e
DIFF:
https://github.com/llvm/llvm-project/commit/5c7b43aa8298a389b906d72c792941a0ce57782e.dif
Author: Momchil Velikov
Date: 2021-04-15T22:58:14+01:00
New Revision: f9d932e6735afe73117e142a12443449f2197e69
URL:
https://github.com/llvm/llvm-project/commit/f9d932e6735afe73117e142a12443449f2197e69
DIFF:
https://github.com/llvm/llvm-project/commit/f9d932e6735afe73117e142a12443449f2197e69.dif
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/112747
>From c2f223d84c18498f3cbe1582b006b0d4c52999aa Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Thu, 17 Oct 2024 14:04:05 +0100
Subject: [PATCH 1/3] [Clang][AArch64] Fix Pure Scalables Types argument
@@ -533,11 +638,158 @@ bool
AArch64ABIInfo::isZeroLengthBitfieldPermittedInHomogeneousAggregate()
return true;
}
+// Check if a type is a Pure Scalable Type as defined by AAPCS64. Return the
+// number of data vectors and the number of predicate vectors in the types,
into
@@ -533,11 +638,158 @@ bool
AArch64ABIInfo::isZeroLengthBitfieldPermittedInHomogeneousAggregate()
return true;
}
+// Check if a type is a Pure Scalable Type as defined by AAPCS64. Return the
+// number of data vectors and the number of predicate vectors in the types,
into
@@ -97,6 +97,17 @@
SVE_TYPE(Name, Id, SingletonId)
#endif
+#ifndef AARCH64_VECTOR_TYPE
momchil-velikov wrote:
This naming seems odd to me. So, far we've got a sort of taxonomy, or "isA"
relationship
that looks like:
SVE_VECTOR_TYPE_BFLOAT -> SVE_VECTO
@@ -533,11 +638,158 @@ bool
AArch64ABIInfo::isZeroLengthBitfieldPermittedInHomogeneousAggregate()
return true;
}
+// Check if a type is a Pure Scalable Type as defined by AAPCS64. Return the
+// number of data vectors and the number of predicate vectors in the types,
into
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/112747
>From c2f223d84c18498f3cbe1582b006b0d4c52999aa Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Thu, 17 Oct 2024 14:04:05 +0100
Subject: [PATCH 1/4] [Clang][AArch64] Fix Pure Scalables Types argument
@@ -353,6 +427,17 @@ AArch64ABIInfo::classifyArgumentType(QualType Ty, bool
IsVariadic,
nullptr, true, Align);
}
+ // In AAPCS named arguments of a Pure Scalable Type are passed expanded in
+ // registers, or indirectly if there are not enough registers.
+ if (Ki
https://github.com/momchil-velikov approved this pull request.
LGTM, cheers!
https://github.com/llvm/llvm-project/pull/112575
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
@@ -353,6 +427,17 @@ AArch64ABIInfo::classifyArgumentType(QualType Ty, bool
IsVariadic,
nullptr, true, Align);
}
+ // In AAPCS named arguments of a Pure Scalable Type are passed expanded in
+ // registers, or indirectly if there are not enough registers.
+ if (Ki
@@ -0,0 +1,338 @@
+// RUN: %clang_cc1 -O3 -triple aarch64
-target-feature +sve -target-feature +sve2p1 -mvscale-min=1 -mvscale-max=1
-emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-AAPCS
+// RUN: %clang_cc1 -O3 -triple arm64-apple-
201 - 300 of 483 matches
Mail list logo
