Author: chill
Date: Wed Aug 15 05:22:08 2018
New Revision: 339766
URL: http://llvm.org/viewvc/llvm-project?rev=339766&view=rev
Log:
Use .cpp extension for certain tests instead of .cc
The tests `CodeGen/aapcs[64]-align.cc` are not run since files with a `.cc`
suffix aren't recognisze as tests. Th
Author: chill
Date: Mon May 21 07:28:43 2018
New Revision: 332843
URL: http://llvm.org/viewvc/llvm-project?rev=332843&view=rev
Log:
[Sema] Fix incorrect packed aligned structure layout
Handle attributes before checking the record layout (e.g. underalignment check
during `alignas` processing), as
Author: chill
Date: Mon Jul 30 10:48:23 2018
New Revision: 338279
URL: http://llvm.org/viewvc/llvm-project?rev=338279&view=rev
Log:
[ARM, AArch64]: Use unadjusted alignment when passing composites as arguments
The "Procedure Call Procedure Call Standard for the ARM® Architecture"
(https://static.
Author: chill
Date: Wed Feb 7 08:52:02 2018
New Revision: 324490
URL: http://llvm.org/viewvc/llvm-project?rev=324490&view=rev
Log:
[DebugInfo] Improvements to representation of enumeration types (PR36168)
This patch:
* fixes an incorrect sign-extension of unsigned values, when emitting
debug
Author: chill
Date: Wed Feb 7 11:57:04 2018
New Revision: 324508
URL: http://llvm.org/viewvc/llvm-project?rev=324508&view=rev
Log:
Revert [DebugInfo] Improvements to representation of enumeration types
(PR36168)"
Revert due to breaking buildbots (LLDB tests)
Removed:
cfe/trunk/test/CodeGen
Author: chill
Date: Mon Feb 12 08:12:52 2018
New Revision: 324900
URL: http://llvm.org/viewvc/llvm-project?rev=324900&view=rev
Log:
Re-commit r324490: [DebugInfo] Improvements to representation of enumeration
types (PR36168)
Differential revision: https://reviews.llvm.org/D42736
Added:
cfe
Author: chill
Date: Wed Jul 17 04:24:37 2019
New Revision: 366315
URL: http://llvm.org/viewvc/llvm-project?rev=366315&view=rev
Log:
[AArch64] Consistent types and naming for AArch64 target features (NFC)
Differential Revision: https://reviews.llvm.org/D64415
Committed as obvious.
Modified:
Author: chill
Date: Wed Jul 17 06:23:27 2019
New Revision: 366322
URL: http://llvm.org/viewvc/llvm-project?rev=366322&view=rev
Log:
[AArch64] Add support for Transactional Memory Extension (TME)
TME is a future architecture technology, documented in
https://developer.arm.com/architectures/cpu-ar
Thanks, I've reverted it for now.
From: Simon Pilgrim via Phabricator
Sent: 17 July 2019 18:23:29
To: Momchil Velikov; oliver.stann...@linaro.org; t.p.northo...@gmail.com;
jdoerf...@anl.gov
Cc: llvm-...@redking.me.uk; notst...@gmail.com; cfe-commits@lists.llvm.or
Author: chill
Date: Wed Jul 17 10:43:32 2019
New Revision: 366355
URL: http://llvm.org/viewvc/llvm-project?rev=366355&view=rev
Log:
Revert [AArch64] Add support for Transactional Memory Extension (TME)
This reverts r366322 (git commit 4b8da3a503e434ddbc08ecf66582475765f449bc)
Removed:
cfe/tr
Author: chill
Date: Wed Jul 31 05:52:17 2019
New Revision: 367428
URL: http://llvm.org/viewvc/llvm-project?rev=367428&view=rev
Log:
[AArch64] Add support for Transactional Memory Extension (TME)
Re-commit r366322 after some fixes
TME is a future architecture technology, documented in
https:/
Author: chill
Date: Tue Aug 13 07:20:06 2019
New Revision: 368696
URL: http://llvm.org/viewvc/llvm-project?rev=368696&view=rev
Log:
[AArch64] Make the memtag sanitizer require the memtag extension
... or otherwise we get an ICE.
Differential Revision: https://reviews.llvm.org/D65508
Modified:
Author: chill
Date: Tue Aug 13 07:20:23 2019
New Revision: 368697
URL: http://llvm.org/viewvc/llvm-project?rev=368697&view=rev
Log:
Enable memtag sanitizer in all AArch64 toolchains
That sanitizer does not have runtime library or other dependencies.
Differential Revision: https://reviews.llvm.or
Author: Momchil Velikov
Date: 2020-04-27T16:01:07+01:00
New Revision: 334ac81054018c3ae6058a0bf12e9c9363bd50ad
URL:
https://github.com/llvm/llvm-project/commit/334ac81054018c3ae6058a0bf12e9c9363bd50ad
DIFF:
https://github.com/llvm/llvm-project/commit/334ac81054018c3ae6058a0bf12e9c9363bd50ad.dif
Author: Momchil Velikov
Date: 2020-04-28T17:05:58+01:00
New Revision: 102b4105e3fd568ed2c758ed7e6fd266a819d6db
URL:
https://github.com/llvm/llvm-project/commit/102b4105e3fd568ed2c758ed7e6fd266a819d6db
DIFF:
https://github.com/llvm/llvm-project/commit/102b4105e3fd568ed2c758ed7e6fd266a819d6db.dif
@@ -9497,8 +9500,11 @@ Value *CodeGenFunction::EmitSVEScatterStore(const
SVETypeFlags &TypeFlags,
// mapped to . However, this might be incompatible with the
// actual type being stored. For example, when storing doubles (i64) the
// predicated should be instead. At the
@@ -1457,6 +1457,24 @@ class AdvSIMD_GatherLoad_VS_Intrinsic
],
[IntrReadMem]>;
+class AdvSIMD_GatherLoadQ_VS_Intrinsic
+: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
+[
+ llvm_nxv1i1_ty,
+ ll
@@ -9497,8 +9500,11 @@ Value *CodeGenFunction::EmitSVEScatterStore(const
SVETypeFlags &TypeFlags,
// mapped to . However, this might be incompatible with the
// actual type being stored. For example, when storing doubles (i64) the
// predicated should be instead. At the
@@ -1457,6 +1457,24 @@ class AdvSIMD_GatherLoad_VS_Intrinsic
],
[IntrReadMem]>;
+class AdvSIMD_GatherLoadQ_VS_Intrinsic
+: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
+[
+ llvm_nxv1i1_ty,
+ ll
@@ -9671,28 +9677,47 @@ Value *CodeGenFunction::EmitSVEMaskedLoad(const
CallExpr *E,
// The vector type that is returned may be different from the
// eventual type loaded from memory.
auto VectorTy = cast(ReturnTy);
- auto MemoryTy = llvm::ScalableVectorType::get(MemElt
momchil-velikov wrote:
I'm going to squash the commits which belong to this PR as I don't believe they
are useful in isolation anymore and they get in the way of refactoring/rebasing.
(Long story short, I did a patch to avoid having two back to back probing
loops, then factored out a stack pr
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/68993
>From bfd551c181b8325382247eab80544e69212121aa Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Sat, 11 Nov 2023 11:41:48 +
Subject: [PATCH 1/6] [AArch64] Refactor allocation of locals and stack
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/68993
>From c55da9c253829610418e5fb22e2b0ecc3f1585b7 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Sat, 11 Nov 2023 15:27:53 +
Subject: [PATCH 1/6] [CFIFixup] Precommit test ahead of multi-block prol
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/70565
>From 0fb3e4e96d9377e65d1c794fe0b648ff835748b9 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Sat, 28 Oct 2023 15:01:36 +0100
Subject: [PATCH 1/4] [Verifier] Check function attributes related to bra
momchil-velikov wrote:
Ping?
https://github.com/llvm/llvm-project/pull/70565
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momchil-velikov wrote:
Ping?
https://github.com/llvm/llvm-project/pull/68993
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momchil-velikov wrote:
In the last update:
- do not set the `FrameSetup` flag for dynamic allocations
- avoid back to back probing loops for allocation of SVE locals and non-SVE
locals - fold the allocations together and emit a single loop (or no loop)
https://github.com/llvm/llvm-project/pul
https://github.com/momchil-velikov closed
https://github.com/llvm/llvm-project/pull/71289
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@@ -0,0 +1,61 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1
-target-feature +b16b16 -target-feature +sve -S -disable-O0-optnone -
@@ -0,0 +1,61 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1
-target-feature +b16b16 -target-feature +sve -S -disable-O0-optnone -
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/68993
>From a0f51e927e03140dae160151229f72383df9aeb6 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Sat, 11 Nov 2023 11:41:48 +
Subject: [PATCH 1/3] [AArch64] Refactor allocation of locals and stack
momchil-velikov wrote:
Latest update adds this patch:
https://github.com/llvm/llvm-project/pull/66524/commits/ff16f798d747ec9c16ebeeccbf4ef7ddd77f4636
https://github.com/llvm/llvm-project/pull/66524
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momchil-velikov wrote:
I thought the suggestion was to add a few lines to
https://github.com/llvm/llvm-project/blob/main/clang/docs/ReleaseNotes.rst
https://github.com/llvm/llvm-project/pull/73326
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https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/75117
None
>From 4fe606a2cf764ae4281789727d241c91c3cb9c39 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 11 Dec 2023 23:25:07 +
Subject: [PATCH] [Clang][SVE2.1] Add floating-point variants of `s
https://github.com/momchil-velikov edited
https://github.com/llvm/llvm-project/pull/71930
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@@ -0,0 +1,217 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 2
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1\
+// RUN: -S -Werror -emit-llvm -disable-O0-
@@ -1992,3 +1992,36 @@ let TargetGuard = "sme2" in {
def SVADD_SINGLE_X2 : SInst<"svadd[_single_{d}_x2]", "22d", "cUcsUsiUilUl",
MergeNone, "aarch64_sve_add_single_x2", [IsStreaming], []>;
def SVADD_SINGLE_X4 : SInst<"svadd[_single_{d}_x4]", "44d", "cUcsUsiUilUl",
MergeNon
@@ -1992,3 +1992,36 @@ let TargetGuard = "sme2" in {
def SVADD_SINGLE_X2 : SInst<"svadd[_single_{d}_x2]", "22d", "cUcsUsiUilUl",
MergeNone, "aarch64_sve_add_single_x2", [IsStreaming], []>;
def SVADD_SINGLE_X4 : SInst<"svadd[_single_{d}_x4]", "44d", "cUcsUsiUilUl",
MergeNon
@@ -0,0 +1,217 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 2
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1\
+// RUN: -S -Werror -emit-llvm -disable-O0-
@@ -0,0 +1,216 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 2
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1\
+// RUN: -S -Werror -emit-llvm -disable-O0-
https://github.com/momchil-velikov commented:
In addition to the code comments:
In the (tentative) commit message the prototype `svuint8_t
svextq_lane[_u8](svuint8_t zdn,` is cut short.
The prototype of `svint8_t svtbxq[_s8](svint8_t zn, svuint8_t zm);` is missing
an parameter.
The attribution
@@ -0,0 +1,217 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 2
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1\
+// RUN: -S -Werror -emit-llvm -disable-O0-
@@ -116,3 +116,9 @@ void test_svdot_lane_2way(svint32_t s32, svuint32_t u32,
svint16_t s16, svuint16
svdot_lane_u32_u16_u16(u32, u16, u16, 4); // expected-error {{argument value
4 is outside the valid range [0, 3]}}
svdot_lane_f32_f16_f16(f32, f16, f16, 4); // expected-err
@@ -1992,3 +1992,36 @@ let TargetGuard = "sme2" in {
def SVADD_SINGLE_X2 : SInst<"svadd[_single_{d}_x2]", "22d", "cUcsUsiUilUl",
MergeNone, "aarch64_sve_add_single_x2", [IsStreaming], []>;
def SVADD_SINGLE_X4 : SInst<"svadd[_single_{d}_x4]", "44d", "cUcsUsiUilUl",
MergeNon
@@ -0,0 +1,2503 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1
-target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-ll
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/68993
>From b42de31d5584cddb90c22c94e9d971feaaf0b624 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Wed, 11 Oct 2023 17:22:51 +0100
Subject: [PATCH] [clang][AArch64] Pass down stack clash protection optio
@@ -0,0 +1,61 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1
-target-feature +b16b16 -target-feature +sve -S -disable-O0-optnone -
@@ -1992,3 +1992,36 @@ let TargetGuard = "sme2" in {
def SVADD_SINGLE_X2 : SInst<"svadd[_single_{d}_x2]", "22d", "cUcsUsiUilUl",
MergeNone, "aarch64_sve_add_single_x2", [IsStreaming], []>;
def SVADD_SINGLE_X4 : SInst<"svadd[_single_{d}_x4]", "44d", "cUcsUsiUilUl",
MergeNon
https://github.com/momchil-velikov approved this pull request.
LGTM, cheers!
https://github.com/llvm/llvm-project/pull/71930
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https://github.com/momchil-velikov approved this pull request.
LGTM, cheers!
Check the commit message, a double colon in `Co-authored-by::`.
https://github.com/llvm/llvm-project/pull/70362
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https://github.com/llvm/llvm-project/pull/70474
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@@ -420,6 +449,35 @@ let TargetGuard = "sve,bf16" in {
def SVSTNT1_VNUM_BF : MInst<"svstnt1_vnum[_{d}]", "vPpld", "b", [IsStore],
MemEltTyDefault, "aarch64_sve_stnt1">;
}
+let TargetGuard = "sve2p1" in {
+ // Contiguous truncating store from quadword (single vector).
+ de
https://github.com/momchil-velikov closed
https://github.com/llvm/llvm-project/pull/70474
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https://github.com/llvm/llvm-project/pull/70476
>From 9f90ac3383b37e9d2310836527d01a94b6fbadb9 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Fri, 27 Oct 2023 16:09:07 +0100
Subject: [PATCH 1/2] [AArch64] Add SVE2.1 intrinsics for indexed quadwor
https://github.com/momchil-velikov closed
https://github.com/llvm/llvm-project/pull/70476
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https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/71290
>From 22ecaa7d6f7854bd89da7390a7813bd9f1397f0b Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Sat, 4 Nov 2023 12:02:06 +
Subject: [PATCH 1/2] [AArch64] Add quadword gather load/scatter store
in
@@ -26262,3 +26262,37 @@ bool
AArch64TargetLowering::preferScalarizeSplat(SDNode *N) const {
}
return true;
}
+
+bool AArch64TargetLowering::hasInlineStackProbe(
+const MachineFunction &MF) const {
+ // If the function specifically requests inline stack probes, emit t
@@ -1827,12 +1908,36 @@ void AArch64FrameLowering::emitPrologue(MachineFunction
&MF,
// FIXME: in the case of dynamic re-alignment, NumBytes doesn't have
// the correct value here, as NumBytes also includes padding bytes,
// which shouldn't be counted here.
-
@@ -4052,3 +4193,192 @@ void AArch64FrameLowering::orderFrameObjects(
dbgs() << "\n";
});
}
+
+/// Emit a loop to decrement SP until it is equal to TargetReg, with probes at
+/// least every ProbeSize bytes. Returns an iterator of the first instruction
+/// after the loop
@@ -97,14 +97,45 @@ AArch64FunctionInfo::AArch64FunctionInfo(const Function &F,
if (const auto *BTE = mdconst::extract_or_null(
F.getParent()->getModuleFlag("branch-target-enforcement")))
BranchTargetEnforcement = BTE->getZExtValue();
-return;
+ } els
@@ -672,6 +673,74 @@ void AArch64FrameLowering::emitCalleeSavedSVERestores(
emitCalleeSavedRestores(MBB, MBBI, true);
}
+void AArch64FrameLowering::allocateSVEStackSpace(
+MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+StackOffset AllocSize, StackOffset I
@@ -9460,6 +9461,94 @@ bool AArch64InstrInfo::isReallyTriviallyReMaterializable(
return TargetInstrInfo::isReallyTriviallyReMaterializable(MI);
}
+MachineBasicBlock::iterator
+AArch64InstrInfo::insertStackProbingLoop(MachineBasicBlock::iterator MBBI,
+
@@ -672,6 +673,74 @@ void AArch64FrameLowering::emitCalleeSavedSVERestores(
emitCalleeSavedRestores(MBB, MBBI, true);
}
+void AArch64FrameLowering::allocateSVEStackSpace(
+MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+StackOffset AllocSize, StackOffset I
@@ -1827,12 +1908,36 @@ void AArch64FrameLowering::emitPrologue(MachineFunction
&MF,
// FIXME: in the case of dynamic re-alignment, NumBytes doesn't have
// the correct value here, as NumBytes also includes padding bytes,
// which shouldn't be counted here.
-
@@ -26262,3 +26262,37 @@ bool
AArch64TargetLowering::preferScalarizeSplat(SDNode *N) const {
}
return true;
}
+
+bool AArch64TargetLowering::hasInlineStackProbe(
+const MachineFunction &MF) const {
+ // If the function specifically requests inline stack probes, emit t
@@ -9460,6 +9461,94 @@ bool AArch64InstrInfo::isReallyTriviallyReMaterializable(
return TargetInstrInfo::isReallyTriviallyReMaterializable(MI);
}
+MachineBasicBlock::iterator
+AArch64InstrInfo::insertStackProbingLoop(MachineBasicBlock::iterator MBBI,
+
@@ -1076,6 +1076,16 @@ void CodeGenModule::Release() {
"sign-return-address-with-bkey", 1);
}
+ if (Arch == llvm::Triple::aarch64 || Arch == llvm::Triple::aarch64_be) {
+auto *InlineAsm = llvm::MDString::get(TheModule.getContext(),
"inli
@@ -1757,46 +1826,55 @@ void AArch64FrameLowering::emitPrologue(MachineFunction
&MF,
}
}
- StackOffset AllocateBefore = SVEStackSize, AllocateAfter = {};
+ StackOffset SVECalleeSavedSize = {}, SVELocalsSize = SVEStackSize;
MachineBasicBlock::iterator CalleeSavesBeg
momchil-velikov wrote:
I only now noticed I had a bunch of comments sitting for a few weeks in
"Pending" state :/
https://github.com/llvm/llvm-project/pull/66524
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https://github.com/momchil-velikov closed
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https://github.com/llvm/llvm-project/pull/68993
>From ed580b95157d7f423c5384fa2d51af00f1359a10 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 2 Oct 2023 14:46:27 +0100
Subject: [PATCH 1/3] [CFIFixup] Allow function prologues to span more tha
@@ -85,17 +90,32 @@ static bool isPrologueCFIInstruction(const MachineInstr
&MI) {
MI.getFlag(MachineInstr::FrameSetup);
}
-static bool containsPrologue(const MachineBasicBlock &MBB) {
- return llvm::any_of(MBB.instrs(), isPrologueCFIInstruction);
-}
-
static bool
momchil-velikov wrote:
> Co-author: Matthew Devereau
Should be "Co-authored-by:"
https://github.com/llvm/llvm-project/pull/70362
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momchil-velikov wrote:
Rebased a couple of times to resolve merge conflicts.
https://github.com/llvm/llvm-project/pull/69598
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https://github.com/momchil-velikov closed
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https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/71289
When emitting LLVM IR for gather loads/scatter stores, the predicate parameter
is cast to a type that depends on the loaded, resp. stored type. That's correct
for operation where we have a predicate per
@@ -9671,28 +9677,47 @@ Value *CodeGenFunction::EmitSVEMaskedLoad(const
CallExpr *E,
// The vector type that is returned may be different from the
// eventual type loaded from memory.
auto VectorTy = cast(ReturnTy);
- auto MemoryTy = llvm::ScalableVectorType::get(MemElt
@@ -2614,6 +2619,37 @@ def int_aarch64_sve_ld1_pn_x4 :
SVE2p1_Load_PN_X4_Intrinsic;
def int_aarch64_sve_ldnt1_pn_x2 : SVE2p1_Load_PN_X2_Intrinsic;
def int_aarch64_sve_ldnt1_pn_x4 : SVE2p1_Load_PN_X4_Intrinsic;
+//
+// SVE2.1 - Contiguous loads to quadword (single vector)
+//
@@ -9702,17 +9727,34 @@ Value *CodeGenFunction::EmitSVEMaskedStore(const
CallExpr *E,
auto VectorTy = cast(Ops.back()->getType());
auto MemoryTy = llvm::ScalableVectorType::get(MemEltTy, VectorTy);
- Value *Predicate = EmitSVEPredicateCast(Ops[0], MemoryTy);
+ auto Pred
@@ -2614,6 +2619,37 @@ def int_aarch64_sve_ld1_pn_x4 :
SVE2p1_Load_PN_X4_Intrinsic;
def int_aarch64_sve_ldnt1_pn_x2 : SVE2p1_Load_PN_X2_Intrinsic;
def int_aarch64_sve_ldnt1_pn_x4 : SVE2p1_Load_PN_X4_Intrinsic;
+//
+// SVE2.1 - Contiguous loads to quadword (single vector)
+//
@@ -9671,28 +9677,47 @@ Value *CodeGenFunction::EmitSVEMaskedLoad(const
CallExpr *E,
// The vector type that is returned may be different from the
// eventual type loaded from memory.
auto VectorTy = cast(ReturnTy);
- auto MemoryTy = llvm::ScalableVectorType::get(MemElt
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/70565
>From eb47903ad47f4a9e833948424a1c88bc2c72090e Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Sat, 28 Oct 2023 15:01:36 +0100
Subject: [PATCH 1/4] [Verifier] Check function attributes related to bra
momchil-velikov wrote:
Ping?
https://github.com/llvm/llvm-project/pull/68993
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momchil-velikov wrote:
Ping?
https://github.com/llvm/llvm-project/pull/66525
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https://github.com/momchil-velikov edited
https://github.com/llvm/llvm-project/pull/70476
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@@ -1341,6 +1341,26 @@ def SVWHILEHS_U32 : SInst<"svwhilege_{d}[_{1}]", "Pmm",
"PUcPUsPUiPUl", MergeNon
def SVWHILEHS_U64 : SInst<"svwhilege_{d}[_{1}]", "Pnn", "PUcPUsPUiPUl",
MergeNone, "aarch64_sve_whilehs", [IsOverloadWhile]>;
}
+let TargetGuard = "sve2p1|sme2" in {
https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/75200
The `_s64`/`_u64` part can be omitted now. It's inferred from the argument
types.
>From 1cab2e8cfb0427e5d97e0f306460d1d83123d78b Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 12 Dec 2023 15
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/75200
>From bb881371fb036819a1d6489a9779e2c5ac7e7d3c Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 12 Dec 2023 15:08:33 +
Subject: [PATCH] [Clang][SVE2.1] Make the part of the name optional for
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/75200
>From bb881371fb036819a1d6489a9779e2c5ac7e7d3c Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 12 Dec 2023 15:08:33 +
Subject: [PATCH 1/2] [Clang][SVE2.1] Make the part of the name optional
@@ -1950,19 +1950,17 @@ let TargetGuard = "sve2p1|sme2" in {
//FIXME: Replace IsStreamingCompatible with IsStreamingOrHasSVE2p1 when
available
def SVPEXT_SINGLE : SInst<"svpext_lane_{d}", "P}i", "QcQsQiQl", MergeNone,
"aarch64_sve_pext", [IsStreamingCompatible], [ImmCheck<1, I
@@ -1950,19 +1950,17 @@ let TargetGuard = "sve2p1|sme2" in {
//FIXME: Replace IsStreamingCompatible with IsStreamingOrHasSVE2p1 when
available
def SVPEXT_SINGLE : SInst<"svpext_lane_{d}", "P}i", "QcQsQiQl", MergeNone,
"aarch64_sve_pext", [IsStreamingCompatible], [ImmCheck<1, I
@@ -1950,19 +1950,17 @@ let TargetGuard = "sve2p1|sme2" in {
//FIXME: Replace IsStreamingCompatible with IsStreamingOrHasSVE2p1 when
available
def SVPEXT_SINGLE : SInst<"svpext_lane_{d}", "P}i", "QcQsQiQl", MergeNone,
"aarch64_sve_pext", [IsStreamingCompatible], [ImmCheck<1, I
https://github.com/momchil-velikov edited
https://github.com/llvm/llvm-project/pull/75200
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https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/75200
>From bb881371fb036819a1d6489a9779e2c5ac7e7d3c Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 12 Dec 2023 15:08:33 +
Subject: [PATCH 1/3] [Clang][SVE2.1] Make the part of the name optional
@@ -1950,19 +1950,17 @@ let TargetGuard = "sve2p1|sme2" in {
//FIXME: Replace IsStreamingCompatible with IsStreamingOrHasSVE2p1 when
available
def SVPEXT_SINGLE : SInst<"svpext_lane_{d}", "P}i", "QcQsQiQl", MergeNone,
"aarch64_sve_pext", [IsStreamingCompatible], [ImmCheck<1, I
@@ -1341,6 +1341,26 @@ def SVWHILEHS_U32 : SInst<"svwhilege_{d}[_{1}]", "Pmm",
"PUcPUsPUiPUl", MergeNon
def SVWHILEHS_U64 : SInst<"svwhilege_{d}[_{1}]", "Pnn", "PUcPUsPUiPUl",
MergeNone, "aarch64_sve_whilehs", [IsOverloadWhile]>;
}
+let TargetGuard = "sve2p1|sme2" in {
+ d
@@ -1,12 +1,20 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S
-O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -t
@@ -1,12 +1,20 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S
-O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -t
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