r290642 - Update test that relies on the optimizer to match new output.

Author: mkuper Date: Tue Dec 27 18:30:43 2016 New Revision: 290642 URL: http://llvm.org/viewvc/llvm-project?rev=290642&view=rev Log: Update test that relies on the optimizer to match new output. Modified: cfe/trunk/test/CodeGen/avx-shuffle-builtins.c Modified: cfe/trunk/test/CodeGen/avx-shuf

r289455 - Bring back note about not supporting global register variables.

Author: mkuper Date: Mon Dec 12 13:11:39 2016 New Revision: 289455 URL: http://llvm.org/viewvc/llvm-project?rev=289455&view=rev Log: Bring back note about not supporting global register variables. This was accidentally removed in r260506, even though we only support non-allocatable global registe

[PATCH] D13009: [X86] Fix some non-reserved parameter names in intrinsic headers

mkuper created this revision. mkuper added a reviewer: AsafBadouh. mkuper added a subscriber: cfe-commits. http://reviews.llvm.org/D13009 Files: lib/Headers/avx512fintrin.h lib/Headers/emmintrin.h Index: lib/Headers/avx512fintrin.h

r248150 - [X86] Fix some non-reserved parameter names in intrinsic headers

Author: mkuper Date: Mon Sep 21 06:45:27 2015 New Revision: 248150 URL: http://llvm.org/viewvc/llvm-project?rev=248150&view=rev Log: [X86] Fix some non-reserved parameter names in intrinsic headers Differential Revision: http://reviews.llvm.org/D13009 Modified: cfe/trunk/lib/Headers/avx512fi

Re: [PATCH] D13009: [X86] Fix some non-reserved parameter names in intrinsic headers

This revision was automatically updated to reflect the committed changes. Closed by commit rL248150: [X86] Fix some non-reserved parameter names in intrinsic headers (authored by mkuper). Changed prior to commit: http://reviews.llvm.org/D13009?vs=35225&id=35230#toc Repository: rL LLVM http:

[PATCH] D13015: [X86] Make f16c intrinsics accessible through emmintrin.h, per Intel docs

mkuper created this revision. mkuper added a reviewer: AsafBadouh. mkuper added a subscriber: cfe-commits. http://reviews.llvm.org/D13015 Files: lib/Headers/emmintrin.h lib/Headers/f16cintrin.h Index: lib/Headers/emmintrin.h ===

Re: [PATCH] D13015: [X86] Make f16c intrinsics accessible through emmintrin.h, per Intel docs

This revision was automatically updated to reflect the committed changes. Closed by commit rL248156: [X86] Make f16c intrinsics accessible through emmintrin.h, per Intel docs (authored by mkuper). Changed prior to commit: http://reviews.llvm.org/D13015?vs=35237&id=35250#toc Repository: rL LL

r248156 - [X86] Make f16c intrinsics accessible through emmintrin.h, per Intel docs

Author: mkuper Date: Mon Sep 21 08:34:47 2015 New Revision: 248156 URL: http://llvm.org/viewvc/llvm-project?rev=248156&view=rev Log: [X86] Make f16c intrinsics accessible through emmintrin.h, per Intel docs Differential Revision: http://reviews.llvm.org/D13015 Modified: cfe/trunk/lib/Headers

Re: [PATCH] D12052: [X86][SSE] Add _mm_undefined_* intrinsics

mkuper added a comment. Thanks, Simon! I've wanted to add the _undefined intrinsics for a while now, but never got to it. Anyway, this sort of implementation somewhat worries me. Yes, I know that the gcc intrinsics do something very similar. And I also know that in practice we'll get an undef

Re: [PATCH] D12052: [X86][SSE] Add _mm_undefined_* intrinsics

mkuper added a comment. I think this is slightly less elegant than having a generic builtin, but I'm just fine with it, especially if David/Eric prefer it to the generic version. Repository: rL LLVM http://reviews.llvm.org/D12052 ___ cfe-commits

Re: [PATCH] D12052: [X86][SSE] Add _mm_undefined_* intrinsics

mkuper added a comment. Actually, thinking about it a bit more, a generic builtin most probably won't be more elegant. LGTM. Repository: rL LLVM http://reviews.llvm.org/D12052 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.

[PATCH] D12271: [X86] Expose the various _rot intrinsics on non-MS platforms

mkuper created this revision. mkuper added reviewers: majnemer, rnk. mkuper added a subscriber: cfe-commits. _rotl, _rotwl and _lrotl (and their right-shift counterparts) are official x86 intrinsics, and should be supported regardless of environment. This is in contrast to _rotl8, _rotl16, and _r

[PATCH] D12278: [X86] Add MSVC-compatible intrinsics for clac, stac, lgdt and sgdt

mkuper created this revision. mkuper added reviewers: rnk, majnemer. mkuper added a subscriber: cfe-commits. LLVM part was posted as D12277 http://reviews.llvm.org/D12278 Files: include/clang/Basic/BuiltinsX86.def lib/Headers/Intrin.h test/CodeGen/builtins-x86.c Index: lib/Headers/Intrin.

Re: [PATCH] D12278: [X86] Add MSVC-compatible intrinsics for clac, stac, lgdt and sgdt

mkuper added inline comments. Comment at: lib/Headers/Intrin.h:961 @@ +960,3 @@ +static __inline__ void __DEFAULT_FN_ATTRS _lgdt(void *__ptr) { + __builtin_ia32_lgdt(__ptr); +} compnerd wrote: > Why does this need a builtin? Is an inline assembly block using lgd

r245923 - [X86] Expose the various _rot intrinsics on non-MS platforms

Author: mkuper Date: Tue Aug 25 02:21:33 2015 New Revision: 245923 URL: http://llvm.org/viewvc/llvm-project?rev=245923&view=rev Log: [X86] Expose the various _rot intrinsics on non-MS platforms _rotl, _rotwl and _lrotl (and their right-shift counterparts) are official x86 intrinsics, and should b

Re: [PATCH] D12271: [X86] Expose the various _rot intrinsics on non-MS platforms

This revision was automatically updated to reflect the committed changes. Closed by commit rL245923: [X86] Expose the various _rot intrinsics on non-MS platforms (authored by mkuper). Changed prior to commit: http://reviews.llvm.org/D12271?vs=32925&id=33050#toc Repository: rL LLVM http://re

r245929 - Revert r245923 since it breaks mingw.

Author: mkuper Date: Tue Aug 25 06:42:31 2015 New Revision: 245929 URL: http://llvm.org/viewvc/llvm-project?rev=245929&view=rev Log: Revert r245923 since it breaks mingw. Removed: cfe/trunk/test/CodeGen/x86-rot-intrinsics.c Modified: cfe/trunk/lib/Headers/Intrin.h cfe/trunk/lib/Header

[PATCH] D13554: [X86] Enable soft float ABI for x86

mkuper created this revision. mkuper added reviewers: rafael, rnk. mkuper added a subscriber: cfe-commits. The Intel MCU psABI is a new soft-float ABI, based on the IA32 psABI. The document describing the ABI can be found here: https://github.com/hjl-tools/x86-psABI/wiki/iamcu-psABI-0.7.pdf Pe

Re: [PATCH] D13554: [X86] Enable soft float ABI for x86

mkuper added a comment. It's ok, thanks a lot for taking the time to review it! http://reviews.llvm.org/D13554 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

r250687 - Use saner variable names. NFC.

Author: mkuper Date: Mon Oct 19 02:52:25 2015 New Revision: 250687 URL: http://llvm.org/viewvc/llvm-project?rev=250687&view=rev Log: Use saner variable names. NFC. Modified: cfe/trunk/lib/CodeGen/TargetInfo.cpp Modified: cfe/trunk/lib/CodeGen/TargetInfo.cpp URL: http://llvm.org/viewvc/llvm-

r250689 - [X86] Enable soft float ABI for x86

Author: mkuper Date: Mon Oct 19 03:09:43 2015 New Revision: 250689 URL: http://llvm.org/viewvc/llvm-project?rev=250689&view=rev Log: [X86] Enable soft float ABI for x86 The Intel MCU psABI requires floating-point values to be passed in-reg. This makes the x86-32 ABI code respect "-mfloat-abi soft

Re: [PATCH] D13554: [X86] Enable soft float ABI for x86

This revision was automatically updated to reflect the committed changes. Closed by commit rL250689: [X86] Enable soft float ABI for x86 (authored by mkuper). Changed prior to commit: http://reviews.llvm.org/D13554?vs=36853&id=37723#toc Repository: rL LLVM http://reviews.llvm.org/D13554 Fi

[PATCH] D13978: [X86] Support MCU psABI when marking inregs

mkuper created this revision. mkuper added reviewers: rnk, rafael. mkuper added a subscriber: cfe-commits. mkuper added a dependency: D13977: [X86] Add elfiamcu triple support, and a workaround for PR3997. Herald added a subscriber: aemerson. The MCU psABI has a calling convention that is somewh

Re: [PATCH] D13978: [X86] Support MCU psABI when marking inregs

mkuper added inline comments. Comment at: lib/CodeGen/TargetInfo.cpp:857 @@ -854,3 +856,3 @@ IsWin32StructABI(Win32StructABI), - IsSoftFloatABI(SoftFloatABI), + IsSoftFloatABI(SoftFloatABI), IsMCUABI(MCUABI), DefaultNumRegisterParameters(NumRegisterParamete

Re: [PATCH] D13978: [X86] Support MCU psABI when marking inregs

This revision was automatically updated to reflect the committed changes. Closed by commit rL251224: [X86] Mark inregs correctly for MCU psABI (authored by mkuper). Changed prior to commit: http://reviews.llvm.org/D13978?vs=38107&id=38341#toc Repository: rL LLVM http://reviews.llvm.org/D139

r251224 - [X86] Mark inregs correctly for MCU psABI

Author: mkuper Date: Sun Oct 25 03:18:20 2015 New Revision: 251224 URL: http://llvm.org/viewvc/llvm-project?rev=251224&view=rev Log: [X86] Mark inregs correctly for MCU psABI The MCU psABI calling convention is somewhat, but not quite, like -mregparm 3. In particular, the rules involving structs

r251396 - Access the right triple field for IAMCU.

Author: mkuper Date: Tue Oct 27 02:46:22 2015 New Revision: 251396 URL: http://llvm.org/viewvc/llvm-project?rev=251396&view=rev Log: Access the right triple field for IAMCU. Modified: cfe/trunk/lib/CodeGen/TargetInfo.cpp Modified: cfe/trunk/lib/CodeGen/TargetInfo.cpp URL: http://llvm.org/vi

Re: [PATCH] D14205: [x86] Front-end part of MCU psABI support

mkuper accepted this revision. mkuper added a comment. This revision is now accepted and ready to land. LGTM Comment at: lib/Basic/Targets.cpp:2327 @@ -2325,3 +2326,3 @@ // X87 evaluates with 80 bits "long double" precision. return SSELevel == NoSSE ? 2 : 0; } -

Re: [PATCH] D11753: [X86] Add support for _MM_ALIGN16

This revision was automatically updated to reflect the committed changes. Closed by commit rL244201: [X86] Add support for _MM_ALIGN16 (authored by mkuper). Changed prior to commit: http://reviews.llvm.org/D11753?vs=31317&id=31430#toc Repository: rL LLVM http://reviews.llvm.org/D11753 File

r244201 - [X86] Add support for _MM_ALIGN16

Author: mkuper Date: Thu Aug 6 03:24:38 2015 New Revision: 244201 URL: http://llvm.org/viewvc/llvm-project?rev=244201&view=rev Log: [X86] Add support for _MM_ALIGN16 Differential Revision: http://reviews.llvm.org/D11753 Added: cfe/trunk/test/CodeGen/ms-mm-align.c Modified: cfe/trunk/lib

Re: [PATCH] D11476: Marked call instruction in thunk function with tail attribute when applicable

This revision was automatically updated to reflect the committed changes. Closed by commit rL244207: Mark calls in thunk functions as tail-call optimization candidates (authored by mkuper). Changed prior to commit: http://reviews.llvm.org/D11476?vs=31341&id=31440#toc Repository: rL LLVM htt

Re: [PATCH] D22900: Revert r244207 - Mark calls in thunk functions as tail-call optimization

mkuper resigned from this revision. mkuper removed a reviewer: mkuper. mkuper added a comment. I really don't understand anything about this. :-) https://reviews.llvm.org/D22900 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.ll

Re: [PATCH] D22900: Revert r244207 - Mark calls in thunk functions as tail-call optimization

I care highly about my commits. It's just that it's not actually my commit, I committed it on Amjad's behalf before he had commit permissions. :-) I think Eli missed the "Patch by" line when he originally added me to the thread. On Fri, Jul 29, 2016 at 11:16 AM, Gerolf Hoflehner wrote: > Sounds

Re: [PATCH] D17092: [X86] Add -mseparate-stack-seg

mkuper resigned from this revision. mkuper removed a reviewer: mkuper. mkuper added a comment. I really don't know enough about this part of clang either. http://reviews.llvm.org/D17092 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://

Re: [PATCH] D20468: [X86][AVX] Ensure zero-extension of _mm256_extract_epi8 and _mm256_extract_epi16

mkuper added a comment. Could you point me to where in the documentation it says they must be zero-extended? The Intel intrinsics guide actually has them with shorter return types: __int8 _mm256_extract_epi8 (__m256i a, const int index) __int16 _mm256_extract_epi16 (__m256i a, const int inde

Re: [PATCH] D20468: [X86][AVX] Ensure zero-extension of _mm256_extract_epi8 and _mm256_extract_epi16

mkuper added a comment. You're right, the underlying instructions zext, and it seems like it's the right thing to do. I'm just wondering if this is something user code is supposed to rely on, given the way the intrinsics guide documents them right now. H.J, could you please take a look? Repos

Re: [PATCH] D20468: [X86][AVX] Ensure zero-extension of _mm256_extract_epi8 and _mm256_extract_epi16

mkuper accepted this revision. mkuper added a comment. This revision is now accepted and ready to land. Thanks, Dave! In that case, LGTM. Repository: rL LLVM http://reviews.llvm.org/D20468 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

Re: [PATCH] D19458: Add address space 258 to Clang documentation

mkuper accepted this revision. mkuper added a comment. This revision is now accepted and ready to land. LGTM with a small nit - can you change the heading from "Memory references off the GS segment" to something more general? http://reviews.llvm.org/D19458 ___

Re: [PATCH] D19458: Add address space 258 to Clang documentation

mkuper added a comment. LGTM http://reviews.llvm.org/D19458 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

Re: [PATCH] D20528: [X86][SSE] Replace lossless i32/f32 to f64 conversion intrinsics with generic IR

mkuper added a comment. Thanks, Simon! This looks right, but we may lose some end-to-end tests, since right now we have a clang-level test that checks the builtin is lowered to the intrinsic, and (hopefully) a CG-level test that the intrinsic is lowered to the correct instruction. Do you know i

Re: [PATCH] D20528: [X86][SSE] Replace lossless i32/f32 to f64 conversion intrinsics with generic IR

mkuper added a comment. In http://reviews.llvm.org/D20528#437090, @RKSimon wrote: > In http://reviews.llvm.org/D20528#436893, @mkuper wrote: > > > This looks right, but we may lose some end-to-end tests, since right now we > > have a clang-level test that checks the builtin is lowered to the >

Re: [PATCH] D20528: [X86][SSE] Replace lossless i32/f32 to f64 conversion intrinsics with generic IR

mkuper added a comment. Presumably, the fast-isel lowering of the IR pattern is already correct, and in any case, it isn't affected by this patch. I just want to make sure we don't regress the optimized DAG codegen - that is, it still produces the instruction we'd expect from the intrinsic (or s

Re: [PATCH] D20528: [X86][SSE] Replace lossless i32/f32 to f64 conversion intrinsics with generic IR

mkuper accepted this revision. mkuper added a comment. This revision is now accepted and ready to land. > The existing llvm\test\CodeGen\X86\vec_fpext.ll and > llvm\test\CodeGen\X86\vec_int_to_fp.ll already demonstrate the correct > optimized DAG codegen using the same IR as output in the > cla

Re: [PATCH] D21173: [X86] _MM_ALIGN16 attribute support for non-windows targets

mkuper accepted this revision. mkuper added a comment. This revision is now accepted and ready to land. LGTM Repository: rL LLVM http://reviews.llvm.org/D21173 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/

r274805 - [CUDA] Pass correct option in test.

Author: mkuper Date: Thu Jul 7 18:22:39 2016 New Revision: 274805 URL: http://llvm.org/viewvc/llvm-project?rev=274805&view=rev Log: [CUDA] Pass correct option in test. Modified: cfe/trunk/test/Driver/cuda-version-check.cu Modified: cfe/trunk/test/Driver/cuda-version-check.cu URL: http://ll

r256495 - [X86] Better support for the MCU psABI (clang part)

Author: mkuper Date: Mon Dec 28 08:39:54 2015 New Revision: 256495 URL: http://llvm.org/viewvc/llvm-project?rev=256495&view=rev Log: [X86] Better support for the MCU psABI (clang part) This adds support for the MCU psABI in a way different from r251223 and r251224, basically reverting most of the

Re: [PATCH] D15055: [X86] Better support for the MCU psABI

This revision was automatically updated to reflect the committed changes. Closed by commit rL256495: [X86] Better support for the MCU psABI (clang part) (authored by mkuper). Changed prior to commit: http://reviews.llvm.org/D15055?vs=41348&id=43685#toc Repository: rL LLVM http://reviews.llv

Re: [PATCH] D14954: [x86] Exclusion of incorrect include headers paths for MCU target

mkuper accepted this revision. mkuper added a comment. This revision is now accepted and ready to land. LGTM http://reviews.llvm.org/D14954 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-co

[PATCH] D15055: [X86] Better support for the MCU psABI

mkuper created this revision. mkuper added reviewers: rnk, rafael, DavidKreitzer. mkuper added a subscriber: cfe-commits. This adds support for the MCU psABI in a way different from r251223 and r251224, basically reverting most of these two patches. The problem with the approach taken in r251223

Re: [PATCH] D15127: Move _mm256_cvtps_ph and _mm256_cvtph_ps to immintrin.h.

mkuper accepted this revision. mkuper added a comment. This revision is now accepted and ready to land. Thanks Paul, LGTM. http://reviews.llvm.org/D15127 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/l

r256121 - [X86] Add signed aliases for popcnt intrinsics

Author: mkuper Date: Sun Dec 20 06:35:35 2015 New Revision: 256121 URL: http://llvm.org/viewvc/llvm-project?rev=256121&view=rev Log: [X86] Add signed aliases for popcnt intrinsics The Intel manual documents both an unsigned form (_mm_popcnt_u32) and a signed form (_popcnt32) of the intrinsic. Add

r256122 - [X86] Add missing m64/int64 conversions

Author: mkuper Date: Sun Dec 20 06:37:18 2015 New Revision: 256122 URL: http://llvm.org/viewvc/llvm-project?rev=256122&view=rev Log: [X86] Add missing m64/int64 conversions Define the 64-bit equivalents of _m_to_int and _m_from_int. Differential Revision: http://reviews.llvm.org/D15572 Modifie