@@ -91,6 +97,88 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T,
const Triple &TT,
setRequiresStructuredCFG(false);
}
+enum AddressSpace {
+ Function = storageClassToAddressSpace(SPIRV::StorageClass::Function),
+ CrossWorkgroup =
+ storageClassToAddressSpac
@@ -91,6 +97,88 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T,
const Triple &TT,
setRequiresStructuredCFG(false);
}
+enum AddressSpace {
+ Function = storageClassToAddressSpace(SPIRV::StorageClass::Function),
+ CrossWorkgroup =
+ storageClassToAddressSpac
@@ -91,6 +97,88 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T,
const Triple &TT,
setRequiresStructuredCFG(false);
}
+enum AddressSpace {
+ Function = storageClassToAddressSpace(SPIRV::StorageClass::Function),
+ CrossWorkgroup =
+ storageClassToAddressSpac
@@ -0,0 +1,29 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
arsenm wrote:
You don't need to duplicate all of these tests. You just need some basic
samples that the target is implemented, the full set is testing pass mechanics
whi
https://github.com/arsenm approved this pull request.
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@@ -463,10 +463,11 @@ void HIP::constructGenerateObjFileFromHIPFatBinary(
Objf << ObjBuffer;
- ArgStringList McArgs{"-triple", Args.MakeArgString(HostTriple.normalize()),
+ ArgStringList McArgs{"-target", Args.MakeArgString(HostTriple.normalize()),
@@ -372,6 +372,31 @@ void foo(double *d, float f, float *fp, long double *l,
int *i, const char *c) {
// HAS_MAYTRAP: declare float @llvm.experimental.constrained.minnum.f32(
// HAS_MAYTRAP: declare x86_fp80 @llvm.experimental.constrained.minnum.f80(
+ fmaximum_num(*d,*d);
@@ -15314,6 +15314,32 @@ bool FloatExprEvaluator::VisitCallExpr(const CallExpr
*E) {
Result = RHS;
arsenm wrote:
Unrelated, but why is up here reproducing logic that's already in APFloat?
https://github.com/llvm/llvm-project/pull/96281
_
@@ -15314,6 +15314,32 @@ bool FloatExprEvaluator::VisitCallExpr(const CallExpr
*E) {
Result = RHS;
return true;
}
+
+ case Builtin::BI__builtin_fmaximum_num:
+ case Builtin::BI__builtin_fmaximum_numf:
+ case Builtin::BI__builtin_fmaximum_numl:
+ case Builtin::B
@@ -475,6 +475,12 @@ SYMBOL(fmaxl, None, )
SYMBOL(fmin, None, )
SYMBOL(fminf, None, )
SYMBOL(fminl, None, )
+SYMBOL(fmaximum_num, None, )
arsenm wrote:
Not sure what this for, but this isn't tested?
https://github.com/llvm/llvm-project/pull/96281
@@ -372,6 +372,31 @@ void foo(double *d, float f, float *fp, long double *l,
int *i, const char *c) {
// HAS_MAYTRAP: declare float @llvm.experimental.constrained.minnum.f32(
// HAS_MAYTRAP: declare x86_fp80 @llvm.experimental.constrained.minnum.f80(
+ fmaximum_num(f,f);
@@ -1295,6 +1295,24 @@ SYMBOL(fminf, None, )
SYMBOL(fminl, std::, )
SYMBOL(fminl, None, )
SYMBOL(fminl, None, )
+SYMBOL(fmaximum_num, std::, )
arsenm wrote:
Not sure what this for, but this isn't tested?
https://github.com/llvm/llvm-project/pull/96281
__
arsenm wrote:
> > I fixed an apparent missing test dependency in
> > [1ac6ef5](https://github.com/llvm/llvm-project/commit/1ac6ef5af28b72e534496a9833a2b75a2aba66cc)
> > and this commit removed the llvm-mc dependency
>
> I probably should've remembered to include removing that in this patch.
I
@@ -91,6 +97,100 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T,
const Triple &TT,
setRequiresStructuredCFG(false);
}
+enum AddressSpace {
+ Function = storageClassToAddressSpace(SPIRV::StorageClass::Function),
+ CrossWorkgroup =
+ storageClassToAddressSpa
@@ -91,6 +97,100 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T,
const Triple &TT,
setRequiresStructuredCFG(false);
}
+enum AddressSpace {
+ Function = storageClassToAddressSpace(SPIRV::StorageClass::Function),
+ CrossWorkgroup =
+ storageClassToAddressSpa
arsenm wrote:
I fixed an apparent missing test dependency in
1ac6ef5af28b72e534496a9833a2b75a2aba66cc and this commit removed the llvm-mc
dependency
https://github.com/llvm/llvm-project/pull/112041
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>From 91c2f46274f83603552b12317c2fb87a8633ccc3 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 11 Oct 2024 14:33:32 +0400
Subject: [PATCH 1/7] clang: Remove requires system-linux from some driver
tests
@@ -108,11 +108,15 @@ RawAddress CodeGenFunction::CreateTempAlloca(llvm::Type
*Ty, CharUnits Align,
if (AllocaAddr)
*AllocaAddr = Alloca;
llvm::Value *V = Alloca.getPointer();
+ assert((!getLangOpts().OpenCL ||
+ CGM.getTarget().getTargetAddressSpace(getASTAl
https://github.com/arsenm commented:
I agree that in theory a target could want to do something else, but that would
be an ABI lowering decision. It doesn't naturally come from a source level
type. Supporting such a target would require more work, but given the current
state of the world just
@@ -5390,11 +5391,19 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo
&CallInfo,
V->getType()->isIntegerTy())
V = Builder.CreateZExt(V, ArgInfo.getCoerceToType());
-// If the argument doesn't match, perform a bitcast to coerce it. This
-
@@ -5390,11 +5391,19 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo
&CallInfo,
V->getType()->isIntegerTy())
V = Builder.CreateZExt(V, ArgInfo.getCoerceToType());
-// If the argument doesn't match, perform a bitcast to coerce it. This
-
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@@ -5390,11 +5391,19 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo
&CallInfo,
V->getType()->isIntegerTy())
V = Builder.CreateZExt(V, ArgInfo.getCoerceToType());
-// If the argument doesn't match, perform a bitcast to coerce it. This
-
@@ -23,8 +25,10 @@ X Test()
// sret argument.
// CHECK-CXX98: call void @_ZN1XC1ERKS_(
// CHECK-CXX11: call void @_ZN1XC1EOS_(
+ // CHECK-CXX11-NONZEROALLOCAAS: call void @_ZN1XC1EOS_(
arsenm wrote:
Can you add more context checks here?
https://github.
https://github.com/arsenm commented:
Should fix commit description
https://github.com/llvm/llvm-project/pull/114067
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@@ -108,11 +108,15 @@ RawAddress CodeGenFunction::CreateTempAlloca(llvm::Type
*Ty, CharUnits Align,
if (AllocaAddr)
*AllocaAddr = Alloca;
llvm::Value *V = Alloca.getPointer();
+ assert((!getLangOpts().OpenCL ||
+ CGM.getTarget().getTargetAddressSpace(getASTAl
https://github.com/arsenm approved this pull request.
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@@ -318,6 +318,7 @@ TEST_F(TargetLibraryInfoTest, ValidProto) {
"declare void @qsort(i8*, i64, i64, i32 (i8*, i8*)*)\n"
"declare i64 @readlink(i8*, i8*, i64)\n"
"declare i8* @realloc(i8*, i64)\n"
+ "declare i8* @reallocarray(i8*, i64, i64)\n"
@@ -0,0 +1,19 @@
+//===--- AtomicOptions.def - Atomic Options database -*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -569,19 +569,21 @@ void AMDGPUTargetCodeGenInfo::setTargetAtomicMetadata(
AtomicInst.setMetadata(llvm::LLVMContext::MD_noalias_addrspace, ASRange);
}
- if (!RMW || !CGF.getTarget().allowAMDGPUUnsafeFPAtomics())
+ if (!RMW)
return;
- // TODO: Introduce new, m
@@ -0,0 +1,30 @@
+// RUN: %clang_cc1 -fsyntax-only -verify %s
+// RUN: %clang_cc1 -fsyntax-only -verify -fcuda-is-device %s
+// RUN: %clang_cc1 -fsyntax-only -verify -fcuda-is-device %s \
+// RUN:
-fatomic=no_fine_grained_memory:off,no_remote_memory:on,ignore_denormal_mode:on
+
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arsenm wrote:
> I do think this change still makes sense, especially from a consistency point
> of view. If SROA sets one of the value-based FMF flags (nsz) then it stands
> to reason that it should also set the other two (nnan and ninf). Unless there
> is some reason why nsz would be more pro
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/113751
>From 6981d5ad80130130d373b8c879a88b7d727b0115 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Sat, 19 Oct 2024 02:39:06 +0400
Subject: [PATCH 1/4] clang/AMDGPU: Emit grid size builtins with range metadata
T
https://github.com/arsenm edited
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arsenm wrote:
> I'm not sure what's special about your usage of Graphite, but I've seen other
> people use it without triggering these notifications to everyone.
This was specifically a reorder. I've seen this in some reorder cases, but not
others
> I think you need to do it the other way ar
@@ -852,6 +852,7 @@ static void initializeLibCalls(TargetLibraryInfoImpl &TLI,
const Triple &T,
TLI.setUnavailable(LibFunc_memrchr);
TLI.setUnavailable(LibFunc_ntohl);
TLI.setUnavailable(LibFunc_ntohs);
+TLI.setUnavailable(LibFunc_reallocarray);
---
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@@ -1024,6 +1024,15 @@ GCNTTIImpl::instCombineIntrinsic(InstCombiner &IC,
IntrinsicInst &II) const {
}
break;
}
+ case Intrinsic::amdgcn_wavefrontsize: {
+// TODO: this is a workaround for the pseudo-generic target one gets with
no
+// specified mcpu, which
@@ -1024,6 +1024,15 @@ GCNTTIImpl::instCombineIntrinsic(InstCombiner &IC,
IntrinsicInst &II) const {
}
break;
}
+ case Intrinsic::amdgcn_wavefrontsize: {
+// TODO: this is a workaround for the pseudo-generic target one gets with
no
+// specified mcpu, which
@@ -6,48 +7,78 @@
; RUN: opt -O3 -S < %s | FileCheck -check-prefix=OPT %s
; RUN: opt -mtriple=amdgcn-- -O3 -S < %s | FileCheck -check-prefix=OPT %s
-; RUN: opt -mtriple=amdgcn-- -O3 -mattr=+wavefrontsize32 -S < %s | FileCheck
-check-prefix=OPT %s
-; RUN: opt -mtriple=amdgcn--
@@ -1024,6 +1024,15 @@ GCNTTIImpl::instCombineIntrinsic(InstCombiner &IC,
IntrinsicInst &II) const {
}
break;
}
+ case Intrinsic::amdgcn_wavefrontsize: {
+// TODO: this is a workaround for the pseudo-generic target one gets with
no
+// specified mcpu, which
@@ -318,6 +318,7 @@ TEST_F(TargetLibraryInfoTest, ValidProto) {
"declare void @qsort(i8*, i64, i64, i32 (i8*, i8*)*)\n"
"declare i64 @readlink(i8*, i8*, i64)\n"
"declare i8* @realloc(i8*, i64)\n"
+ "declare i8* @reallocarray(i8*, i64, i64)\n"
@@ -1024,6 +1024,15 @@ GCNTTIImpl::instCombineIntrinsic(InstCombiner &IC,
IntrinsicInst &II) const {
}
break;
}
+ case Intrinsic::amdgcn_wavefrontsize: {
+// TODO: this is a workaround for the pseudo-generic target one gets with
no
+// specified mcpu, which
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --version 5
arsenm wrote:
The tests for this should go in test/InstCombine/AMDGPU
https://github.com/llvm/llvm-project/pull/114481
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/111976
>From a53a138fca1de49afb1814b538fcb3f97bb66264 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 11 Oct 2024 14:33:32 +0400
Subject: [PATCH 1/8] clang: Remove requires system-linux from some driver
tests
@@ -0,0 +1,154 @@
+//===-- amdgpuintrin.h - AMDPGU intrinsic functions
---===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/111976
>From c9b2950be07d7272ece89b8bca6e3e982391a5c3 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 11 Oct 2024 14:33:32 +0400
Subject: [PATCH 1/8] clang: Remove requires system-linux from some driver
tests
https://github.com/arsenm approved this pull request.
https://github.com/llvm/llvm-project/pull/114774
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@@ -745,12 +745,12 @@ Let ``VT`` be a vector type and ``ET`` the element type
of ``VT``.
===
==
==
Name
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/111976
>From 947c0732cb8ebff4495a64d9fe7aa79ab3827926 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 11 Oct 2024 14:33:32 +0400
Subject: [PATCH 1/9] clang: Remove requires system-linux from some driver
tests
@@ -745,12 +745,8 @@ Let ``VT`` be a vector type and ``ET`` the element type of
``VT``.
===
==
==
NameO
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>From 2e3964fef9cef4b374a8451367a01c850b70e7e8 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Sat, 19 Oct 2024 02:39:06 +0400
Subject: [PATCH] clang/AMDGPU: Emit grid size builtins with range metadata
These
arsenm wrote:
### Merge activity
* **Nov 5, 3:43 PM EST**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/113038).
https://github.com/llvm/llvm-project/pull/113038
__
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@@ -722,6 +722,38 @@ static Value *emitFrexpBuiltin(CodeGenFunction &CGF, const
CallExpr *E,
return CGF.Builder.CreateExtractValue(Call, 0);
}
+static void emitSincosBuiltin(CodeGenFunction &CGF, const CallExpr *E,
+ llvm::Intrinsic::ID Intrinsi
@@ -722,6 +722,36 @@ static Value *emitFrexpBuiltin(CodeGenFunction &CGF, const
CallExpr *E,
return CGF.Builder.CreateExtractValue(Call, 0);
}
+static void emitSincosBuiltin(CodeGenFunction &CGF, const CallExpr *E,
+ llvm::Intrinsic::ID Intrinsi
arsenm wrote:
That sounds like MSVC's problem to solve. Why does the amount of stack size
matter
https://github.com/llvm/llvm-project/pull/114285
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https://github.com/arsenm commented:
If you really want to work around MSVC's bug, you could change tablegen to emit
the string literals as constant globals / StringLiteral
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https://github.com/arsenm commented:
Modify how? There seem to be too many things going on here. Description should
say how
https://github.com/llvm/llvm-project/pull/114550
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@@ -920,6 +920,124 @@ class AMDGPULowerModuleLDS {
return KernelToCreatedDynamicLDS;
}
+ static GlobalVariable *uniquifyGVPerKernel(Module &M, GlobalVariable *GV,
arsenm wrote:
This looks like an unrelated, separate change
https://github.com/llvm/llv
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@@ -920,6 +920,124 @@ class AMDGPULowerModuleLDS {
return KernelToCreatedDynamicLDS;
}
+ static GlobalVariable *uniquifyGVPerKernel(Module &M, GlobalVariable *GV,
arsenm wrote:
This still should be a separate PR
https://github.com/llvm/llvm-project/p
@@ -108,11 +108,15 @@ RawAddress CodeGenFunction::CreateTempAlloca(llvm::Type
*Ty, CharUnits Align,
if (AllocaAddr)
*AllocaAddr = Alloca;
llvm::Value *V = Alloca.getPointer();
+ assert((!getLangOpts().OpenCL ||
+ CGM.getTarget().getTargetAddressSpace(getASTAl
@@ -1672,10 +1672,11 @@ CodeGenTypes::GetFunctionType(const CGFunctionInfo &FI)
{
// Add type for sret argument.
if (IRFunctionArgs.hasSRetArg()) {
-QualType Ret = FI.getReturnType();
-unsigned AddressSpace = CGM.getTypes().getTargetAddressSpace(Ret);
+auto Ad
@@ -1648,6 +1648,8 @@ CodeGenTypes::GetFunctionType(const CGFunctionInfo &FI) {
// Add type for sret argument.
if (IRFunctionArgs.hasSRetArg()) {
QualType Ret = FI.getReturnType();
+if (CGM.getLangOpts().OpenCL)
+ Ret = getContext().getAddrSpaceQualType(Ret, La
@@ -108,11 +108,15 @@ RawAddress CodeGenFunction::CreateTempAlloca(llvm::Type
*Ty, CharUnits Align,
if (AllocaAddr)
*AllocaAddr = Alloca;
llvm::Value *V = Alloca.getPointer();
+ assert((!getLangOpts().OpenCL ||
+ CGM.getTarget().getTargetAddressSpace(getASTAl
@@ -1579,7 +1579,7 @@ NamedDecl *Sema::getCurFunctionOrMethodDecl() const {
}
LangAS Sema::getDefaultCXXMethodAddrSpace() const {
- if (getLangOpts().OpenCL)
+ if (getLangOpts().OpenCL || getLangOpts().OpenCLGenericAddressSpace)
arsenm wrote:
I think this w
@@ -5133,6 +5133,132 @@ RValue CodeGenFunction::EmitBuiltinExpr(const
GlobalDecl GD, unsigned BuiltinID,
Builder.SetInsertPoint(ContBB);
return RValue::get(nullptr);
}
+ case Builtin::BI__scoped_atomic_thread_fence: {
+auto ScopeModel = AtomicScopeModel::create(
@@ -5133,6 +5133,132 @@ RValue CodeGenFunction::EmitBuiltinExpr(const
GlobalDecl GD, unsigned BuiltinID,
Builder.SetInsertPoint(ContBB);
return RValue::get(nullptr);
}
+ case Builtin::BI__scoped_atomic_thread_fence: {
+auto ScopeModel = AtomicScopeModel::create(
@@ -5133,6 +5133,135 @@ RValue CodeGenFunction::EmitBuiltinExpr(const
GlobalDecl GD, unsigned BuiltinID,
Builder.SetInsertPoint(ContBB);
return RValue::get(nullptr);
}
+ case Builtin::BI__scoped_atomic_thread_fence: {
+auto ScopeModel = AtomicScopeModel::create(
@@ -5133,6 +5133,135 @@ RValue CodeGenFunction::EmitBuiltinExpr(const
GlobalDecl GD, unsigned BuiltinID,
Builder.SetInsertPoint(ContBB);
return RValue::get(nullptr);
}
+ case Builtin::BI__scoped_atomic_thread_fence: {
+auto ScopeModel = AtomicScopeModel::create(
@@ -5133,6 +5133,135 @@ RValue CodeGenFunction::EmitBuiltinExpr(const
GlobalDecl GD, unsigned BuiltinID,
Builder.SetInsertPoint(ContBB);
return RValue::get(nullptr);
}
+ case Builtin::BI__scoped_atomic_thread_fence: {
+auto ScopeModel = AtomicScopeModel::create(
@@ -0,0 +1,179 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 5
+// RUN: %clang_cc1 %s -emit-llvm -o - -triple=amdgcn-amd-amdhsa -ffreestanding
\
+// RUN: -fvisibility=hidden | FileCheck --check-prefix=AMDGCN %s
+//: %clan
@@ -3224,6 +3224,13 @@ def AllocA : GNULibBuiltin<"stdlib.h"> {
let AddBuiltinPrefixedAlias = 1;
}
+// Available in glibc by default since since 2.29 and in GNU mode before.
+def ReallocArray : GNULibBuiltin<"stdlib.h"> {
arsenm wrote:
The clang builtin cha
@@ -121,6 +121,7 @@ static const OffloadArchToStringMap arch_names[] = {
GFX(909), // gfx909
GFX(90a), // gfx90a
GFX(90c), // gfx90c
+{OffloadArch::GFX9_4_GENERIC, "gfx9-4-generic", "compute_amdgcn"},
arsenm wrote:
Why "9-4" and not "9.4"?
@@ -121,6 +121,7 @@ static const OffloadArchToStringMap arch_names[] = {
GFX(909), // gfx909
GFX(90a), // gfx90a
GFX(90c), // gfx90c
+{OffloadArch::GFX9_4_GENERIC, "gfx9-4-generic", "compute_amdgcn"},
arsenm wrote:
I guess this precedent is
@@ -85,6 +87,7 @@
// GFX940:
"target-features"="+16-bit-insts,+atomic-buffer-global-pk-add-f16-insts,+atomic-ds-pk-add-16-insts,+atomic-fadd-rtn-insts,+atomic-flat-pk-add-16-insts,+atomic-global-pk-add-bf16-inst,+ci-insts,+dl-insts,+dot1-insts,+dot10-insts,+dot2-insts,+dot3-inst
https://github.com/arsenm edited
https://github.com/llvm/llvm-project/pull/115190
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https://github.com/arsenm commented:
Test that the unsupported clang builtins are errors?
https://github.com/llvm/llvm-project/pull/115190
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@@ -322,22 +322,26 @@ foreach( t ${LIBCLC_TARGETS_TO_BUILD} )
if ( ARCH STREQUAL spirv OR ARCH STREQUAL spirv64 )
set( build_flags -O0 -finline-hint-functions -DCLC_SPIRV )
- set( opt_flags )
+ set( clc_opt_flags )
+ # Inline CLC functions into OpenCL
@@ -0,0 +1,38 @@
+#include
+#include
+#include
+
+#define CLC_SIGN(TYPE, F)
\
+ _CLC_DEF _CLC_OVERLOAD TYPE __clc_sign(TYPE x) {
\
+if (__clc_isnan(x)) {
https://github.com/arsenm edited
https://github.com/llvm/llvm-project/pull/115699
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@@ -152,6 +115,44 @@ bool SemaAMDGPU::CheckAMDGCNBuiltinFunctionCall(unsigned
BuiltinID,
return false;
}
+bool SemaAMDGPU::CheckMovDPPFunctionCall(CallExpr *TheCall, unsigned NumArgs,
arsenm wrote:
Start with lowercase
https://github.com/llvm/llvm-projec
@@ -703,6 +715,39 @@ SDValue BPFTargetLowering::LowerSELECT_CC(SDValue Op,
SelectionDAG &DAG) const {
return DAG.getNode(BPFISD::SELECT_CC, DL, VTs, Ops);
}
+SDValue BPFTargetLowering::LowerATOMIC_LOAD(SDValue Op,
+SelectionDAG &D
@@ -42,6 +42,14 @@ entry:
%f = fneg float %x
; CHECK: %f_vec = fneg <3 x float> %vec
%f_vec = fneg <3 x float> %vec
+; CHECK: %g = fpext float %x to double
arsenm wrote:
Needs bitcode compatibility test
https://github.com/llvm/llvm-project/pull/115894
_
@@ -148,6 +172,14 @@ entry:
%e = frem nnan float %x, %y
; CHECK: %e_vec = frem nnan ninf <3 x float> %vec, %vec
%e_vec = frem ninf nnan <3 x float> %vec, %vec
+; CHECK: %f = fpext nnan ninf float %x to double
+ %f = fpext ninf nnan float %x to double
+; CHECK: %f_vec = fp
https://github.com/arsenm approved this pull request.
https://github.com/llvm/llvm-project/pull/115190
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@@ -0,0 +1,39 @@
+// REQUIRES: amdgpu-registered-target
+
+// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -target-cpu gfx9-4-generic
-verify -emit-llvm -o - %s
+
+typedef unsigned int uint;
+
+typedef float v2f __attribute__((ext_vector_type(2)));
+typedef float v4f __attribu
arsenm wrote:
Is this still relevant?
https://github.com/llvm/llvm-project/pull/67721
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https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/111976
>From 3912e952fd6d9ae3f4c3dd9dc6ff8b72eee794db Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 11 Oct 2024 14:33:32 +0400
Subject: [PATCH 1/9] clang: Remove requires system-linux from some driver
tests
@@ -745,12 +745,10 @@ Let ``VT`` be a vector type and ``ET`` the element type
of ``VT``.
===
==
==
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