[PATCH] D112613: [Clang][RISCV] Change TARGET_BUILTIN to require zve32x for vector instruction

2022-01-20 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112613/new/ https://reviews.llvm.org/D112613 ___

[PATCH] D119837: [RISCV] Fix the include search path order between sysroot and resource folder

2022-02-20 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added a comment. Revert due to windows build regression fail: https://lab.llvm.org/buildbot/#/builders/216/builds/195 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D119837/new/ https://reviews.llvm.org/D119837 __

[PATCH] D119837: [RISCV] Fix the include search path order between sysroot and resource folder

2022-02-20 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added a comment. Recommit with windows path fix: https://reviews.llvm.org/rG47b1fa5fc48821eefefd157ed4af2f2cf3bacef4 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D119837/new/ https://reviews.llvm.org/D119837 ___

[PATCH] D120449: [RISCV][RVV] Add strict vfcvt intrinsics that have side effects for dynamically-set rounding mode

2022-03-02 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4683 +Ops.push_back(VL); +Ops.push_back(DAG.getUNDEF(XLenVT)); // Policy + } Is this operand for tail policy? if so why this is `UNDEF`? I guess this should be `TA

[PATCH] D120639: [RISCV] Pass -mno-relax to assembler when -fno-integrated-as specified

2022-03-02 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added inline comments. Comment at: clang/test/Driver/riscv-gnutools.c:19 +// Check default when -mno-relax and -fno-integrated-as specified +// RUN: %clang -target riscv32 --gcc-toolchain=%S/Inputs/basic_riscv32_tree -mno-relax -fno-integrated-as %s -### -c \ --

[PATCH] D120967: [NFC] Divide tests into smaller files

2022-03-03 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. Do you mind give more comment on SUMMARY to describe what you did? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D120967/new/ https://rev

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

2022-01-14 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng commandeered this revision. kito-cheng edited reviewers, added: HsiangKai; removed: kito-cheng. kito-cheng added a comment. @HsiangKai hand over this revision to me. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111617/new/ https://revie

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

2022-01-16 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng updated this revision to Diff 400358. kito-cheng added a comment. Herald added subscribers: alextsao1999, hiraditya. Changes: - Using different approach to implement to prevent build time explosion. - build time for `SemaRVVLookup.cpp` is ~6 sec in my machine. Repository: rG LLVM

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

2022-01-16 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added a comment. TL;DR: -- - Binary size of clang increase ~200k, which is +0.07% for debug build and +0.13% for release build. - Single file compilation speed up ~33x speed up for debug build and ~8.5x speed up for release build - Regression time reduce ~10% (`ninja check-all`,

[PATCH] D103228: [PoC][RISCV] Using pragma to register vector intrinsic

2022-01-16 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng abandoned this revision. kito-cheng added a comment. Herald added subscribers: alextsao1999, VincentWu, luke957, achieveartificialintelligence. Further development move to https://reviews.llvm.org/D111617 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://revi

[PATCH] D113237: [RISCV] Support I extension version 2.1

2021-12-09 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added a comment. There is several issue around the default extension version stuffs. - Should we add `-misa-spec=` option to Clang/LLVM? - Behavior for `zifencei` and `zicsr` with `i` 2.0? - How to encode the extension version in LLVM? by attribute or module flags? --- Should we add

[PATCH] D115430: [Clang][RISCV] Fix upper bound of RISC-V V type in debug info

2021-12-12 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added a comment. Could you re-upload diff with full context? You can create that via `git format-patch -1 -U999` or `git diff -U99 > mypatch.patch`. [1] https://llvm.org/docs/Phabricator.html#requesting-a-review-via-the-web-interface Repository: rG LLVM Github Monorepo C

[PATCH] D113237: [RISCV] Support I extension version 2.1

2021-12-16 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added a comment. @jrtc27 > Outside of the I/F/D special cases, where F/D don't really matter and I2p0 is > just I2p1Zicsr2p0_Zifencei2p0,, I thought the new policy was that ratified > extensions would never be changed, only new extensions published, and thus > version numbers are ba

[PATCH] D113237: [RISCV] Support I extension version 2.1

2021-12-16 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added a comment. @asb > Are you saying that there won't be a new ISA manual release (using whatever > naming scheme) that incorporates the ratified versions of bitmanip, crypto, > vector etc? Oh, I guess I using some word too strong there, here should have some newer release in fut

[PATCH] D97916: [Driver][RISCV] Support parsing multi-lib config from GCC.

2021-03-16 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng updated this revision to Diff 331024. kito-cheng added a comment. Address jrtc27's and luismarques comment ChangeLogs - Move all new test to clang/test/Driver/riscv-toolchain-gcc-multilib.c - I don't found good way to test that on windows, since ExecuteAndWait only allow to execute

[PATCH] D97916: [Driver][RISCV] Support parsing multi-lib config from GCC.

2021-03-16 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added a comment. > This still doesn't report that the multilib configuration came from GCC when > it succeeds, does it? I suppose that's not a deal-breaker, but it would be > nice to have. Would it be difficult to implement? There is some order issue is those function are executed be

[PATCH] D97916: [Driver][RISCV] Support parsing multi-lib config from GCC.

2021-03-17 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng updated this revision to Diff 331448. kito-cheng added a comment. ChangeLog: - Add more verbose message during reading GCC multilib configuration Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D97916/new/ https://reviews.llvm.org/D97916

[PATCH] D99319: [RISCV] [2/2] Add intrinsic for Zbb extension

2021-03-25 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added inline comments. Comment at: clang/lib/Headers/riscv_zbb_intrin.h:18 +// Zbb +static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_orc_b(int_xlen_t rs1) { + return __builtin_riscv_orc_b(rs1); craig.topper wrote: > craig.topper wrote: > > I think

[PATCH] D99320: [RISCV] [1/2] Add intrinsic for Zbb extension

2021-04-01 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added a comment. Created an issue for continue discuses on riscv-c-api-doc https://github.com/riscv/riscv-c-api-doc/issues/19 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99320/new/ https://reviews.llvm.org/D99320 _

[PATCH] D100611: [RISCV] Add new attribute __clang_riscv_builtin_alias for intrinsics.

2021-04-15 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added inline comments. Comment at: clang/test/CodeGen/RISCV/riscv-attr-builtin-alias.c:9 +#define __rvv_generic \ +static inline __attribute__((__always_inline__, __nodebug__, __overloadable__)) + I guess this is not needed anymore? or at least could b

[PATCH] D100615: [RISCV][Driver] Make the ordering of CmdArgs consistent between RISCV::Linker and baremetal::Linker

2021-04-15 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added a comment. Few more word for this issue, the option order is matter for linker both for GNU `ld` and `lld`, in the test @arcbbb provided, `ABC` will treat as undefined in `a.lds` if the order is wrong. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://

[PATCH] D100615: [RISCV][Driver] Make the ordering of CmdArgs consistent between RISCV::Linker and baremetal::Linker

2021-04-15 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added a comment. So I think it's more than consistent issue, it's a bug fix. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D100615/new/ https://reviews.llvm.org/D100615 ___ cfe-commits mailing

[PATCH] D100611: [RISCV] Add new attribute __clang_riscv_builtin_alias for intrinsics.

2021-04-15 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added a comment. Could you also check the compiler diagnostic messages? it will report `__builtin_rvv_vadd_vv_i8m1` or `vadd_generic` if argument type mis-match, which one you expected? I assume without `__clang_riscv_builtin_alias` clang will report `vadd_generic`? Repository: r

[PATCH] D94403: [RISCV] Implement new architecture extension macros

2021-01-17 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added a comment. That's my fault, I didn't specify the behavior of sub-extension clearly on the spec, but I think it would be great if we also define sub-extension marcos, since it would be easier to check when some core only implement sub-extension, and the code can just check the s

[PATCH] D94403: [RISCV] Implement new architecture extension macros

2021-01-19 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added a comment. Just note how current GCC implemented, GCC implement that like implied extension, e.g. `V` implied `Zvamo` and `Zvlsseg`, so `__riscv_zvamo` is naturally defined when `V`-ext is enabled. Comment at: clang/lib/Basic/Targets/RISCV.cpp:148 + if (HasB

[PATCH] D94403: [RISCV] Implement new architecture extension macros

2021-01-21 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng accepted this revision. kito-cheng added a comment. I believe the behavior has aligned to GCC now. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D94403/new/ https://reviews.llvm.org/D94403 ___

[PATCH] D94403: [RISCV] Implement new architecture extension macros

2021-01-21 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added a comment. In D94403#2512232 , @asb wrote: > @kito-cheng could you please confirm that this patch handles sub-extensions > in the same way GCC does. i.e. -march=rv32izbb0p92 defines `__riscv_zbb` but > NOT `__riscv_b`? Yes :) Reposito

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

2021-10-11 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng updated this revision to Diff 378729. kito-cheng added a comment. Changes: - Rebase to main - Remove b and zbproposedc. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105168/new/ https://reviews.llvm.org/D105168 Files: clang/include/c

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

2021-10-12 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added inline comments. Comment at: clang/lib/Sema/SemaLookup.cpp:923 + + const RVVIntrinsicInfo *Intrinsic = std::find_if( + std::begin(RVVIntrinsicInfos), std::end(RVVIntrinsicInfos), rogfer01 wrote: > Not for this patch: I think this table may

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

2021-10-13 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng updated this revision to Diff 379329. kito-cheng marked 11 inline comments as done. kito-cheng added a comment. Changes: - Address @craig.topper's comment - Add XLen to constructor of RISCVISAInfo. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llv

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

2021-10-13 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:388 +const std::vector &Features) { + std::unique_ptr ISAInfo(new RISCVISAInfo()); + assert(XLen == 32 || XLen == 64); craig.topper wrote: > Use > > ```

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

2021-10-17 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:39 + +static constexpr StringLiteral AllStdExts = "mafdqlcbjtpvn"; + craig.topper wrote: > 'b' shouldn't be in this list anymore? I would prefer to keep that for sync with ISA manual,

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

2021-10-17 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added a comment. Committed with one minor update for version of zba/zbb/zbc/zbs. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105168/new/ https://reviews.llvm.org/D105168 ___ cfe-commits mail

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

2021-10-17 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:39 + +static constexpr StringLiteral AllStdExts = "mafdqlcbjtpvn"; + kito-cheng wrote: > craig.topper wrote: > > 'b' shouldn't be in this list anymore? > I would prefer to keep that f

[PATCH] D111529: Specify Clang vector builtins.

2021-10-18 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added inline comments. Comment at: clang/docs/LanguageExtensions.rst:579 + NaNs, fmax() return a NaN. + ET __builtin_reduce_add(VT a) \+ integer and floatin

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

2021-08-19 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng updated this revision to Diff 367704. kito-cheng added a comment. Changes: - Fix build warning and build error with clang Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105168/new/ https://reviews.llvm.org/D105168 Files: clang/lib/Bas

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

2021-08-19 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added a comment. @asb Thanks for report that, there is no warning and build error when I build with GCC 7 (which is default compiler in Ubuntu 18.04), but I can reproduce that with clang 13, seems like I should switch my default compiler :P Repository: rG LLVM Github Monorepo CHA

[PATCH] D107290: [PoC][RISCV] Add support for the vscale_range attribute

2021-08-25 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp:106 + assert(RVVBitsMin % 128 == 0 && + "RVV requires vector length in multiples of 128!"); + assert(RVVBitsMax % 128 == 0 && RISC-V require VLEN in power of 2, m

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

2021-08-29 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng updated this revision to Diff 369364. kito-cheng added a comment. Changes: - Remove unused argument MArch for getExtensionVersion. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105168/new/ https://reviews.llvm.org/D105168 Files: clan

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

2021-08-29 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng marked an inline comment as done. kito-cheng added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:268 +// omitted from the version string. E.g., rv32i2p0, rv32i2, rv32i2p1. +static Error getExtensionVersion(StringRef MArch, StringRef Ext, StringRef In,

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

2021-09-02 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng updated this revision to Diff 370174. kito-cheng marked an inline comment as done. kito-cheng added a comment. Changes: - Check feature combination is valid. - Change return type of parseFeatures to llvm::Expected>. - Set default extension version in getExtensionVersion. Repository:

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

2021-09-02 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng marked 2 inline comments as done. kito-cheng added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:387 +ExtensionInfoIterator->Version.Minor); + if (ExtName == "e") +HasE = true; Jim wrote: > Does

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

2021-09-08 Thread Kito Cheng via Phabricator via cfe-commits
kito-cheng updated this revision to Diff 371509. kito-cheng marked 2 inline comments as done. kito-cheng added a comment. Changes: - Address Jim's comment. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105168/new/ https://reviews.llvm.org/D105168

<    1   2   3   4