[PATCH] D67065: [RISCV] Define __riscv_cmodel_medlow and __riscv_cmodel_medany correctly

kito-cheng created this revision. kito-cheng added reviewers: asb, apazos, lewis-revill. Herald added subscribers: cfe-commits, pzheng, s.egerton, lenary, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, shiva0217, nios

[PATCH] D67066: [RISCV] Add option aliases: -mcmodel=medany and -mcmodel=medlow

kito-cheng created this revision. kito-cheng added reviewers: asb, apazos. Herald added subscribers: cfe-commits, pzheng, s.egerton, lenary, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook

[PATCH] D72245: [PoC][RISCV][LTO] Pass target-abi via module flag metadata

kito-cheng added a comment. Seems like this patch mixed with LTO related changes? Could you clean it up? CHANGES SINCE LAST ACTION https://reviews.llvm.org/D72245/new/ https://reviews.llvm.org/D72245 ___ cfe-commits mailing list cfe-commits@lists

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

kito-cheng added inline comments. Comment at: clang/include/clang/Basic/RISCVVTypes.def:67 +RVV_VECTOR_TYPE_INT("__rvv_int8m2_t", RvvInt8m2, RvvInt8m2Ty, 16, 8, 1, true) +RVV_VECTOR_TYPE_INT("__rvv_int8m4_t", RvvInt8m4, RvvInt8m4Ty, 32, 8, 1, true) +RVV_VECTOR_TYPE_INT(

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

kito-cheng added a comment. Do you have implement register pair for rv32ifd_zfinx? I didn't saw the related implementation, but I could be wrong since I am not LLVM expert, in case you have implemented, you need a test case for that. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST AC

[PATCH] D89025: [RISCV] Add -mtune support

kito-cheng created this revision. kito-cheng added reviewers: asb, evandro, lenary, khchen. kito-cheng added projects: LLVM, clang. Herald added subscribers: llvm-commits, cfe-commits, dang, luismarques, apazos, sameer.abuasal, pzheng, pengfei, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o,

[PATCH] D89025: [RISCV] Add -mtune support

kito-cheng added a comment. > If possible that would good, since -mcpu is deprecated (for e.g. x86_64) or > unsupported in GCC (for e.g. RISC-V). So doing that would further align Clang > with GCC. But I wonder if this might be too problematic, in terms of > compatibility. I am also working on

[PATCH] D89025: [RISCV] Add -mtune support

kito-cheng updated this revision to Diff 298060. kito-cheng added a comment. ChangeLog - Fix wording in comment - Add more comment in testcase - Fix format issue. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D89025/new/ https://reviews.llvm.org/D89025 Files: clang/include/clang/Driv

[PATCH] D89025: [RISCV] Add -mtune support

kito-cheng marked 3 inline comments as done. kito-cheng added a comment. In D89025#2327749 , @luismarques wrote: > In D89025#2324334 , @khchen wrote: > >> RISCV supports `-mcpu` with default empty arch to align gcc'

[PATCH] D89025: [RISCV] Add -mtune support

kito-cheng updated this revision to Diff 298293. kito-cheng added a comment. ChangeLog: - Update testcase according to MaskRay's suggestion. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D89025/new/ https://reviews.llvm.org/D89025 Files: clang/include/clang/Driver/Options.td clang/

[PATCH] D89025: [RISCV] Add -mtune support

kito-cheng marked an inline comment as done. kito-cheng added a comment. @MaskRay Thanks, that's first time I know the suffix `-SAME` :P CHANGES SINCE LAST ACTION https://reviews.llvm.org/D89025/new/ https://reviews.llvm.org/D89025 ___ cfe-commits

[PATCH] D102839: [RISCV][Clang] Add -mno-div option to disable hardware int division

kito-cheng added a comment. We have Zmmul extension in the ISA spec now, that's equivalent to `-mno-div` , so I suggest we should go forward to implement that extension rather than `-mno-div`. https://github.com/riscv/riscv-isa-manual/pull/648 CHANGES SINCE LAST ACTION https://reviews.llvm.

[PATCH] D103228: [PoC][RISCV] Using pragma to register vector intrinsic

kito-cheng created this revision. Herald added subscribers: vkmr, frasercrmck, dexonsmith, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook,

[PATCH] D103228: [PoC][RISCV] Using pragma to register vector intrinsic

kito-cheng updated this revision to Diff 348175. kito-cheng added a comment. Minor cleanup Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D103228/new/ https://reviews.llvm.org/D103228 Files: clang/include/clang/Basic/Builtins.h clang/include/cla

[PATCH] D103228: [PoC][RISCV] Using pragma to register vector intrinsic

kito-cheng added inline comments. Comment at: clang/lib/Sema/SemaRISCV.cpp:21 + PP.getIdentifierTable(), PP.getLangOpts(), Builtin::RISCV_VECTOR_KIND); + Builtin::RegisterOverloadBuiltinFunc F = [](Sema &S, const Builtin::Info &BI, +

[PATCH] D102839: [RISCV][Clang] Add -mno-div option to disable hardware int division

kito-cheng added a comment. Personally I prefer to deprecate `-mno-div` soon, but based on the rule for RISC-V GNU toolchain, it need to wait `Zmmul` extension frozen. My plan is deprecate the `-mno-div` and emit warning to tell user should use `Zmmul` instead once it frozen. CHANGES SINCE LAS

[PATCH] D103603: [Sema][RISCV] Allow ?: to select Typedef BuiltinType in C

kito-cheng added a comment. Testcase for AArch64/SVE: #include svint8_t a(); __SVInt8_t b(); svint8_t foo(int cond){ return cond ? a(): b(); } Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D103603/new/ https://reviews.llvm.org/

[PATCH] D103603: [Sema][RISCV] Allow ?: to select Typedef BuiltinType in C

kito-cheng added a comment. The testcase I provided in last comment could be compile successfully with aarch64-gcc, but failed on clang. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D103603/new/ https://reviews.llvm.org/D103603 __

[PATCH] D94583: [RISCV] Update V extension to v1.0-draft 08a0b464.

kito-cheng added a comment. @jrtc27 just let you know I have same concern too, that's one major reason why we don't upstream those extension on GNU toolchain... we are intend to introduce an internal revision number on ELF attribute in near future, e.g. v-ext 0.9.1 / v0p9p1 to prevent compatibl

[PATCH] D94403: [RISCV] Implement new architecture extension macros

kito-cheng accepted this revision. kito-cheng added a comment. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D94403/new/ https://reviews.llvm.org/D94403 ___ cfe-commits mailing list cfe-commits@lists

[PATCH] D94583: [RISCV] Update V extension to v1.0-draft 08a0b464.

kito-cheng added a comment. Could you also update macros and attributes which implemented in https://reviews.llvm.org/D94403 and https://reviews.llvm.org/D94931 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D94583/new/ https://reviews.llvm.org/D945

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

kito-cheng added a comment. Seems like conflict with D108187 , will update after testing :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105168/new/ https://reviews.llvm.org/D105168 _

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

kito-cheng updated this revision to Diff 372939. kito-cheng added a comment. Changes: - Rebase to `main`. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105168/new/ https://reviews.llvm.org/D105168 Files: clang/include/clang/Basic/DiagnosticComm

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

kito-cheng added a comment. Herald added a subscriber: achieveartificialintelligence. ping Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105168/new/ https://reviews.llvm.org/D105168 ___ cfe-commits maili

[PATCH] D103228: [PoC][RISCV] Using pragma to register vector intrinsic

kito-cheng updated this revision to Diff 349784. kito-cheng added a comment. Changes: - Using less invasive way to add intrinsic functions. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D103228/new/ https://reviews.llvm.org/D103228 Files: clang/

[PATCH] D103228: [PoC][RISCV] Using pragma to register vector intrinsic

kito-cheng updated this revision to Diff 349785. kito-cheng added a comment. Herald added a project: LLVM. Herald added a subscriber: llvm-commits. Reupload. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D103228/new/ https://reviews.llvm.org/D103228

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

kito-cheng updated this revision to Diff 364758. kito-cheng marked an inline comment as done. kito-cheng added a comment. Changes: - Forbid copy ctor and operator= for RISCVISAInfo. - Move RISCVISAInfo's constructor to private. - Refine RISCVISAInfo::parse* and made they become static function. -

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

kito-cheng added inline comments. Comment at: llvm/include/llvm/Support/RISCVISAInfo.h:31 +public: + RISCVISAInfo() : XLen(0), FLen(0) {} + jrtc27 wrote: > Does Exts need initialising to be empty here? I can never remember std::map has default construct that wil

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

kito-cheng added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:41 +static const RISCVSupportedExtensionInfo SupportedExtensionInfos[] = { +{"i", RISCVExtensionVersion{2, 0}}, {"e", RISCVExtensionVersion{1, 9}}, +{"m", RISCVExtensionVersion{2, 0}}, {"a", R

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

kito-cheng updated this revision to Diff 365941. kito-cheng added a comment. Changes: - Rename class, strip the `Info`: - `RISCVSupportedExtensionInfo` -> `RISCVSupportedExtension` - Rename variables: - `SupportedExtensionInfos` -> `SupportedExtensions` - `SupportedExperimentalExtensionInfo

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

kito-cheng added a comment. ping Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105168/new/ https://reviews.llvm.org/D105168 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/

[PATCH] D105091: [RISCV] Pass -u to linker correctly.

kito-cheng created this revision. Herald added subscribers: vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook, johnrusso,

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to to RISCVArchStringParser.

kito-cheng created this revision. Herald added subscribers: vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook, johnrusso,

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to to RISCVArchStringParser.

kito-cheng updated this revision to Diff 355459. kito-cheng added a comment. Minor clean up. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105168/new/ https://reviews.llvm.org/D105168 Files: clang/lib/Basic/Targets/RISCV.cpp clang/lib/Basic/Ta

[PATCH] D105091: [RISCV] Pass -u to linker correctly.

kito-cheng updated this revision to Diff 355783. kito-cheng added a comment. Address @MaskRay's comment Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105091/new/ https://reviews.llvm.org/D105091 Files: clang/lib/Driver/ToolChains/RISCVToolchain.

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to to RISCVArchStringParser.

kito-cheng updated this revision to Diff 356890. kito-cheng added a comment. Changes: - Rebase to master, resolve conflict for zvamo change. - New function filterSupportedExtensionInfosByName to simplify itearting SupportedExtensionInfos. - Remove RISCVTargetInfo::HasA, look-up ISAInfo instead.

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to to RISCVArchStringParser.

kito-cheng marked 13 inline comments as done. kito-cheng added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:230 + unsigned XLEN = getTriple().isArch64Bit() ? 64 : 32; + if (auto E = ISAInfo.parse(XLEN, Features)) +return false; jrtc27 wrot

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to to RISCVArchStringParser.

kito-cheng updated this revision to Diff 356916. kito-cheng marked 3 inline comments as done. kito-cheng added a comment. Minor update for createStringError. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105168/new/ https://reviews.llvm.org/D105168

[PATCH] D105091: [RISCV] Pass -u to linker correctly.

kito-cheng added inline comments. Comment at: clang/test/Driver/riscv-args.c:5 // RUN: %clang -### -target riscv32 \ // RUN: --gcc-toolchain= -Xlinker --defsym=FOO=10 -T a.lds %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-LD %s MaskRay wrote: > MaskRay

[PATCH] D105091: [RISCV] Pass -u to linker correctly.

kito-cheng updated this revision to Diff 357152. kito-cheng added a comment. Update testcase. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105091/new/ https://reviews.llvm.org/D105091 Files: clang/lib/Driver/ToolChains/RISCVToolchain.cpp clan

[PATCH] D103228: [PoC][RISCV] Using pragma to register vector intrinsic

kito-cheng planned changes to this revision. kito-cheng added a comment. Update: Send RFC[1] to cfe-dev list, and got useful feedback from OpenCL: - OpenCL's way is the fastest way to declare builtin, since it defer until symbol look-up, however that require re-implement vector intrinsic with t

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

kito-cheng added inline comments. Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:195 if (MArch.startswith_insensitive("rv32")) { // FIXME: parse `March` to find `D` extension properly if (MArch.substr(4).contains_insensitive("d") || khchen wr

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

kito-cheng updated this revision to Diff 358130. kito-cheng added a comment. Changes: - Using RISCVISAInfo in riscv::getRISCVABI - Allow rv32e for -march. - Address review comments. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105168/new/ https:/

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

kito-cheng added inline comments. Comment at: llvm/include/llvm/Support/RISCVISAInfo.h:42 + // keep entries in canonical order of extension. + typedef std::map + OrderedExtensionMap; craig.topper wrote: > Could this be a sorted vector? Would require a good

[PATCH] D105254: [RISCV] Support machine constraint "S"

kito-cheng added a comment. RISC-V GCC site has update the document for 'S'. https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=18a463bb666cc8f3421589e7641ec617acb84741 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105254/new/ https://reviews.llvm.org/

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

kito-cheng updated this revision to Diff 358193. kito-cheng added a comment. Changes: - Handle arch attribute emition in RISCVTargetStreamer.cpp, thanks @khchen for reminding me that! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105168/new/ http

[PATCH] D105091: [RISCV] Pass -u to linker correctly.

kito-cheng updated this revision to Diff 358314. kito-cheng added a comment. Changes: - Add 2 testcases Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105091/new/ https://reviews.llvm.org/D105091 Files: clang/lib/Driver/ToolChains/RISCVToolchain

[PATCH] D105091: [RISCV] Pass -u to linker correctly.

kito-cheng updated this revision to Diff 358494. kito-cheng added a comment. Changes: - Update testcase again. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105091/new/ https://reviews.llvm.org/D105091 Files: clang/lib/Driver/ToolChains/RISCVTo

[PATCH] D112398: [RISCV] Add ABI testing for Float16.

kito-cheng added a comment. Herald added subscribers: VincentWu, luke957. From the psABI aspect, we already included that by this PR , this PR added size and alignment for `_Float16`, and we didn't added extra rule for that, because

[PATCH] D97912: [doc] Document that __fp16 will apply default argument promotion rule.

kito-cheng created this revision. kito-cheng requested review of this revision. Herald added a project: clang. Herald added a subscriber: cfe-commits. ACLE didn't specify the default argument promotion rule on __fp16, but the current implementation both on GCC and clang are applied default argumen

[PATCH] D97912: [doc] Document that __fp16 will apply default argument promotion rule.

kito-cheng added a comment. Update SUMMARY, first version I just incorrectly said ACLE didn't clarify the default argument promotion rule, but I found that in ABI spec later. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D97912/new/ https://reviews

[PATCH] D97916: [Driver][RISCV] Support parsing multi-lib config from GCC.

kito-cheng created this revision. Herald added subscribers: vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook, johnrusso,

[PATCH] D97916: [Driver][RISCV] Support parsing multi-lib config from GCC.

kito-cheng updated this revision to Diff 328040. kito-cheng added a comment. Minor clean up Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D97916/new/ https://reviews.llvm.org/D97916 Files: clang/include/clang/Basic/DiagnosticDriverKinds.td clan

[PATCH] D97916: [Driver][RISCV] Support parsing multi-lib config from GCC.

kito-cheng added inline comments. Comment at: clang/test/Driver/riscv64-toolchain.c:158 +// RUN: %clang %s \ +// RUN: -target riscv64-unknown-elf \ +// RUN: --gcc-toolchain=%S/Inputs/multilib_riscv64_elf_sdk \ MaskRay wrote: > Hmm. I happened to have posted

[PATCH] D97916: [Driver][RISCV] Support parsing multi-lib config from GCC.

kito-cheng updated this revision to Diff 328062. kito-cheng added a comment. Address MaskRay's comment and apply clang-format. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D97916/new/ https://reviews.llvm.org/D97916 Files: clang/include/clang/Ba

[PATCH] D97916: [Driver][RISCV] Support parsing multi-lib config from GCC.

kito-cheng marked 3 inline comments as done. kito-cheng added inline comments. Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:727 +{ + /* Default code model is small(medlow). */ + StringRef CodeModel; MaskRay wrote: > `//` Thanks, I guess some time my

[PATCH] D97916: [Driver][RISCV] Support parsing multi-lib config from GCC.

kito-cheng marked 5 inline comments as done. kito-cheng added a comment. Here is another solution for flexible multi-lib configuration I consider before: - Add an option called `-fmultilib-config=` - Using same or similar syntax with GCC's `--with-multilib-generator` But the problem is it's real

[PATCH] D97916: [Driver][RISCV] Support parsing multi-lib config from GCC.

kito-cheng updated this revision to Diff 328406. kito-cheng marked 2 inline comments as done. kito-cheng added a comment. - Fix build issue. - Address Jim Lin's and Zakk's comment Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D97916/new/ https://rev

[PATCH] D97916: [Driver][RISCV] Support parsing multi-lib config from GCC.

kito-cheng updated this revision to Diff 328407. kito-cheng added a comment. Reupload Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D97916/new/ https://reviews.llvm.org/D97916 Files: clang/include/clang/Basic/DiagnosticDriverKinds.td clang/incl

[PATCH] D98012: [RFC][doc] Document that RISC-V's __fp16 has different behavior

kito-cheng created this revision. Herald added subscribers: vkmr, luismarques, sameer.abuasal, s.egerton, Jim, PkmX, rogfer01, shiva0217, simoncook. kito-cheng requested review of this revision. Herald added a project: clang. Herald added a subscriber: cfe-commits. RISC-V has a draft extension fo

[PATCH] D98616: [RISCV] Add inline asm constraint 'v' in Clang for RISC-V 'V'.

kito-cheng added a comment. GCC use `vr` for vector register and `vm` for vector mask register. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D98616/new/ https://reviews.llvm.org/D98616 ___ cfe-commits ma

[PATCH] D98616: [RISCV] Add inline asm constraint 'v' in Clang for RISC-V 'V'.

kito-cheng added a comment. Provide more implementation detail on GCC, - if a letter are used as a prefix of multi-char constraint, then it can't be used as a single letter constraint - e.g. If we defined `vr` and `vm` then we can't define `v` as constraint - constraint with same prefix should

[PATCH] D136570: [RISCV] Add Svnapot extension

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM, thanks :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D136570/new/ https://reviews.llvm.org/D136570

[PATCH] D136812: [RISCV] Drop single letter b extension support

kito-cheng created this revision. Herald added subscribers: sunshaoce, VincentWu, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, niosHD, sabuasal,

[PATCH] D136817: [RISCV] Add H extension

kito-cheng created this revision. kito-cheng added reviewers: asb, craig.topper, reames. Herald added subscribers: sunshaoce, VincentWu, StephenFan, vkmr, frasercrmck, jdoerfert, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinM

[PATCH] D134050: [clang][RISCV][NFC][WIP/RFC] Move riscv-abi.cpp and riscv32-*abi.c tests to use update_cc_test_checks.py

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM, manually update such testcase is really painful! CHANGES SINCE LAST ACTION https://reviews.llvm.org/D134050/new/ https://reviews.llvm.org/D134050

[PATCH] D134050: [clang][RISCV][NFC][WIP/RFC] Move riscv-abi.cpp and riscv32-*abi.c tests to use update_cc_test_checks.py

kito-cheng added a comment. Oh, it's still `[WIP/RFC]`, but anyway that's really good way to go. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D134050/new/ https://reviews.llvm.org/D134050 ___ cfe-commits mailing list cfe-commits@lists.llvm.or

[PATCH] D136812: [RISCV] Drop single letter b extension support

This revision was automatically updated to reflect the committed changes. Closed by commit rGae116f43ff14: [RISCV] Drop single letter b extension support (authored by kito-cheng). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D136812/new/ https://rev

[PATCH] D136817: [RISCV] Add H extension

kito-cheng planned changes to this revision. kito-cheng added a comment. Let me do that within this patch :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D136817/new/ https://reviews.llvm.org/D136817 ___

[PATCH] D136817: [RISCV] Add H extension

kito-cheng updated this revision to Diff 471386. kito-cheng added a comment. Update instructions which are belong H extension now. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D136817/new/ https://reviews.llvm.org/D136817 Files: clang/test/Prepr

[PATCH] D136817: [RISCV] Add H extension

kito-cheng added inline comments. Comment at: llvm/test/MC/RISCV/rvi-aliases-valid.s:270 -# CHECK-S-OBJ: hfence.vvma a0 -hfence.vvma a0 Note: Those testcase are moved to `rv32ih-aliases-valid.s`, not just removed. Repository: rG LLVM Github Monorepo CHANGE

[PATCH] D136817: [RISCV] Add H extension

kito-cheng updated this revision to Diff 471701. kito-cheng added a comment. Changes: - Update doc, H is support assembly only. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D136817/new/ https://reviews.llvm.org/D136817 Files: clang/test/Preproc

[PATCH] D136817: [RISCV] Add H extension

kito-cheng marked an inline comment as done. kito-cheng added inline comments. Comment at: llvm/docs/RISCVUsage.rst:54 ``F``Supported + ``H``Supported ``M``Supported reames wrote: > If I'm reading the code right

[PATCH] D136930: [RISCV] Support -mcpu/mtune=native

kito-cheng added a comment. Maybe we could add test like aarch64? https://github.com/llvm/llvm-project/blob/main/clang/test/Driver/aarch64-mcpu.c#L20 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D136930/new/ https://reviews.llvm.org/D136930 _

[PATCH] D136930: [RISCV] Support -mcpu/mtune=native

kito-cheng added inline comments. Comment at: clang/lib/Driver/ToolChains/Clang.cpp:2190 CmdArgs.push_back("-tune-cpu"); -CmdArgs.push_back(A->getValue()); +if (strcmp(A->getValue(), "native") == 0) + CmdArgs.push_back(Args.MakeArgString(llvm::sys::getHostCPUNam

[PATCH] D131345: [RISC-V][HWASAN] Enable HWASAN for RISC-V architecture

kito-cheng accepted this revision. kito-cheng added a comment. > It relies on a runtime check: during init runtime makes > PR_{SET,GET}_TAGGED_ADDR_CTRL calls and if they're not supported, it fails > with an error. So burden of checking if J extension is present is on Linux > kernel. Sounds go

[PATCH] D131708: [RISCV] Change how mtune aliases are implemented.

kito-cheng added inline comments. Comment at: clang/test/Driver/riscv-cpus.c:27 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=rocket | FileCheck -check-prefix=MTUNE-ROCKET-64 %s -// MTUNE-ROCKET-64: "-tune-cpu" "rocket-rv64" - -// RUN: %clang --target=riscv32 -### -c %

[PATCH] D131677: [clang][RISCV] Fix incorrect ABI lowering for inherited structs under hard-float ABIs

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM, result has compared with GCC for `rv32gc/ilp32d` and `rv64gc/lp64d`. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D131677/new/ https://reviews.llvm.org/D131677

[PATCH] D121670: [RISCV] Add zihintntl instructions

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D121670/new/ https://reviews.llvm.org/D121670 ___

[PATCH] D121779: [RISCV] Add zihintntl compressed instructions

kito-cheng added inline comments. Herald added subscribers: sunshaoce, StephenFan, shiva0217. Comment at: llvm/test/MC/RISCV/rv32zihintntlc-valid.s:42 +# CHECK-ASM: encoding: [0x16,0x90] +c.ntl.all Could you add an invalid check for `c.ntl` instruction to make su

[PATCH] D139995: [RISCV] Refactor RVV Policy by structure

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D139995/new/ https://reviews.llvm.org/D139995 ___

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

kito-cheng added a comment. Ken has updated spec to clarify requirements of those vector crypto extensions: https://github.com/riscv/riscv-crypto/commit/40695306f628e6dc764d1d0f35392eac792d2c3b These Vector Crypto Extensions can be built on any RISC-V base. However, XLEN=32 implementations

[PATCH] D140361: [RISCV] Merge Masked and unMasked RVV manual codegen

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM, thanks for clean up this! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D140361/new/ https://reviews.llvm.org/D140361

[PATCH] D140389: [NFC][RISCV] Rename data member 'DefaultPolicy' to 'PolicyAttrs'

kito-cheng added a comment. Could you rebase with D140361 ? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D140389/new/ https://reviews.llvm.org/D140389 ___ cfe-commits ma

[PATCH] D136817: [RISCV] Add H extension

kito-cheng updated this revision to Diff 485360. kito-cheng added a comment. Changes: - Rebase to main - Add negative test. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D136817/new/ https://reviews.llvm.org/D136817 Files: clang/test/Preprocesso

[PATCH] D140693: [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march

kito-cheng created this revision. kito-cheng added reviewers: craig.topper, asb, reames. Herald added subscribers: sunshaoce, VincentWu, StephenFan, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rog

[PATCH] D140692: [RISCV] Add Svbmpt extension support.

kito-cheng added a comment. You are typo on title and commit log, it should be `Svpbmt` not `Svbmpt`, but the code changes are right, and you need to update `llvm/docs/RISCVUsage.rst` too. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D140692/new/

[PATCH] D140692: [RISCV] Add Svpbmt extension support.

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D140692/new/ https://reviews.llvm.org/D140692 ___

[PATCH] D140662: [NFC][Clang][RISCV] Reduce boilerplate when determining prototype for segment loads

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. Go ahead, thanks for clean up! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D140662/new/ https://reviews.llvm.org/D140662 _

[PATCH] D140693: [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march

kito-cheng added a comment. > So if I read this correctly, the effect of this is that we never pass > -target-cpu to the backend after this patch and will only pass > -target-feature and -tune-cpu? Yes, that's prevent us taking any extensions from `-target-cpu`, so always pass `-target-feature

[PATCH] D140693: [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march

kito-cheng added inline comments. Comment at: clang/lib/Driver/ToolChains/Clang.cpp:5457 + // RISC-V will handle -mcpu option in Clang::AddRISCVTargetArgs. + if (!Triple.isRISCV()) { +// Add the target cpu craig.topper wrote: > I wonder if we should stop ge

[PATCH] D140693: [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march

kito-cheng updated this revision to Diff 485674. kito-cheng added a comment. Changes: - Stop calling getRISCVTargetCPU in getCPUName. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D140693/new/ https://reviews.llvm.org/D140693 Files: clang/lib/Dr

[PATCH] D140693: [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march

kito-cheng added inline comments. Comment at: clang/lib/Driver/ToolChains/Clang.cpp:5457 + // RISC-V will handle -mcpu option in Clang::AddRISCVTargetArgs. + if (!Triple.isRISCV()) { +// Add the target cpu craig.topper wrote: > kito-cheng wrote: > > craig.t

[PATCH] D136817: [RISCV] Add H extension

kito-cheng added a comment. ping :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D136817/new/ https://reviews.llvm.org/D136817 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.o

[PATCH] D140693: [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march

kito-cheng planned changes to this revision. kito-cheng added a comment. - @craig.topper has suggested we could pass all extension with `-` or `+` to neutralize the effect of the `-target-cpu`, that's less intrusive way. - Add release note to mention the behavior change. Repository: rG LLVM G

[PATCH] D136817: [RISCV] Add H extension

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGf4c887c3a840: [RISCV] Add H extension (authored by kito-cheng). Changed prior to commit: https://reviews.llvm.org/D136817?vs=485360&id=487624#toc

[PATCH] D140693: [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march

kito-cheng updated this revision to Diff 488173. kito-cheng added a comment. Herald added subscribers: llvm-commits, hiraditya. Herald added a project: LLVM. Changes: - Add release note to mention the behavior change for `-march` and `-mcpu`. - New way to implement this behavior, passing all supp

[PATCH] D140693: [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march

kito-cheng updated this revision to Diff 488175. kito-cheng added a comment. Changes: - Trim unexpected change by clang-format Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D140693/new/ https://reviews.llvm.org/D140693 Files: clang/docs/ReleaseN

[PATCH] D140693: [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march

kito-cheng added inline comments. Comment at: clang/test/Driver/riscv-cpus.c:13 +// MCPU-SYNTACORE-SCR1-BASE: "-target-feature" "+c" +// MCPU-SYNTACORE-SCR1-BASE: "-target-feature" "-64bit" // MCPU-SYNTACORE-SCR1-BASE: "-target-abi" "ilp32" Need to break this in

[PATCH] D136817: [RISCV] Add H extension

kito-cheng marked an inline comment as done. kito-cheng added a comment. ping :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D136817/new/ https://reviews.llvm.org/D136817 ___ cfe-commits mailing list cf

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