Author: Kerry McLaughlin
Date: 2020-06-24T10:32:19+01:00
New Revision: 3d6cab271c7cecf105b77834d837ccd4406700d7
URL:
https://github.com/llvm/llvm-project/commit/3d6cab271c7cecf105b77834d837ccd4406700d7
DIFF:
https://github.com/llvm/llvm-project/commit/3d6cab271c7cecf105b77834d837ccd4406700d7.di
Author: Kerry McLaughlin
Date: 2020-06-26T11:05:56+01:00
New Revision: edcfef8fee134cf98e0e812a6569c4900045d31c
URL:
https://github.com/llvm/llvm-project/commit/edcfef8fee134cf98e0e812a6569c4900045d31c
DIFF:
https://github.com/llvm/llvm-project/commit/edcfef8fee134cf98e0e812a6569c4900045d31c.di
@@ -257,7 +257,7 @@ class ImmCheck {
}
class Inst ft, list ch, MemEltType met> {
+ list ft, list ch, MemEltType met =
MemEltTyDefault> {
kmclaughlin-arm wrote:
Hi @dtemirbulatov, this change is just to set the default MemEltType to
MemEltTyDefault
https://github.com/kmclaughlin-arm closed
https://github.com/llvm/llvm-project/pull/69725
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@@ -0,0 +1,1562 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -D__ARM_FEATURE_SME2 -triple
aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S
-disable-O0-optnone -Werror -Wall -emit-llv
@@ -296,5 +296,28 @@ multiclass ZAAddSub {
}
}
+
+// SME2 - MIN, MAX
+
+multiclass MinMaxIntr {
+ def SVS # NAME : SInst<"sv" # i # "[" # zm # "_{d}_" # mul # "]", t, "csil",
MergeNone, "aa
@@ -0,0 +1,1562 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -D__ARM_FEATURE_SME2 -triple
aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S
-disable-O0-optnone -Werror -Wall -emit-llv
https://github.com/kmclaughlin-arm approved this pull request.
Thanks @SamTebbs33, I just have one small suggestion but otherwise this LGTM.
https://github.com/llvm/llvm-project/pull/71688
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https://github.com/kmclaughlin-arm edited
https://github.com/llvm/llvm-project/pull/71688
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@@ -1987,8 +1987,26 @@ defm SVREVD : SInstZPZ<"svrevd", "csilUcUsUiUl",
"aarch64_sve_revd">;
// SME intrinsics which operate only on vectors and do not require ZA should
be added here,
// as they could possibly become SVE instructions in the future.
+multiclass MinMaxIntr {
@@ -0,0 +1,444 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2
-target-feature +sve2 -S -disable-O0-optnone -Werror -Wall -emit-llv
@@ -1981,6 +1979,11 @@ def SVCNTP_COUNT : SInst<"svcntp_{d}", "n}i",
"QcQsQiQl", MergeNone, "aarch64_sv
defm SVREVD : SInstZPZ<"svrevd", "csilUcUsUiUl", "aarch64_sve_revd">;
}
+let TargetGuard = "sve2p1|sme2" in {
+ def SVPTRUE_COUNT : SInst<"svptrue_{d}", "}v", "QcQsQiQl",
@@ -0,0 +1,34 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S
-disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | FileCheck %s
https://github.com/kmclaughlin-arm updated
https://github.com/llvm/llvm-project/pull/71176
>From 7ff0f13bdf5f81681145d63843c66a27e77ecc3b Mon Sep 17 00:00:00 2001
From: Kerry McLaughlin
Date: Thu, 2 Nov 2023 17:02:32 +
Subject: [PATCH] [Clang][SME2] Add outer product and accumulate/subtract
https://github.com/kmclaughlin-arm updated
https://github.com/llvm/llvm-project/pull/71176
>From 7ff0f13bdf5f81681145d63843c66a27e77ecc3b Mon Sep 17 00:00:00 2001
From: Kerry McLaughlin
Date: Thu, 2 Nov 2023 17:02:32 +
Subject: [PATCH 1/2] [Clang][SME2] Add outer product and accumulate/subt
https://github.com/kmclaughlin-arm edited
https://github.com/llvm/llvm-project/pull/71191
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https://github.com/kmclaughlin-arm approved this pull request.
LGTM!
https://github.com/llvm/llvm-project/pull/74450
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@@ -1316,6 +1321,13 @@ def SVSET_3_BF16 : SInst<"svset3[_{d}]", "33id", "b",
MergeNone, "", [IsTupleSet
def SVSET_4_BF16 : SInst<"svset4[_{d}]", "44id", "b", MergeNone, "",
[IsTupleSet], [ImmCheck<1, ImmCheck0_3>]>;
}
+let TargetGuard = "sve2p1" in {
+ def SVGET_2_B : SInst
@@ -1316,6 +1321,13 @@ def SVSET_3_BF16 : SInst<"svset3[_{d}]", "33id", "b",
MergeNone, "", [IsTupleSet
def SVSET_4_BF16 : SInst<"svset4[_{d}]", "44id", "b", MergeNone, "",
[IsTupleSet], [ImmCheck<1, ImmCheck0_3>]>;
}
+let TargetGuard = "sve2p1" in {
+ def SVGET_2_B : SInst
@@ -2130,6 +2130,9 @@ let TargetGuard = "sme2" in {
def SVURSHL_X2 : SInst<"svrshl[_{d}_x2]", "222", "UcUsUiUl", MergeNone,
"aarch64_sve_urshl_x2", [IsStreaming], []>;
def SVSRSHL_X4 : SInst<"svrshl[_{d}_x4]", "444", "csil", MergeNone,
"aarch64_sve_srshl_x4", [IsStream
https://github.com/kmclaughlin-arm approved this pull request.
Thank you @dtemirbulatov, LGTM!
https://github.com/llvm/llvm-project/pull/74720
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https://github.com/kmclaughlin-arm edited
https://github.com/llvm/llvm-project/pull/74594
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@@ -167,3 +167,23 @@ void test_svpmov_lane(){
zn_u32 = svpmov_lane_u32_m(zn_u32, pn, 5); // expected-error {{argument
value 5 is outside the valid range [1, 3]}}
zn_u64 = svpmov_lane_u64_m(zn_u64, pn, 8); // expected-error {{argument
value 8 is outside the valid range [1,
@@ -167,3 +167,23 @@ void test_svpmov_lane(){
zn_u32 = svpmov_lane_u32_m(zn_u32, pn, 5); // expected-error {{argument
value 5 is outside the valid range [1, 3]}}
zn_u64 = svpmov_lane_u64_m(zn_u64, pn, 8); // expected-error {{argument
value 8 is outside the valid range [1,
https://github.com/kmclaughlin-arm commented:
Thank you for adding the tests @CarolineConcatto!
https://github.com/llvm/llvm-project/pull/74594
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@@ -1316,6 +1321,13 @@ def SVSET_3_BF16 : SInst<"svset3[_{d}]", "33id", "b",
MergeNone, "", [IsTupleSet
def SVSET_4_BF16 : SInst<"svset4[_{d}]", "44id", "b", MergeNone, "",
[IsTupleSet], [ImmCheck<1, ImmCheck0_3>]>;
}
+let TargetGuard = "sve2p1" in {
+ def SVGET_2_B : SInst
https://github.com/kmclaughlin-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/74594
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https://github.com/kmclaughlin-arm created
https://github.com/llvm/llvm-project/pull/75075
Adds the following SME2 builtins:
- svunpk (x2 & x4)
See https://github.com/ARM-software/acle/pull/217/files
Patch by David Sherwood
>From 35ea4be3c6fe26a4dd956df6717df1e6f6e4ae6d Mon Sep 17 00:00:00
@@ -263,3 +263,38 @@ multiclass ZAFPOuterProd {
defm SVMOPA : ZAFPOuterProd<"mopa">;
defm SVMOPS : ZAFPOuterProd<"mops">;
+
+
+// SME2 - ADD, SUB
+
+multiclass ZAAddSub {
kmclaughl
@@ -9571,22 +9571,17 @@ Value *CodeGenFunction::EmitSVEStructStore(const
SVETypeFlags &TypeFlags,
Value *BasePtr = Ops[1];
// Does the store have an offset?
- if (Ops.size() > 3)
+ if (Ops.size() > (2 + N))
kmclaughlin-arm wrote:
This change was intend
@@ -10266,35 +10288,13 @@ Value
*CodeGenFunction::EmitAArch64SVEBuiltinExpr(unsigned BuiltinID,
Value *CodeGenFunction::EmitAArch64SMEBuiltinExpr(unsigned BuiltinID,
const CallExpr *E) {
- // Find out if any arguments are req
@@ -9893,24 +9888,40 @@ Value *CodeGenFunction::FormSVEBuiltinResult(Value
*Call) {
return Call;
}
-Value *CodeGenFunction::EmitAArch64SVEBuiltinExpr(unsigned BuiltinID,
- const CallExpr *E) {
+void CodeGenFunction::GetAArch6
@@ -9893,24 +9888,40 @@ Value *CodeGenFunction::FormSVEBuiltinResult(Value
*Call) {
return Call;
}
-Value *CodeGenFunction::EmitAArch64SVEBuiltinExpr(unsigned BuiltinID,
- const CallExpr *E) {
+void CodeGenFunction::GetAArch6
@@ -1363,6 +1364,8 @@ static void __init_cpu_features_constructor(unsigned long
hwcap,
setCPUFeature(FEAT_SME_I64);
if (hwcap2 & HWCAP2_SME_F64F64)
setCPUFeature(FEAT_SME_F64);
+ if (hwcap2 & HWCAP2_SME_FA64)
kmclaughlin-arm wrote:
Does HWCAP2_SME_
https://github.com/kmclaughlin-arm closed
https://github.com/llvm/llvm-project/pull/70662
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kmclaughlin-arm wrote:
This patch was originally committed in #70662, but it was reverted as it was
missing updates to the acle_sve2p1_st1.c & acle_sve2p1_stnt1.c tests.
The first commit in this pull request contains the original patch and the
second contains the updated tests.
https://github
https://github.com/kmclaughlin-arm unassigned
https://github.com/llvm/llvm-project/pull/70959
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https://github.com/kmclaughlin-arm ready_for_review
https://github.com/llvm/llvm-project/pull/70959
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https://github.com/kmclaughlin-arm closed
https://github.com/llvm/llvm-project/pull/70959
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https://github.com/kmclaughlin-arm created
https://github.com/llvm/llvm-project/pull/71176
Adds the following SME2 builtins:
- svmop(a|s)_za32,
- svbmop(a|s)_za32
See https://github.com/ARM-software/acle/pull/217
>From b8560b9a4496db32b730ba5715fcd7febf27b98d Mon Sep 17 00:00:00 2001
From: K
@@ -1341,6 +1341,26 @@ def SVWHILEHS_U32 : SInst<"svwhilege_{d}[_{1}]", "Pmm",
"PUcPUsPUiPUl", MergeNon
def SVWHILEHS_U64 : SInst<"svwhilege_{d}[_{1}]", "Pnn", "PUcPUsPUiPUl",
MergeNone, "aarch64_sve_whilehs", [IsOverloadWhile]>;
}
+let TargetGuard = "sve2p1|sme2" in {
+ d
https://github.com/kmclaughlin-arm closed
https://github.com/llvm/llvm-project/pull/75075
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@@ -1950,19 +1950,17 @@ let TargetGuard = "sve2p1|sme2" in {
//FIXME: Replace IsStreamingCompatible with IsStreamingOrHasSVE2p1 when
available
def SVPEXT_SINGLE : SInst<"svpext_lane_{d}", "P}i", "QcQsQiQl", MergeNone,
"aarch64_sve_pext", [IsStreamingCompatible], [ImmCheck<1, I
@@ -0,0 +1,78 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1
-target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-
@@ -1,12 +1,20 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S
-O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -t
@@ -1,12 +1,20 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S
-O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -t
https://github.com/kmclaughlin-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/75454
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@@ -0,0 +1,760 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S
-disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p
@@ -315,6 +315,219 @@ let TargetGuard = "sme2" in {
def SVBMOPS : Inst<"svbmops_za32[_{d}]_m", "viPPdd", "iUi", MergeNone,
"aarch64_sme_bmops_za32", [IsSharedZA, IsStreaming], [ImmCheck<0,
ImmCheck0_3>]>;
}
+// FMLA/FMLS
+let TargetGuard = "sme2" in {
+ def SVMLA_MULTI_VG
https://github.com/kmclaughlin-arm created
https://github.com/llvm/llvm-project/pull/75821
This patch enables the following builtins for SME2:
- svld1, svld1_vnum
- svldnt1, svldnt1_vnum
- svst1, svst1_vnum
- svstnt1, svstnt1_vnum
>From 1b2022f34ad3b038f714d8d0559f4e129d5e731a Mon Sep 17 00
https://github.com/kmclaughlin-arm closed
https://github.com/llvm/llvm-project/pull/74841
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https://github.com/kmclaughlin-arm closed
https://github.com/llvm/llvm-project/pull/71191
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https://github.com/kmclaughlin-arm created
https://github.com/llvm/llvm-project/pull/75941
Adds the following SME2 builtins:
- svrinta, svrintm, svrintn, svrintp (x2 & x4)
>From 85674fa6c6b568c900b3728555a3e276439818a2 Mon Sep 17 00:00:00 2001
From: Kerry McLaughlin
Date: Tue, 19 Dec 2023 14:
@@ -11,10 +11,16 @@
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu
-target-feature +sve2p1 \
// RUN: -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu
-target-feature
@@ -10,6 +10,10 @@
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu \
// RUN: -target-feature +sve2p1 -S -O1 -Werror -emit-llvm -o - -x c++ %s |
FileCheck %s -check-prefix=CPP-CHECK
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-
@@ -1,14 +1,20 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: aarch64-registered-target
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S
-disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S
-p
@@ -11,10 +11,16 @@
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu
-target-feature +sve2p1 \
// RUN: -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu
-target-feature
@@ -1,14 +1,20 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: aarch64-registered-target
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S
-disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S
-p
https://github.com/kmclaughlin-arm updated
https://github.com/llvm/llvm-project/pull/71176
>From c975abe9015d5c9f5f7c7388101900cbcf738ab6 Mon Sep 17 00:00:00 2001
From: Kerry McLaughlin
Date: Thu, 2 Nov 2023 17:02:32 +
Subject: [PATCH 1/3] [Clang][SME2] Add outer product and accumulate/subt
@@ -298,3 +298,19 @@ multiclass ZAAddSub {
defm SVADD : ZAAddSub<"add">;
defm SVSUB : ZAAddSub<"sub">;
+
+//
+// Outer produce and accumulate/subtract
+//
+
+let TargetGuard = "sme2" in {
+ def SVSMOPA : Inst<"svmopa_za32[_{d}]_m", "viPPdd", "s", MergeNone,
"aarch64_sme_smo
@@ -0,0 +1,170 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2
-target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-ll
https://github.com/kmclaughlin-arm closed
https://github.com/llvm/llvm-project/pull/71176
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@@ -5098,6 +5099,12 @@ void AArch64DAGToDAGISel::Select(SDNode *Node) {
AArch64::LUTI2_4ZTZI_S}))
// Second Immediate must be <= 3:
SelectMultiVectorLuti<3>(Node, 4, Opc);
+ else if (auto Opc = SelectOpcodeFromVT(
kmclaughlin
@@ -5098,6 +5099,12 @@ void AArch64DAGToDAGISel::Select(SDNode *Node) {
AArch64::LUTI2_4ZTZI_S}))
// Second Immediate must be <= 3:
SelectMultiVectorLuti<3>(Node, 4, Opc);
+ else if (auto Opc = SelectOpcodeFromVT(
kmclaughlin
@@ -1666,7 +1674,8 @@ static unsigned SelectOpcodeFromVT(EVT VT,
ArrayRef Opcodes) {
return 0;
break;
case SelectTypeKind::FP:
-if (EltVT != MVT::f16 && EltVT != MVT::f32 && EltVT != MVT::f64)
+if (EltVT != MVT::bf16 && EltVT != MVT::f16 && EltVT != MVT::f3
@@ -2995,6 +2995,134 @@ static QualType getNeonEltType(NeonTypeFlags Flags,
ASTContext &Context,
enum ArmStreamingType { ArmNonStreaming, ArmStreaming, ArmStreamingCompatible
};
+bool Sema::ParseSVEImmChecks(
+CallExpr *TheCall, SmallVector, 3> &ImmChecks) {
+ // Perfo
@@ -2119,6 +2119,21 @@ let TargetGuard = "sme2" in {
// 2-way and 4-way selects
def SVSEL_X2 : SInst<"svsel[_{d}_x2]", "2}22", "cUcsUsiUilUlbhfd",
MergeNone, "aarch64_sve_sel_x2", [IsStreaming], []>;
def SVSEL_X4 : SInst<"svsel[_{d}_x4]", "4}44", "cUcsUsiUilUlbhfd",
M
@@ -2069,21 +2070,20 @@ def SVDOT_LANE_X2_U : SInst<"svdot_lane[_{d}_{2}_{3}]",
"ddhhi", "Ui", MergeNone
def SVDOT_LANE_X2_F : SInst<"svdot_lane[_{d}_{2}_{3}]", "ddhhi", "f",
MergeNone, "aarch64_sve_fdot_lane_x2", [], [ImmCheck<3, ImmCheck0_3>]>;
}
-let TargetGuard = "sve2p
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https://github.com/llvm/llvm-project/pull/75941
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https://github.com/kmclaughlin-arm closed
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https://github.com/kmclaughlin-arm commented:
Thanks for fixing these tests @MDevereau!
There are also some tests in acle_sme2_mlal.c, acle_sme2_mlall.c &
acle_sme2_mlsl.c which have a similar issue, could you please update them in
this patch too?
https://github.com/llvm/llvm-project/pull/7671
https://github.com/kmclaughlin-arm edited
https://github.com/llvm/llvm-project/pull/76711
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@@ -246,7 +246,7 @@ void test_svmls_single2_f64(uint32_t slice_base,
svfloat64x2_t zn, svfloat64_t z
// CPP-CHECK-NEXT:ret void
//
void test_svmls_single4_f64(uint32_t slice_base, svfloat64x4_t zn, svfloat64_t
zm) __arm_streaming __arm_shared_za {
- SVE_ACLE_FUNC(svmls_s
@@ -246,7 +246,7 @@ void test_svmls_single2_f64(uint32_t slice_base,
svfloat64x2_t zn, svfloat64_t z
// CPP-CHECK-NEXT:ret void
//
void test_svmls_single4_f64(uint32_t slice_base, svfloat64x4_t zn, svfloat64_t
zm) __arm_streaming __arm_shared_za {
- SVE_ACLE_FUNC(svmls_s
https://github.com/kmclaughlin-arm created
https://github.com/llvm/llvm-project/pull/77097
PSEL intrinsics which return a predicate-as-counter are available
in SVE2p1 & SME2.
>From 0cea7a1c7d72493de5533815903aec868543d544 Mon Sep 17 00:00:00 2001
From: Kerry McLaughlin
Date: Fri, 5 Jan 2024 11
https://github.com/kmclaughlin-arm updated
https://github.com/llvm/llvm-project/pull/77097
>From 0cea7a1c7d72493de5533815903aec868543d544 Mon Sep 17 00:00:00 2001
From: Kerry McLaughlin
Date: Fri, 5 Jan 2024 11:44:53 +
Subject: [PATCH 1/2] [Clang][SME2] Fix PSEL builtin predicates
PSEL int
@@ -1952,10 +1952,6 @@ def SVPSEL_B : SInst<"svpsel_lane_b8", "PPPm", "Pc",
MergeNone, "", [IsStreamin
def SVPSEL_H : SInst<"svpsel_lane_b16", "PPPm", "Ps", MergeNone, "",
[IsStreamingCompatible], []>;
def SVPSEL_S : SInst<"svpsel_lane_b32", "PPPm", "Pi", MergeNone, "",
[IsS
https://github.com/kmclaughlin-arm edited
https://github.com/llvm/llvm-project/pull/76711
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https://github.com/kmclaughlin-arm commented:
Thanks for updating this @MDevereau, I think there are just a few more tests
that should be included in this PR.
https://github.com/llvm/llvm-project/pull/76711
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@@ -460,7 +460,7 @@ void test_svmla_single4_u16(uint32_t slice_base,
svuint16x4_t zn, svuint16_t zm)
//
void test_svmla_single4_s16(uint32_t slice_base, svint16x4_t zn, svint16_t zm)
__arm_streaming __arm_shared_za
{
- SVE_ACLE_FUNC(svmla_single_za32,,_s16,,_vg2x4)(slice_ba
@@ -494,7 +494,7 @@ void test_svmls_lane1_f16(uint32_t slice_base, svfloat16_t
zn, svfloat16_t zm) _
//
void test_svmls_lane1_bf16(uint32_t slice_base, svbfloat16_t zn, svbfloat16_t
zm) __arm_streaming __arm_shared_za
{
- SVE_ACLE_FUNC(svmls_lane_za32,,_bf16,,_vg2x1)(slice_
@@ -1321,12 +1321,17 @@ def SVSET_3_BF16 : SInst<"svset3[_{d}]", "33id", "b",
MergeNone, "", [IsTupleSet
def SVSET_4_BF16 : SInst<"svset4[_{d}]", "44id", "b", MergeNone, "",
[IsTupleSet], [ImmCheck<1, ImmCheck0_3>]>;
}
-let TargetGuard = "sve2p1" in {
- def SVGET_2_B : SIns
@@ -0,0 +1,35 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 4
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S
-O2 -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim |
FileC
https://github.com/kmclaughlin-arm approved this pull request.
LGTM!
https://github.com/llvm/llvm-project/pull/76711
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https://github.com/kmclaughlin-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/80293
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https://github.com/kmclaughlin-arm approved this pull request.
LGTM!
https://github.com/llvm/llvm-project/pull/77792
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https://github.com/kmclaughlin-arm closed
https://github.com/llvm/llvm-project/pull/77097
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https://github.com/kmclaughlin-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/77338
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https://github.com/kmclaughlin-arm closed
https://github.com/llvm/llvm-project/pull/78430
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@@ -342,331 +342,331 @@ let TargetGuard = "sme2" in {
//
let TargetGuard = "sme2" in {
- def SVSMOPA : Inst<"svmopa_za32[_{d}]_m", "viPPdd", "s", MergeNone,
"aarch64_sme_smopa_za32", [IsSharedZA, IsStreaming], [ImmCheck<0,
ImmCheck0_3>]>;
- def SVUSMOPA : Inst<"svmopa_za3
https://github.com/kmclaughlin-arm updated
https://github.com/llvm/llvm-project/pull/78321
>From 11dce217ed307601d0ea1eb5b016b47f80e67786 Mon Sep 17 00:00:00 2001
From: Kerry McLaughlin
Date: Thu, 11 Jan 2024 17:46:00 +
Subject: [PATCH 1/7] [SME2][Clang] Add tests with ZT0 state
---
llvm/
https://github.com/kmclaughlin-arm closed
https://github.com/llvm/llvm-project/pull/78321
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https://github.com/kmclaughlin-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/78961
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@@ -108,3 +108,11 @@ svint8_t new_za(svint8_t zd, svbool_t pg, uint32_t
slice_base) __arm_streaming {
// expected-no-warning
return svread_hor_za8_s8_m(zd, pg, 0, slice_base);
}
+
+void missing_zt0(void) __arm_streaming {
+ // expected-warning@+1 {{builtin call is not
https://github.com/kmclaughlin-arm commented:
Thank you for reviewing this @david-arm!
https://github.com/llvm/llvm-project/pull/69725
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@@ -9893,24 +9888,37 @@ Value *CodeGenFunction::FormSVEBuiltinResult(Value
*Call) {
return Call;
}
-Value *CodeGenFunction::EmitAArch64SVEBuiltinExpr(unsigned BuiltinID,
- const CallExpr *E) {
+void CodeGenFunction::GetAArch6
@@ -1016,29 +1021,24 @@ std::string Intrinsic::mangleName(ClassKind LocalCK)
const {
getMergeSuffix();
}
-void Intrinsic::emitIntrinsic(raw_ostream &OS, SVEEmitter &Emitter) const {
+void Intrinsic::emitIntrinsic(raw_ostream &OS, ACLEKind Kind) const {
bool IsOver
@@ -10272,29 +10291,13 @@ Value
*CodeGenFunction::EmitAArch64SMEBuiltinExpr(unsigned BuiltinID,
getContext().GetBuiltinType(BuiltinID, Error, &ICEArguments);
kmclaughlin-arm wrote:
I've removed this, it wasn't needed here now that it's checked in
GetAArch64S
@@ -9893,24 +9888,37 @@ Value *CodeGenFunction::FormSVEBuiltinResult(Value
*Call) {
return Call;
}
-Value *CodeGenFunction::EmitAArch64SVEBuiltinExpr(unsigned BuiltinID,
- const CallExpr *E) {
+void CodeGenFunction::GetAArch6
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