[clang] [llvm] [HLSL] Implement elementwise popcount (PR #108121)

@@ -0,0 +1,28 @@ +; RUN: opt -S -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-library %s | FileCheck %s + +; Make sure dxil operation function calls for countbits are generated for all integer types. + +define noundef i16 @test_countbits_short(i16 noundef %a) { +entry: +; CHECK

[clang] [llvm] [HLSL] Implement elementwise popcount (PR #108121)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/108121 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] Implement elementwise popcount (PR #108121)

@@ -0,0 +1,21 @@ +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} + +; CHECK: OpMemoryModel Logical GLSL450 + +define noundef i32 @co

[clang] [llvm] [HLSL] Implement elementwise popcount (PR #108121)

@@ -0,0 +1,28 @@ +; RUN: opt -S -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-library %s | FileCheck %s + +; Make sure dxil operation function calls for countbits are generated for all integer types. + +define noundef i16 @test_countbits_short(i16 noundef %a) { +entry: +; CHECK

[clang] [llvm] [HLSL] Implement elementwise popcount (PR #108121)

@@ -0,0 +1,27 @@ +// RUN: %clang_cc1 -finclude-default-header +// -triple dxil-pc-shadermodel6.6-library %s -fnative-half-type -emit-llvm-only +// -disable-llvm-passes -verify + + +double test_int_builtin(double p0) { + return countbits(p0); + // expected-error@-1 {{call to 'cou

[clang] [llvm] [HLSL] Implement elementwise popcount (PR #108121)

@@ -0,0 +1,27 @@ +// RUN: %clang_cc1 -finclude-default-header +// -triple dxil-pc-shadermodel6.6-library %s -fnative-half-type -emit-llvm-only +// -disable-llvm-passes -verify + + +double test_int_builtin(double p0) { + return countbits(p0); + // expected-error@-1 {{call to 'cou

[clang] [llvm] [HLSL] Implement elementwise popcount (PR #108121)

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[clang] Adding `asuint` implementation to hlsl (PR #107292)

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[clang] Adding `asuint` implementation to hlsl (PR #107292)

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[clang] [llvm] [HLSL] Implementation of the fmod intrinsic (PR #108849)

@@ -90,4 +90,5 @@ def int_dx_rsqrt : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>] def int_dx_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [], [IntrConvergent]>; def int_dx_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>],

[clang] [llvm] [HLSL] Implementation of the fmod intrinsic (PR #108849)

@@ -18709,6 +18709,25 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned BuiltinID, CGM.getHLSLRuntime().getNormalizeIntrinsic(), ArrayRef{X}, nullptr, "hlsl.normalize"); } + case Builtin::BI__builtin_hlsl_elementwise_fmod: { farzonl wr

[clang] [llvm] [HLSL] Implementation of the fmod intrinsic (PR #108849)

@@ -4782,6 +4782,12 @@ def HLSLStep: LangBuiltin<"HLSL_LANG"> { let Prototype = "void(...)"; } +def HLSLFmod : LangBuiltin<"HLSL_LANG"> { + let Spellings = ["__builtin_hlsl_elementwise_fmod"]; farzonl wrote: rename to `__builtin_elementwise_fmod` the add a

[clang] [llvm] [HLSL] Implementation of the fmod intrinsic (PR #108849)

@@ -0,0 +1,38 @@ + +// RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermodel6.6-library %s -fnative-half-type -emit-llvm-only -disable-llvm-passes -verify -verify-ignore-unexpected + +float test_too_few_arg() { + return __builtin_hlsl_elementwise_fmod(); + // ex

[clang] [llvm] [HLSL] Implementation of the fmod intrinsic (PR #108849)

@@ -18709,6 +18709,25 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned BuiltinID, CGM.getHLSLRuntime().getNormalizeIntrinsic(), ArrayRef{X}, nullptr, "hlsl.normalize"); } + case Builtin::BI__builtin_hlsl_elementwise_fmod: { +Value *Op0 = EmitScala

[clang] [llvm] [HLSL] Implementation of the fmod intrinsic (PR #108849)

@@ -90,4 +90,5 @@ def int_dx_rsqrt : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>] def int_dx_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [], [IntrConvergent]>; def int_dx_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>],

[clang] [llvm] [HLSL] Implementation of the fmod intrinsic (PR #108849)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/108849 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] Implementation of the fmod intrinsic (PR #108849)

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[clang] [llvm] [HLSL] Implementation of the fmod intrinsic (PR #108849)

@@ -90,4 +90,5 @@ def int_dx_rsqrt : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>] def int_dx_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [], [IntrConvergent]>; def int_dx_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>],

[clang] [llvm] [HLSL] Implementation of the fmod intrinsic (PR #108849)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/108849 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] Implementation of the fmod intrinsic (PR #108849)

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[clang] Implementing `asfloat` using `bit_cast` (PR #108686)

@@ -0,0 +1,35 @@ +// RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermodel6.6-library %s -fnative-half-type -verify + + +float4 test_float_too_many_arg(float p0, float p1) { + return asfloat(p0, p1); + // expected-error@-1 {{no matching function for call to 'asfl

[clang] Implementing `asfloat` using `bit_cast` (PR #108686)

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[clang] Implementing `asfloat` using `bit_cast` (PR #108686)

https://github.com/farzonl closed https://github.com/llvm/llvm-project/pull/108686 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [HLSL] Align language modes on 202x as default (PR #108662)

https://github.com/farzonl approved this pull request. https://github.com/llvm/llvm-project/pull/108662 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] Implementation of the fmod intrinsic (PR #108849)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/108849 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] Implement `WaveReadLaneAt` intrinsic (PR #111010)

@@ -428,6 +431,7 @@ bool SPIRVInstructionSelector::spvSelect(Register ResVReg, case TargetOpcode::G_INTRINSIC: case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: + case TargetOpcode::G_INTRINSIC_CONVERGENT: farzonl wrote: Is there anything that distinguishes

[clang] [llvm] [HLSL] Implement `WaveReadLaneAt` intrinsic (PR #111010)

https://github.com/farzonl approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/111010 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [SPIR-V] strengthen some lit tests (PR #111636)

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[clang] Switch DirectX Target to use the Itanium ABI (PR #111632)

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[clang] [llvm] [HLSL] Implement the `degrees` intrinsic (PR #111209)

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[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -461,6 +479,27 @@ class OpLowerer { }); } + [[nodiscard]] bool lowerSplitDouble(Function &F) { +IRBuilder<> &IRB = OpBuilder.getIRB(); +return replaceFunction(F, [&](CallInst *CI) -> Error { + IRB.SetInsertPoint(CI); + + Value *Arg0 = CI->getArgOper

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/109331 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -18901,6 +18901,160 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: { CGM.getHLSLRuntime().getRadiansIntrinsic(), ArrayRef{Op0}, nullptr, "hlsl.radians"); } + // This should only be called when targeting DXIL + case Builtin::BI__builtin_hlsl_splitdou

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -461,6 +479,27 @@ class OpLowerer { }); } + [[nodiscard]] bool lowerSplitDouble(Function &F) { +IRBuilder<> &IRB = OpBuilder.getIRB(); +return replaceFunction(F, [&](CallInst *CI) -> Error { + IRB.SetInsertPoint(CI); + + Value *Arg0 = CI->getArgOper

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/109331 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -18901,6 +18901,160 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: { CGM.getHLSLRuntime().getRadiansIntrinsic(), ArrayRef{Op0}, nullptr, "hlsl.radians"); } + // This should only be called when targeting DXIL farzonl wrote: This comm

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -18901,6 +18901,160 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: { CGM.getHLSLRuntime().getRadiansIntrinsic(), ArrayRef{Op0}, nullptr, "hlsl.radians"); } + // This should only be called when targeting DXIL + case Builtin::BI__builtin_hlsl_splitdou

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -18901,6 +18901,160 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: { CGM.getHLSLRuntime().getRadiansIntrinsic(), ArrayRef{Op0}, nullptr, "hlsl.radians"); } + // This should only be called when targeting DXIL + case Builtin::BI__builtin_hlsl_splitdou

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

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[clang] [llvm] [HLSL][DXIL] Implement WaveGetLaneIndex Intrinsic (PR #111576)

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[clang] Enable matrices in HLSL (PR #111415)

@@ -1381,7 +1381,7 @@ void ASTContext::InitBuiltinTypes(const TargetInfo &Target, if (LangOpts.OpenACC && !LangOpts.OpenMP) { InitBuiltinType(ArraySectionTy, BuiltinType::ArraySection); } - if (LangOpts.MatrixTypes) + if (LangOpts.MatrixTypes || LangOpts.HLSL) --

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -264,6 +265,31 @@ class OpLowerer { return lowerToBindAndAnnotateHandle(F); } + Error replaceSplitDoubleCallUsages(CallInst *Intrin, CallInst *Op) { +IRBuilder<> &IRB = OpBuilder.getIRB(); + +for (Use &U : make_early_inc_range(Intrin->uses())) { + if (au

[clang] [clang][HLSL] Add sign intrinsic part 4 (PR #108396)

farzonl wrote: @tgymnich I think its time for you to ask for commit access. Follow these steps: https://llvm.org/docs/DeveloperPolicy.html#obtaining-commit-access https://github.com/llvm/llvm-project/pull/108396 ___ cfe-commits mailing list cfe-commit

[clang] [clang][HLSL] Add sign intrinsic part 4 (PR #108396)

https://github.com/farzonl closed https://github.com/llvm/llvm-project/pull/108396 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][HLSL] Add sign intrinsic part 4 (PR #108396)

farzonl wrote: Build failure was on `Driver/hip-partial-link.hip` Not related to this change. Will proceed with merging. https://github.com/llvm/llvm-project/pull/108396 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cg

[clang] [llvm] [HLSL] Implement `WaveReadLaneAt` intrinsic (PR #111010)

@@ -87,6 +87,7 @@ class CGHLSLRuntime { GENERATE_HLSL_INTRINSIC_FUNCTION(SDot, sdot) GENERATE_HLSL_INTRINSIC_FUNCTION(UDot, udot) GENERATE_HLSL_INTRINSIC_FUNCTION(WaveIsFirstLane, wave_is_first_lane) + GENERATE_HLSL_INTRINSIC_FUNCTION(WaveReadLaneAt, waveReadLaneAt)

[clang] [llvm] [HLSL] implement elementwise firstbithigh hlsl builtin (PR #111082)

@@ -18631,6 +18631,14 @@ static Intrinsic::ID getDotProductIntrinsic(CGHLSLRuntime &RT, QualType QT) { return RT.getUDotIntrinsic(); } +Intrinsic::ID getFirstBitHighIntrinsic(CGHLSLRuntime &RT, QualType QT) { + if (QT->hasSignedIntegerRepresentation()) { +return RT.get

[clang] [llvm] [HLSL] implement elementwise firstbithigh hlsl builtin (PR #111082)

@@ -928,6 +928,78 @@ float3 exp2(float3); _HLSL_BUILTIN_ALIAS(__builtin_elementwise_exp2) float4 exp2(float4); +//===--===// +// firstbithigh builtins +//===

[clang] [llvm] [HLSL] implement elementwise firstbithigh hlsl builtin (PR #111082)

@@ -0,0 +1,91 @@ +; RUN: opt -S -scalarizer -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-library %s | FileCheck %s + +; Make sure dxil operation function calls for firstbithigh are generated for all integer types. + +define noundef i16 @test_firstbithigh_ushort(i16 noundef %a)

[clang] [llvm] [HLSL] implement elementwise firstbithigh hlsl builtin (PR #111082)

@@ -86,4 +86,6 @@ def int_dx_rsqrt : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>] def int_dx_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [], [IntrConvergent]>; def int_dx_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>],

[clang] [llvm] [HLSL] Implement `WaveReadLaneAt` intrinsic (PR #111010)

@@ -18835,6 +18835,22 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: { Intrinsic::ID ID = CGM.getHLSLRuntime().getWaveIsFirstLaneIntrinsic(); return EmitRuntimeCall(Intrinsic::getDeclaration(&CGM.getModule(), ID)); } + case Builtin::BI__builtin_hlsl_wave_read_l

[clang] [llvm] [HLSL] Implement `WaveReadLaneAt` intrinsic (PR #111010)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/111010 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] Implement `WaveReadLaneAt` intrinsic (PR #111010)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/111010 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] Implement `WaveReadLaneAt` intrinsic (PR #111010)

@@ -18835,6 +18835,22 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: { Intrinsic::ID ID = CGM.getHLSLRuntime().getWaveIsFirstLaneIntrinsic(); return EmitRuntimeCall(Intrinsic::getDeclaration(&CGM.getModule(), ID)); } + case Builtin::BI__builtin_hlsl_wave_read_l

[clang] [llvm] [HLSL] Implement `WaveReadLaneAt` intrinsic (PR #111010)

@@ -0,0 +1,40 @@ +// RUN: %clang_cc1 -std=hlsl2021 -finclude-default-header -x hlsl -triple \ +// RUN: dxil-pc-shadermodel6.3-compute %s -emit-llvm -disable-llvm-passes -o - | \ +// RUN: FileCheck %s --check-prefixes=CHECK,CHECK-DXIL +// RUN: %clang_cc1 -std=hlsl2021 -fincl

[clang] [llvm] [HLSL] Implement `WaveReadLaneAt` intrinsic (PR #111010)

@@ -83,6 +83,7 @@ def int_dx_umad : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLV def int_dx_normalize : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty], [IntrNoMem]>; def int_dx_rsqrt : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0

[clang] [llvm] [HLSL] Implement `WaveReadLaneAt` intrinsic (PR #111010)

@@ -2653,6 +2653,22 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, .addUse(GR.getSPIRVTypeID(ResType)) .addUse(GR.getOrCreateConstInt(3, I, IntTy, TII)); } + case Intrinsic::spv_wave_read_lane_at: { +assert(I.getNumOperands() == 4);

[clang] [llvm] [HLSL] Implement `WaveReadLaneAt` intrinsic (PR #111010)

@@ -0,0 +1,56 @@ +; RUN: opt -S -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-compute %s | FileCheck %s + +; Test that for scalar values, WaveReadLaneAt maps down to the DirectX op + +define noundef half @wave_rla_half(half noundef %expr, i32 noundef %idx) #0 { +entry: +; CHECK:

[clang] [llvm] [HLSL] Implement `WaveReadLaneAt` intrinsic (PR #111010)

@@ -0,0 +1,56 @@ +; RUN: opt -S -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-compute %s | FileCheck %s + +; Test that for scalar values, WaveReadLaneAt maps down to the DirectX op + +define noundef half @wave_rla_half(half noundef %expr, i32 noundef %idx) #0 { +entry: +; CHECK:

[clang] [llvm] [HLSL] Implement `WaveReadLaneAt` intrinsic (PR #111010)

@@ -0,0 +1,56 @@ +; RUN: opt -S -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-compute %s | FileCheck %s + +; Test that for scalar values, WaveReadLaneAt maps down to the DirectX op + +define noundef half @wave_rla_half(half noundef %expr, i32 noundef %idx) #0 { +entry: +; CHECK:

[clang] [llvm] [HLSL] Implement `WaveReadLaneAt` intrinsic (PR #111010)

@@ -0,0 +1,56 @@ +; RUN: opt -S -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-compute %s | FileCheck %s + +; Test that for scalar values, WaveReadLaneAt maps down to the DirectX op + +define noundef half @wave_rla_half(half noundef %expr, i32 noundef %idx) #0 { +entry: +; CHECK:

[clang] [llvm] [HLSL] Implement `WaveReadLaneAt` intrinsic (PR #111010)

@@ -0,0 +1,28 @@ +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32v1.3-vulkan-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-vulkan-unknown %s -o - -filetype=obj | spirv-val %} + +; Test lowering to spir-v backend + +; CHECK-DAG: %[[#uint

[clang] [llvm] [HLSL] Implement `WaveReadLaneAt` intrinsic (PR #111010)

@@ -0,0 +1,28 @@ +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32v1.3-vulkan-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-vulkan-unknown %s -o - -filetype=obj | spirv-val %} + +; Test lowering to spir-v backend + +; CHECK-DAG: %[[#uint

[clang] [llvm] [HLSL] implement elementwise firstbithigh hlsl builtin (PR #111082)

@@ -1874,6 +1874,24 @@ bool SemaHLSL::CheckBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) { return true; break; } + case Builtin::BI__builtin_hlsl_elementwise_firstbithigh: { +if (SemaRef.PrepareBuiltinElementwiseMathOneArgCall(TheCall)) + ret

[clang] [llvm] [HLSL] implement elementwise firstbithigh hlsl builtin (PR #111082)

@@ -0,0 +1,153 @@ +// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple \ +// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \ +// RUN: -emit-llvm -disable-llvm-passes -o - | FileCheck %s -DTARGET=dx +// RUN: %clang_cc1 -finclude-default-header -x hlsl -tripl

[clang] [llvm] [HLSL] implement elementwise firstbithigh hlsl builtin (PR #111082)

@@ -0,0 +1,37 @@ +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} farzonl wrote: Do you have spirv-tools installed?

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -489,6 +542,9 @@ class OpLowerer { case Intrinsic::dx_typedBufferStore: HasErrors |= lowerTypedBufferStore(F); break; + case Intrinsic::dx_splitdouble: farzonl wrote: What would require to do it automatically? https://github.com/

[clang] [llvm] [HLSL] Implement `WaveReadLaneAt` intrinsic (PR #111010)

@@ -0,0 +1,28 @@ +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32v1.3-vulkan-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-vulkan-unknown %s -o - -filetype=obj | spirv-val %} + +; Test lowering to spir-v backend + +; CHECK-DAG: %[[#uint

[clang] [llvm] [HLSL] Implement `WaveReadLaneAt` intrinsic (PR #111010)

@@ -82,5 +82,6 @@ let TargetPrefix = "spv" in { [llvm_anyint_ty, LLVMScalarOrSameVectorWidth<0, LLVMVectorElementType<0>>], [IntrNoMem, Commutative] >; def int_spv_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [], [IntrConvergent]>; + def int_spv_wave_rea

[clang] [llvm] [HLSL] Implement `WaveReadLaneAt` intrinsic (PR #111010)

@@ -0,0 +1,28 @@ +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32v1.3-vulkan-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-vulkan-unknown %s -o - -filetype=obj | spirv-val %} + +; Test lowering to spir-v backend + +; CHECK-DAG: %[[#uint

[clang] [llvm] [HLSL] implement elementwise firstbithigh hlsl builtin (PR #111082)

@@ -84,4 +84,6 @@ let TargetPrefix = "spv" in { [IntrNoMem, Commutative] >; def int_spv_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [], [IntrConvergent]>; def int_spv_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>], [llvm_any_ty

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/109331 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] Implement `WaveReadLaneAt` intrinsic (PR #111010)

@@ -83,6 +83,7 @@ def int_dx_umad : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLV def int_dx_normalize : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty], [IntrNoMem]>; def int_dx_rsqrt : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0

[clang] [llvm] [HLSL] implement elementwise firstbithigh hlsl builtin (PR #111082)

@@ -1874,6 +1874,26 @@ bool SemaHLSL::CheckBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) { return true; break; } + case Builtin::BI__builtin_hlsl_elementwise_firstbithigh: { +if (SemaRef.PrepareBuiltinElementwiseMathOneArgCall(TheCall)) + ret

[clang] [llvm] [HLSL] Implement `WaveReadLaneAt` intrinsic (PR #111010)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/111010 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] Implement `WaveReadLaneAt` intrinsic (PR #111010)

@@ -18835,6 +18835,24 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: { Intrinsic::ID ID = CGM.getHLSLRuntime().getWaveIsFirstLaneIntrinsic(); return EmitRuntimeCall(Intrinsic::getDeclaration(&CGM.getModule(), ID)); } + case Builtin::BI__builtin_hlsl_wave_read_l

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -489,6 +542,9 @@ class OpLowerer { case Intrinsic::dx_typedBufferStore: HasErrors |= lowerTypedBufferStore(F); break; + case Intrinsic::dx_splitdouble: farzonl wrote: `replaceFunctionWithNamedStructOp` seems like the right way to

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -18957,6 +18957,134 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: { CGM.getHLSLRuntime().getRadiansIntrinsic(), ArrayRef{Op0}, nullptr, "hlsl.radians"); } + case Builtin::BI__builtin_hlsl_splitdouble: { + +assert((E->getArg(0)->getType()->hasFlo

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -18957,6 +18957,134 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: { CGM.getHLSLRuntime().getRadiansIntrinsic(), ArrayRef{Op0}, nullptr, "hlsl.radians"); } + case Builtin::BI__builtin_hlsl_splitdouble: { + +assert((E->getArg(0)->getType()->hasFlo

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

farzonl wrote: PR looks good. CGBuiltin.cpp were minor fix requests. If we are going to revisit the DXILOpLowering.cpp I'd like to see an issue number to track the work. https://github.com/llvm/llvm-project/pull/109331 ___ cfe-commits mailing list c

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/109331 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] Fix build break in SemaHLSL.cpp on MSVC 2022: warning C4715: 'getResourceClass': not all control paths return a value (PR #112767)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/112767 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -18957,6 +18957,134 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: { CGM.getHLSLRuntime().getRadiansIntrinsic(), ArrayRef{Op0}, nullptr, "hlsl.radians"); } + case Builtin::BI__builtin_hlsl_splitdouble: { + +assert((E->getArg(0)->getType()->hasFlo

[clang] Fix build break in SemaHLSL.cpp on MSVC 2022: warning C4715: 'getResourceClass': not all control paths return a value (PR #112767)

@@ -102,6 +102,7 @@ static ResourceClass getResourceClass(RegisterType RT) { return ResourceClass::Sampler; case RegisterType::C: case RegisterType::I: + default: llvm_unreachable("unexpected RegisterType value"); } farzonl wrote: I'm fine wit

[clang] Fix build break in SemaHLSL.cpp on MSVC 2022: warning C4715: 'getResourceClass': not all control paths return a value (PR #112767)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/112767 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] Fix build break in SemaHLSL.cpp on MSVC 2022: warning C4715: 'getResourceClass': not all control paths return a value (PR #112767)

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[clang] Fix build break in SemaHLSL.cpp on MSVC 2022: warning C4715: 'getResourceClass': not all control paths return a value (PR #112767)

https://github.com/farzonl deleted https://github.com/llvm/llvm-project/pull/112767 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] Fix build break in SemaHLSL.cpp on MSVC 2022: warning C4715: 'getResourceClass': not all control paths return a value (PR #112767)

@@ -102,6 +102,7 @@ static ResourceClass getResourceClass(RegisterType RT) { return ResourceClass::Sampler; case RegisterType::C: case RegisterType::I: + default: llvm_unreachable("unexpected RegisterType value"); } farzonl wrote: I don't agre

[clang] Fix build break in SemaHLSL.cpp on MSVC 2022: warning C4715: 'getResourceClass': not all control paths return a value (PR #112767)

https://github.com/farzonl approved this pull request. https://github.com/llvm/llvm-project/pull/112767 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -18957,6 +18957,134 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: { CGM.getHLSLRuntime().getRadiansIntrinsic(), ArrayRef{Op0}, nullptr, "hlsl.radians"); } + case Builtin::BI__builtin_hlsl_splitdouble: { + +assert((E->getArg(0)->getType()->hasFlo

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/109331 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/109331 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -18957,6 +18957,134 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: { CGM.getHLSLRuntime().getRadiansIntrinsic(), ArrayRef{Op0}, nullptr, "hlsl.radians"); } + case Builtin::BI__builtin_hlsl_splitdouble: { + +assert((E->getArg(0)->getType()->hasFlo

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -0,0 +1,15 @@ +; RUN: opt -S -scalarizer -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-library %s 2>&1 | FileCheck %s + +; DXIL operation splitdouble doesn't support vector types. +; XFAIL: * + +define noundef <3 x i32> @test_vector_double_split(<3 x double> noundef %D) loc

[clang] [clang][HLSL] Add radians intrinsic (PR #110802)

@@ -18852,6 +18852,14 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: { retType, CGM.getHLSLRuntime().getSignIntrinsic(), ArrayRef{Op0}, nullptr, "hlsl.sign"); } + case Builtin::BI__builtin_hlsl_elementwise_radians: { +Value *Op0 = EmitScalarExpr(E->

[clang] [clang][HLSL] Add radians intrinsic (PR #110802)

@@ -0,0 +1,27 @@ +// RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermodel6.6-library %s -fnative-half-type -emit-llvm-only -disable-llvm-passes -verify -verify-ignore-unexpected + +float test_too_few_arg() { + return __builtin_hlsl_elementwise_radians(); + // e

[clang] [clang][HLSL] Add radians intrinsic (PR #110802)

https://github.com/farzonl approved this pull request. https://github.com/llvm/llvm-project/pull/110802 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][HLSL] Add radians intrinsic (PR #110802)

https://github.com/farzonl requested changes to this pull request. Please run clang-format https://github.com/llvm/llvm-project/pull/110802 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-comm

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -461,6 +487,33 @@ class OpLowerer { }); } + [[nodiscard]] bool lowerSplitDouble(Function &F) { +IRBuilder<> &IRB = OpBuilder.getIRB(); +return replaceFunction(F, [&](CallInst *CI) -> Error { + IRB.SetInsertPoint(CI); + + Value *Arg0 = CI->getArgOper

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -0,0 +1,14 @@ +; RUN: opt -S -scalarizer -mtriple=spirv-vulkan-library %s 2>&1 | llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown -o - | FileCheck %s + +; SPIRV lowering for splitdouble should relly on the scalarizer. farzonl wrote: This comment d

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