@@ -19,4 +19,9 @@ def int_dx_flattened_thread_id_in_group :
Intrinsic<[llvm_i32_ty], [], [IntrNoMe
def int_dx_create_handle : ClangBuiltin<"__builtin_hlsl_create_handle">,
Intrinsic<[ llvm_ptr_ty ], [llvm_i8_ty], [IntrWillReturn]>;
-}
+
+def int_dx_dot :
+Intrinsic<[
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>From 5082bc7fb49761424c7984a594a5afad9a03f04d Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Thu, 8 Feb 2024 11:08:59 -0500
Subject: [PATCH] [HLSL] Implementation of dot intrinsic This change implements
#700
@@ -4518,6 +4518,12 @@ def HLSLCreateHandle : LangBuiltin<"HLSL_LANG"> {
let Prototype = "void*(unsigned char)";
}
+def HLSLDotProduct : LangBuiltin<"HLSL_LANG"> {
+ let Spellings = ["__builtin_hlsl_dot"];
+ let Attributes = [NoThrow, Const, CustomTypeChecking];
--
@@ -144,6 +144,92 @@ double3 cos(double3);
_HLSL_BUILTIN_ALIAS(__builtin_elementwise_cos)
double4 cos(double4);
+//===--===//
+// dot product builtins
+//===
@@ -19,4 +19,9 @@ def int_dx_flattened_thread_id_in_group :
Intrinsic<[llvm_i32_ty], [], [IntrNoMe
def int_dx_create_handle : ClangBuiltin<"__builtin_hlsl_create_handle">,
Intrinsic<[ llvm_ptr_ty ], [llvm_i8_ty], [IntrWillReturn]>;
-}
+
+def int_dx_dot :
+Intrinsic<[
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@@ -19,4 +19,9 @@ def int_dx_flattened_thread_id_in_group :
Intrinsic<[llvm_i32_ty], [], [IntrNoMe
def int_dx_create_handle : ClangBuiltin<"__builtin_hlsl_create_handle">,
Intrinsic<[ llvm_ptr_ty ], [llvm_i8_ty], [IntrWillReturn]>;
-}
+
+def int_dx_dot :
+Intrinsic<[
@@ -144,6 +144,92 @@ double3 cos(double3);
_HLSL_BUILTIN_ALIAS(__builtin_elementwise_cos)
double4 cos(double4);
+//===--===//
+// dot product builtins
+//===
https://github.com/farzonl updated
https://github.com/llvm/llvm-project/pull/81190
>From 4103940b5a2578efc08df554ccdf80cb34925d09 Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Thu, 8 Feb 2024 11:08:59 -0500
Subject: [PATCH] [HLSL] Implementation of dot intrinsic This change implements
#700
https://github.com/farzonl updated
https://github.com/llvm/llvm-project/pull/81190
>From 73cc9fde36a44ba1715a3c9fc6d48196602d5dc4 Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Thu, 8 Feb 2024 11:08:59 -0500
Subject: [PATCH] [HLSL] Implementation of dot intrinsic This change implements
#700
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@@ -0,0 +1,43 @@
+// RUN: %clang_cc1 -std=hlsl2021 -finclude-default-header -x hlsl -triple \
+// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \
+// RUN: -emit-llvm -disable-llvm-passes -verify -verify-ignore-unexpected
+
+float test_first_arg_is_not_vector ( floa
@@ -0,0 +1,202 @@
+// RUN: %clang_cc1 -std=hlsl2021 -finclude-default-header -x hlsl -triple \
+// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \
+// RUN: -emit-llvm -disable-llvm-passes -O3 -o - | FileCheck %s
+// RUN: %clang_cc1 -std=hlsl2021 -finclude-default-h
farzonl wrote:
It might be worth adding a .dox file something like this:
```
/*!
\mainpage HLSL Overview
\tableofcontents
\section hlsl-introduction Introduction to HLSL
- \ref hlsl_basic_types.h defines hlsl types
-\ref - hlsl_intrinsics
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>From 0060612b4fc1b7f5f5cc51a41a5fae7535ba2b02 Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Sun, 3 Mar 2024 16:14:35 -0500
Subject: [PATCH 1/2] [HLSL] implement the rcp intrinsic This PR implements
the fro
@@ -18057,6 +18057,14 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned
BuiltinID,
/*ReturnType*/ Op0->getType(), Intrinsic::dx_frac,
ArrayRef{Op0}, nullptr, "dx.frac");
}
+ case Builtin::BI__builtin_hlsl_elementwise_rcp: {
+Value *Op0 = EmitScalar
https://github.com/farzonl updated
https://github.com/llvm/llvm-project/pull/83857
>From 710cef1e42c50c935a2fdd535b48002db3796497 Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Sun, 3 Mar 2024 16:14:35 -0500
Subject: [PATCH 1/2] [HLSL] implement the rcp intrinsic This PR implements
the fro
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https://github.com/llvm/llvm-project/pull/83903
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>From 786d0b41971dcd39fd76ae24ef16c8d086abb092 Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Tue, 5 Mar 2024 12:52:39 -0500
Subject: [PATCH] fix merge conflict, address pr concerns
---
clang/include/clang/B
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@@ -114,6 +114,44 @@ not re-targetable, we want to share the Clang CodeGen
implementation for HLSL
with other GPU graphics targets like SPIR-V and possibly other GPU and even CPU
targets.
+hlsl.h
+--
+
+HLSL has an extensive library of functionality. This is similar to Op
farzonl wrote:
Should we talk at all about why we use __attribute__ clang_builtin_alias
similar to what risc-v vectors does in their docs?
https://github.com/llvm/llvm-project/blob/55c466da2f2f0baa509eb709b8de8926bd498b9b/clang/include/clang/Basic/AttrDocs.td#L5425
https://github.com/llvm/llvm
https://github.com/farzonl created
https://github.com/llvm/llvm-project/pull/84526
This change implements lowering for #70076, #70100, #70072, & #70102
`CGBuiltin.cpp` - - simplify `lerp` intrinsic
`IntrinsicsDirectX.td` - simplify `lerp` intrinsic
`SemaChecking.cpp` - remove unnecessary check
https://github.com/farzonl updated
https://github.com/llvm/llvm-project/pull/84526
>From ad83fd46be2e1587a6cb0098467e18dc38612517 Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Thu, 7 Mar 2024 20:48:46 -0500
Subject: [PATCH 1/2] [DXIL] exp, any, lerp, & rcp Intrinsic Lowering This
change im
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https://github.com/farzonl created
https://github.com/llvm/llvm-project/pull/84820
This change implements #70074
- `hlsl_intrinsics.h` - add the `rsqrt` api
- `DXIL.td` add the llvm intrinsic to DXIL op lowering map.
- `Builtins.td` - add an hlsl builtin for rsqrt.
- `CGBuiltin.cpp` add the ir g
https://github.com/farzonl updated
https://github.com/llvm/llvm-project/pull/84820
>From a46ecdee6356e744a80f3c29748e7c3482a89760 Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Mon, 11 Mar 2024 15:17:35 -0400
Subject: [PATCH] [HLSL] Implement `rsqrt` intrinsic This change implements
#70074
@@ -0,0 +1,49 @@
+; ModuleID =
'D:\projects\llvm-project\clang\test\SemaHLSL\BuiltIns\dot-warning.hlsl'
farzonl wrote:
this file shouldn't be in this pr. this was a mistake.
https://github.com/llvm/llvm-project/pull/84820
___
@@ -0,0 +1,27 @@
+
+// RUN: %clang_cc1 -finclude-default-header -triple
dxil-pc-shadermodel6.6-library %s -fnative-half-type -emit-llvm
-disable-llvm-passes -verify -verify-ignore-unexpected
+
+float test_too_few_arg() {
+ return __builtin_hlsl_elementwise_rsqrt();
+ // expect
https://github.com/farzonl updated
https://github.com/llvm/llvm-project/pull/84820
>From a46ecdee6356e744a80f3c29748e7c3482a89760 Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Mon, 11 Mar 2024 15:17:35 -0400
Subject: [PATCH 1/2] [HLSL] Implement `rsqrt` intrinsic This change implements
#70
https://github.com/farzonl updated
https://github.com/llvm/llvm-project/pull/84820
>From a46ecdee6356e744a80f3c29748e7c3482a89760 Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Mon, 11 Mar 2024 15:17:35 -0400
Subject: [PATCH 1/2] [HLSL] Implement `rsqrt` intrinsic This change implements
#70
https://github.com/farzonl created
https://github.com/llvm/llvm-project/pull/84927
This change implements part 1 of 2 for #70095
- `hlsl_intrinsics.h` - add the `isinf` api
- `Builtins.td` - add an hlsl builtin for `isinf`.
- `CGBuiltin.cpp` add the ir generation for `isinf` intrinsic.
- `SemaCh
https://github.com/farzonl updated
https://github.com/llvm/llvm-project/pull/84526
>From 7dde8faaad046b715027a0f9fb772af90b6ffb30 Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Thu, 7 Mar 2024 20:48:46 -0500
Subject: [PATCH 1/3] [DXIL] exp, any, lerp, & rcp Intrinsic Lowering This
change im
https://github.com/farzonl updated
https://github.com/llvm/llvm-project/pull/84526
>From 7dde8faaad046b715027a0f9fb772af90b6ffb30 Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Thu, 7 Mar 2024 20:48:46 -0500
Subject: [PATCH 1/3] [DXIL] exp, any, lerp, & rcp Intrinsic Lowering This
change im
@@ -0,0 +1,187 @@
+//===- DXILIntrinsicExpansion.cpp - Prepare LLVM Module for DXIL
encoding--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
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@@ -0,0 +1,187 @@
+//===- DXILIntrinsicExpansion.cpp - Prepare LLVM Module for DXIL
encoding--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
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@@ -5254,7 +5250,11 @@ bool CheckAllArgsHaveFloatRepresentation(Sema *S,
CallExpr *TheCall) {
QualType ExpectedType = S->Context.FloatTy;
for (unsigned i = 0; i < TheCall->getNumArgs(); ++i) {
QualType PassedType = TheCall->getArg(i)->getType();
-if (!PassedType->h
https://github.com/farzonl updated
https://github.com/llvm/llvm-project/pull/81190
>From fad7e6eac6a1a65ce00ab3e4f64d5774b426c91d Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Thu, 8 Feb 2024 11:08:59 -0500
Subject: [PATCH 1/4] [HLSL] Implementation of dot intrinsic This change
implements
https://github.com/farzonl created
https://github.com/llvm/llvm-project/pull/82827
There are two issues here. first `ICK_Floating_Integral` were always defaulting
to `CK_FloatingToIntegral` for vectors regardless of direction of cast. Check
was scalar only so added a vec float check to the co
https://github.com/farzonl updated
https://github.com/llvm/llvm-project/pull/82827
>From 15eee3edd9ad834dc46fb5a1053874093b41a65a Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Fri, 23 Feb 2024 15:28:13 -0500
Subject: [PATCH] [HLSL] Fix casting asserts There are two issues here. first
ICK_F
@@ -4843,7 +4843,7 @@ Sema::PerformImplicitConversion(Expr *From, QualType
ToType,
.get();
break;
case ICK_Floating_Integral:
- if (ToType->isRealFloatingType())
+ if (ToType->isRealFloatingType() || ToType->hasFloatingRepresentation())
---
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>From 0ff2c7162d2676190b5ad370b7e7171581d8d21b Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Fri, 23 Feb 2024 15:28:13 -0500
Subject: [PATCH] [HLSL] Fix casting asserts There are two issues here. first
ICK_F
https://github.com/farzonl updated
https://github.com/llvm/llvm-project/pull/81190
>From fad7e6eac6a1a65ce00ab3e4f64d5774b426c91d Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Thu, 8 Feb 2024 11:08:59 -0500
Subject: [PATCH 1/4] [HLSL] Implementation of dot intrinsic This change
implements
@@ -5161,6 +5166,157 @@ bool Sema::CheckPPCMMAType(QualType Type,
SourceLocation TypeLoc) {
return false;
}
+// Helper function for CheckHLSLBuiltinFunctionCall
+// Note: UsualArithmeticConversions handles the case where at least
+// one arg isn't a bool
+bool PromoteBoolsT
@@ -1,4 +1,5 @@
// RUN: %clang_cc1 -triple dxil-unknown-shadermodel6.6-library -S
-fnative-half-type -finclude-default-header -o - -ast-dump %s | FileCheck %s
+// RUN: %clang_cc1 -std=hlsl2021 -finclude-default-header -x hlsl -triple
dxil-pc-shadermodel6.6-library %s -fnative-h
https://github.com/farzonl updated
https://github.com/llvm/llvm-project/pull/81190
>From f6188a3308188aa3037b05f685a6065bfc2d69fa Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Thu, 8 Feb 2024 11:08:59 -0500
Subject: [PATCH 1/5] [HLSL] Implementation of dot intrinsic This change
implements
https://github.com/farzonl updated
https://github.com/llvm/llvm-project/pull/81190
>From f6188a3308188aa3037b05f685a6065bfc2d69fa Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Thu, 8 Feb 2024 11:08:59 -0500
Subject: [PATCH 1/6] [HLSL] Implementation of dot intrinsic This change
implements
https://github.com/farzonl updated
https://github.com/llvm/llvm-project/pull/82827
>From 15eee3edd9ad834dc46fb5a1053874093b41a65a Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Fri, 23 Feb 2024 15:28:13 -0500
Subject: [PATCH 1/2] [HLSL] Fix casting asserts There are two issues here.
first I
https://github.com/farzonl updated
https://github.com/llvm/llvm-project/pull/81190
>From f6188a3308188aa3037b05f685a6065bfc2d69fa Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Thu, 8 Feb 2024 11:08:59 -0500
Subject: [PATCH 1/6] [HLSL] Implementation of dot intrinsic This change
implements
https://github.com/farzonl updated
https://github.com/llvm/llvm-project/pull/82827
>From 15eee3edd9ad834dc46fb5a1053874093b41a65a Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Fri, 23 Feb 2024 15:28:13 -0500
Subject: [PATCH 1/2] [HLSL] Fix casting asserts There are two issues here.
first I
https://github.com/farzonl created
https://github.com/llvm/llvm-project/pull/83077
This is the start of implementing the lerp intrinsic
https://learn.microsoft.com/en-us/windows/win32/direct3dhlsl/dx-graphics-hlsl-lerp
Builtins.td - defines the builtin
hlsl_intrinsics.h - defines the lerp api
@@ -24,4 +24,9 @@ def int_dx_dot :
Intrinsic<[LLVMVectorElementType<0>],
[llvm_anyvector_ty, LLVMScalarOrSameVectorWidth<0,
LLVMVectorElementType<0>>],
[IntrNoMem, IntrWillReturn, Commutative] >;
+
+def int_dx_lerp :
+Intrinsic<[LLVMMatchType<0>],
+[llvm_
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>From d4384c5ac52596eeab512574111e499f230b7db7 Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Sun, 25 Feb 2024 20:08:09 -0500
Subject: [PATCH] [HLSL] Implementation lerp intrinsic This is the start of
implem
https://github.com/farzonl created
https://github.com/llvm/llvm-project/pull/83315
This change implements the frontend for #70099
Builtins.td - add the frac builtin
CGBuiltin.cpp - add the builtin to DirectX intrinsic mapping
hlsl_intrinsics.h - add the frac api
SemaChecki
https://github.com/farzonl ready_for_review
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@@ -0,0 +1,27 @@
+
+// RUN: %clang_cc1 -finclude-default-header -triple
dxil-pc-shadermodel6.6-library %s -fnative-half-type -emit-llvm
-disable-llvm-passes -verify -verify-ignore-unexpected
+
farzonl wrote:
error: 1st argument must be a vector, integer or floa
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@@ -10266,6 +10266,11 @@ def err_block_on_vm : Error<
def err_sizeless_nonlocal : Error<
"non-local variable with sizeless type %0">;
+def err_vec_builtin_non_vector_all : Error<
+ "all arguments to %0 must be vectors">;
+def err_vec_builtin_incompatible_vector_all : Error<
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https://github.com/farzonl created
https://github.com/llvm/llvm-project/pull/83340
This PR brings best practices mentioned to me on other prs and adds them to the
existing builtin tests.
Note to reviewers: I put this up in two commits because the clang-format
changes is making it hard to tell
farzonl wrote:
> Do we have the suggestions that this is responding to written down somewhere?
> I think it would be useful to have those guidelines for anyone who might want
> to contribute HLSL tests. At any rate, I'd like to know the ones that this is
> in response to.
@pow2clk
below are t
farzonl wrote:
> > Do we have the suggestions that this is responding to written down
> > somewhere? I think it would be useful to have those guidelines for anyone
> > who might want to contribute HLSL tests. At any rate, I'd like to know the
> > ones that this is in response to.
>
> Followin
https://github.com/farzonl updated
https://github.com/llvm/llvm-project/pull/83315
>From cd8a27e4571b8e791ce5ccaaf51dd570ee8bc6d3 Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Wed, 28 Feb 2024 13:20:01 -0500
Subject: [PATCH 1/2] [HLSL] Implementation of the frac intrinsic This change
imple
farzonl wrote:
> Do we have the suggestions that this is responding to written down somewhere?
> I think it would be useful to have those guidelines for anyone who might want
> to contribute HLSL tests. At any rate, I'd like to know the ones that this is
> in response to.
After consulting wit
https://github.com/farzonl updated
https://github.com/llvm/llvm-project/pull/83077
>From 56240f07c39deb4c48bf7370dc72b3c67299eee1 Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Sun, 25 Feb 2024 20:08:09 -0500
Subject: [PATCH] start of lerp intrinsic
---
clang/include/clang/Basic/Builtins.t
https://github.com/farzonl updated
https://github.com/llvm/llvm-project/pull/83315
>From 2ec582be1c361c212ea846c8433a9cebfeb7b4ba Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Thu, 29 Feb 2024 10:23:31 -0500
Subject: [PATCH 1/3] address merge conflicts
---
clang/include/clang/Basic/Builti
farzonl wrote:
@python3kgae I wanted to hold off on merging this one because I was
investigating why
[56240f0](https://github.com/llvm/llvm-project/commit/56240f07c39deb4c48bf7370dc72b3c67299eee1)
wiped out my changes on
[d4384c5](https://github.com/llvm/llvm-project/commit/d4384c5ac52596e
https://github.com/farzonl updated
https://github.com/llvm/llvm-project/pull/83315
>From 2ec582be1c361c212ea846c8433a9cebfeb7b4ba Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Thu, 29 Feb 2024 10:23:31 -0500
Subject: [PATCH 1/4] address merge conflicts
---
clang/include/clang/Basic/Builti
https://github.com/farzonl updated
https://github.com/llvm/llvm-project/pull/83315
>From 2ec582be1c361c212ea846c8433a9cebfeb7b4ba Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Thu, 29 Feb 2024 10:23:31 -0500
Subject: [PATCH 1/5] address merge conflicts
---
clang/include/clang/Basic/Builti
https://github.com/farzonl updated
https://github.com/llvm/llvm-project/pull/83315
>From 2ec582be1c361c212ea846c8433a9cebfeb7b4ba Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Thu, 29 Feb 2024 10:23:31 -0500
Subject: [PATCH 1/6] address merge conflicts
---
clang/include/clang/Basic/Builti
https://github.com/farzonl created
https://github.com/llvm/llvm-project/pull/83520
- Builtins.td - add the round builtin
- CGBuiltin.cpp - add the builtin to DirectX intrinsic mapping
hlsl_intrinsics.h - add the round api
- SemaChecking.cpp - add type checks for builtin
- IntrinsicsDirectX.td
https://github.com/farzonl closed
https://github.com/llvm/llvm-project/pull/83520
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https://github.com/farzonl created
https://github.com/llvm/llvm-project/pull/83570
hlsl_intrinsics.h - add the round api
DXIL.td add the llvm intrinsic to DXIL lowering mapping
This chane reuses llvms existing `__builtin_elementwise_round`\`int_round`
This change implements: #70077
>From 2432
https://github.com/farzonl edited
https://github.com/llvm/llvm-project/pull/83570
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https://github.com/farzonl updated
https://github.com/llvm/llvm-project/pull/83570
>From f9e5cf8043dffc0c9fc94a8768b25111664311dd Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Thu, 29 Feb 2024 21:48:47 -0500
Subject: [PATCH] [HLSL][DXIL] Implementation of round intrinsic
hlsl_intrinsics.h
https://github.com/farzonl updated
https://github.com/llvm/llvm-project/pull/83570
>From ca14584d500752215b922e18743a503ea7f323bc Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Thu, 29 Feb 2024 21:48:47 -0500
Subject: [PATCH] [HLSL][DXIL] Implementation of round intrinsic
hlsl_intrinsics.h
@@ -831,6 +831,40 @@ uint64_t3 reversebits(uint64_t3);
_HLSL_BUILTIN_ALIAS(__builtin_elementwise_bitreverse)
uint64_t4 reversebits(uint64_t4);
+//===--===//
+// frac builtins
+//===
https://github.com/farzonl edited
https://github.com/llvm/llvm-project/pull/83570
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https://github.com/farzonl closed
https://github.com/llvm/llvm-project/pull/83570
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https://github.com/farzonl created
https://github.com/llvm/llvm-project/pull/83609
removing the additions of `err_vec_builtin_non_vector_all` &
`err_vec_builtin_incompatible_vector_all`
caused by https://github.com/llvm/llvm-project/pull/83077.
Instead adding a select option to `err_vec_builti
@@ -10266,6 +10266,11 @@ def err_block_on_vm : Error<
def err_sizeless_nonlocal : Error<
"non-local variable with sizeless type %0">;
+def err_vec_builtin_non_vector_all : Error<
+ "all arguments to %0 must be vectors">;
+def err_vec_builtin_incompatible_vector_all : Error<
@@ -38,70 +38,70 @@ float test_dot_element_type_mismatch(int2 p0, float2 p1) {
//NOTE: for all the *_promotion we are intentionally not handling type
promotion in builtins
float test_builtin_dot_vec_int_to_float_promotion(int2 p0, float2 p1) {
return __builtin_hlsl_dot(p0, p
https://github.com/farzonl updated
https://github.com/llvm/llvm-project/pull/83609
>From bfd8afd06400bc936c13d2138576bb0bb51960e9 Mon Sep 17 00:00:00 2001
From: Farzon Lotfi
Date: Fri, 1 Mar 2024 14:21:17 -0500
Subject: [PATCH] [clang][sema] consolidate diags
---
.../clang/Basic/DiagnosticSem
@@ -22,7 +22,7 @@ float test_dot_vector_size_mismatch(float3 p0, float2 p1) {
float test_dot_builtin_vector_size_mismatch(float3 p0, float2 p1) {
return __builtin_hlsl_dot(p0, p1);
- // expected-error@-1 {{all arguments to '__builtin_hlsl_dot' must have
vectors of the same
@@ -5218,15 +5218,15 @@ bool CheckVectorElementCallArgs(Sema *S, CallExpr
*TheCall) {
// Note: type promotion is intended to be handeled via the intrinsics
// and not the builtin itself.
S->Diag(TheCall->getBeginLoc(),
-diag::err_vec_bu
@@ -5241,8 +5241,8 @@ bool CheckVectorElementCallArgs(Sema *S, CallExpr
*TheCall) {
// Note: if we get here one of the args is a scalar which
// requires a VectorSplat on Arg0 or Arg1
- S->Diag(BuiltinLoc, diag::err_vec_builtin_non_vector_all)
- << TheCall->getDirec
farzonl wrote:
@pow2clk force doesn't seem necessary b\c squash merge is the default behavior
for this project. I did it because i tend to rebase my branches when I put out
revisions. I'll stop doing that.
https://github.com/llvm/llvm-project/pull/83609
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https://github.com/farzonl edited
https://github.com/llvm/llvm-project/pull/83609
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