[clang] [Clang][SME2] Add multi-vector add/sub builtins (PR #69725)

@@ -0,0 +1,1226 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py + +// REQUIRES: aarch64-registered-target + +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -target-f

[clang] [Clang][SME2] Add multi-vector add/sub builtins (PR #69725)

https://github.com/david-arm approved this pull request. LGTM! Eccelente! Thanks for the changes @kmclaughlin-arm. https://github.com/llvm/llvm-project/pull/69725 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/ma

[clang] bafdd11 - [SVE] Replace / operator in TypeSize/ElementCount with divideCoefficientBy

Author: David Sherwood Date: 2020-09-28T08:03:00+01:00 New Revision: bafdd11326a46421b68f68c794fd189c77a32e15 URL: https://github.com/llvm/llvm-project/commit/bafdd11326a46421b68f68c794fd189c77a32e15 DIFF: https://github.com/llvm/llvm-project/commit/bafdd11326a46421b68f68c794fd189c77a32e15.diff

[clang] f4257c5 - [SVE] Make ElementCount members private

Author: David Sherwood Date: 2020-08-28T14:43:53+01:00 New Revision: f4257c5832aa51e960e7351929ca3d37031985b7 URL: https://github.com/llvm/llvm-project/commit/f4257c5832aa51e960e7351929ca3d37031985b7 DIFF: https://github.com/llvm/llvm-project/commit/f4257c5832aa51e960e7351929ca3d37031985b7.diff

[clang] cea69fa - [SVE] Add fatal error for unnamed SVE variadic arguments

Author: David Sherwood Date: 2020-10-30T13:35:47Z New Revision: cea69fa4dcc4fcf3be62dba49ad012879d89377d URL: https://github.com/llvm/llvm-project/commit/cea69fa4dcc4fcf3be62dba49ad012879d89377d DIFF: https://github.com/llvm/llvm-project/commit/cea69fa4dcc4fcf3be62dba49ad012879d89377d.diff LOG

[clang] f988f68 - [Analysis] Add support for vscale in computeKnownBitsFromOperator

Author: David Sherwood Date: 2021-09-20T15:01:59+01:00 New Revision: f988f680649ad38806897e7aa75e95e9fda88ffd URL: https://github.com/llvm/llvm-project/commit/f988f680649ad38806897e7aa75e95e9fda88ffd DIFF: https://github.com/llvm/llvm-project/commit/f988f680649ad38806897e7aa75e95e9fda88ffd.diff

[clang] 2a48b69 - [IR] In ConstantFoldShuffleVectorInstruction use zeroinitializer for splats of 0

Author: David Sherwood Date: 2021-11-10T09:42:58Z New Revision: 2a48b6993a973e0ab2331e8c11dbd6e6100e2cfe URL: https://github.com/llvm/llvm-project/commit/2a48b6993a973e0ab2331e8c11dbd6e6100e2cfe DIFF: https://github.com/llvm/llvm-project/commit/2a48b6993a973e0ab2331e8c11dbd6e6100e2cfe.diff LOG

[clang] fbb1194 - [AArch64] Add Neoverse V2 CPU support

Author: David Sherwood Date: 2022-09-27T07:56:08Z New Revision: fbb119412f143530a23d22b6b0f90d4cf2303fbf URL: https://github.com/llvm/llvm-project/commit/fbb119412f143530a23d22b6b0f90d4cf2303fbf DIFF: https://github.com/llvm/llvm-project/commit/fbb119412f143530a23d22b6b0f90d4cf2303fbf.diff LOG

[clang] 4cf11d8 - [Clang][SVE] Permit specific predicate-as-counter registers in inline assembly

Author: David Sherwood Date: 2023-07-25T08:55:45Z New Revision: 4cf11d8a65dfded59761ec52804a86277b9c0036 URL: https://github.com/llvm/llvm-project/commit/4cf11d8a65dfded59761ec52804a86277b9c0036 DIFF: https://github.com/llvm/llvm-project/commit/4cf11d8a65dfded59761ec52804a86277b9c0036.diff LOG

[clang] [SVE][InstCombine] Delete redundante sel instructions with ptrue (PR #68463)

@@ -800,6 +800,13 @@ instCombineConvertFromSVBool(InstCombiner &IC, IntrinsicInst &II) { static std::optional instCombineSVESel(InstCombiner &IC, IntrinsicInst &II) { + // svsel(ptrue, x, y) => x + auto *OpPredicate = II

[clang] [SVE][InstCombine] Delete redundante sel instructions with ptrue (PR #68463)

@@ -63,6 +63,20 @@ svint32_t test_svsel_s32(svbool_t pg, svint32_t op1, svint32_t op2) return SVE_ACLE_FUNC(svsel,_s32,,)(pg, op1, op2); } +// CHECK-LABEL: @test_svsel_s32_ptrue( david-arm wrote: I'm not sure if this test really adds any more value, since

[clang] bfb6f47 - [SVE] Change some bfloat lane intrinsics to use i32 immediates

Author: David Sherwood Date: 2022-12-07T09:19:54Z New Revision: bfb6f47e9ea463555833934ef714b03ee78eb01e URL: https://github.com/llvm/llvm-project/commit/bfb6f47e9ea463555833934ef714b03ee78eb01e DIFF: https://github.com/llvm/llvm-project/commit/bfb6f47e9ea463555833934ef714b03ee78eb01e.diff LOG

[clang] [clang] Add nuw attribute to GEPs (PR #105496)

david-arm wrote: > This patch breaks: https://lab.llvm.org/buildbot/#/builders/25/builds/1952 > https://lab.llvm.org/buildbot/#/builders/52/builds/1775 >From the buildbot run I can see 12 or 13 changes in the build that failed. >Just out of curiosity how did you find out it was this patch that

[clang] [clang] Add nuw attribute to GEPs (PR #105496)

david-arm wrote: > > > This patch breaks: > > > https://lab.llvm.org/buildbot/#/builders/25/builds/1952 > > > https://lab.llvm.org/buildbot/#/builders/52/builds/1775 > > > > > > From the buildbot run I can see 12 or 13 changes in the build that failed. > > Just out of curiosity how did you f

[clang] [Clang][AArch64] Add missing SME/SVE2.1 feature macros (PR #98285)

david-arm wrote: Is it worth adding a link to the ACLE that describes the features in the commit message? https://github.com/llvm/llvm-project/pull/98285 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/li

[clang] 38d18d9 - [SVE] Add support to vectorize_width loop pragma for scalable vectors

Author: David Sherwood Date: 2021-01-08T11:37:27Z New Revision: 38d18d93534d290d045bbbfa86337e70f1139dc2 URL: https://github.com/llvm/llvm-project/commit/38d18d93534d290d045bbbfa86337e70f1139dc2 DIFF: https://github.com/llvm/llvm-project/commit/38d18d93534d290d045bbbfa86337e70f1139dc2.diff LOG

[clang] 607fb1b - [AArch64] Always add -tune-cpu argument to -cc1 driver

Author: David Sherwood Date: 2021-10-19T14:57:51+01:00 New Revision: 607fb1bb8c91a2f284d8c63f3066ab8cc1a66955 URL: https://github.com/llvm/llvm-project/commit/607fb1bb8c91a2f284d8c63f3066ab8cc1a66955 DIFF: https://github.com/llvm/llvm-project/commit/607fb1bb8c91a2f284d8c63f3066ab8cc1a66955.diff

[clang] 23db763 - Fix documentation errors introduced by 607fb1bb8c91a2f284d8c63f3066ab8cc1a66955

Author: David Sherwood Date: 2021-10-19T15:12:03+01:00 New Revision: 23db763b7dadbf99cb46c66c855651ac760e56db URL: https://github.com/llvm/llvm-project/commit/23db763b7dadbf99cb46c66c855651ac760e56db DIFF: https://github.com/llvm/llvm-project/commit/23db763b7dadbf99cb46c66c855651ac760e56db.diff

[clang] [llvm] [AArch64][SVE] Fix definition of bfloat fcvt intrinsics. (PR #110281)

@@ -4072,6 +4078,30 @@ static Value *upgradeX86IntrinsicCall(StringRef Name, CallBase *CI, Function *F, return Rep; } +static Value *upgradeAArch64IntrinsicCall(StringRef Name, CallBase *CI, + Function *F, IRBuilder<> &Builder) { +

[clang] [llvm] [AArch64][SVE] Fix definition of bfloat fcvt intrinsics. (PR #110281)

@@ -5553,6 +5553,14 @@ static SDValue getSVEPredicateBitCast(EVT VT, SDValue Op, SelectionDAG &DAG) { if (InVT == VT) return Op; + // Look through casts to when their input has more lanes than + // VT. This will increase the chances of removing casts that introduce n

[clang] [llvm] [AArch64][SVE] Fix definition of bfloat fcvt intrinsics. (PR #110281)

@@ -1003,6 +998,13 @@ defm SVFCVT_F32_F64 : SInstCvtMXZ<"svcvt_f32[_f64]", "MMPd", "MPd", "d", "aarc defm SVFCVT_F64_F16 : SInstCvtMXZ<"svcvt_f64[_f16]", "ddPO", "dPO", "d", "aarch64_sve_fcvt_f64f16">; defm SVFCVT_F64_F32 : SInstCvtMXZ<"svcvt_f64[_f32]", "ddPM", "dPM", "

[clang] [llvm] [AArch64][SVE] Fix definition of bfloat fcvt intrinsics. (PR #110281)

@@ -5553,6 +5553,14 @@ static SDValue getSVEPredicateBitCast(EVT VT, SDValue Op, SelectionDAG &DAG) { if (InVT == VT) return Op; + // Look through casts to when their input has more lanes than david-arm wrote: Perhaps better written as `casts to ` in

[clang] [llvm] [AArch64][SVE] Fix definition of bfloat fcvt intrinsics. (PR #110281)

https://github.com/david-arm approved this pull request. Looks Astounding To Me. LATM. https://github.com/llvm/llvm-project/pull/110281 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [AArch64] Enable vscale_range with +sme (PR #124466)

@@ -708,7 +708,7 @@ AArch64TargetInfo::getVScaleRange(const LangOptions &LangOpts) const { return std::pair( LangOpts.VScaleMin ? LangOpts.VScaleMin : 1, LangOpts.VScaleMax); - if (hasFeature("sve")) + if (hasFeature("sve") || hasFeature("sme"))

[clang] [llvm] [AArch64][SVE] Improve fixed-length addressing modes. (PR #129732)

@@ -0,0 +1,362 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s +; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -aarch64-sve-vector-bits-min=128 -aarc

[clang] [llvm] [AArch64][SVE] Improve fixed-length addressing modes. (PR #129732)

https://github.com/david-arm approved this pull request. LGTM! https://github.com/llvm/llvm-project/pull/129732 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [AArch64][SVE] Improve fixed-length addressing modes. (PR #129732)

https://github.com/david-arm edited https://github.com/llvm/llvm-project/pull/129732 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] update_test_checks: add new --filter-out-after option (PR #129739)

https://github.com/david-arm closed https://github.com/llvm/llvm-project/pull/129739 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] update_test_checks: add new --filter-out-after option (PR #129739)

david-arm wrote: > I'd be fine with limiting it to update_test_checks, just wanted to make sure > that it works in the instances where it's available. Of course, if we can get > it in the other scripts for free that's great, too! That said, for > update_test_checks, does the regex match the in

[clang] [llvm] update_test_checks: add new --filter-out-after option (PR #129739)

https://github.com/david-arm updated https://github.com/llvm/llvm-project/pull/129739 >From d8487a8d0fb91c0e81636959a80607b9c313bf84 Mon Sep 17 00:00:00 2001 From: David Sherwood Date: Mon, 17 Mar 2025 16:07:03 + Subject: [PATCH] update_test_checks: add new --filter-all-after option Whilst

[clang] [clang][CodeGen] Fix metadata when vectorization is disabled by pragma (PR #135163)

@@ -37,8 +37,8 @@ void test3(int *List, int Length) { List[i] = i * 2; } -// Check that disabling vectorization means a vectorization width of 1, and -// also that vectorization_predicate isn't enabled. +// Check that vectorize is disabled, and also that vectorization_pred

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