davemgreen wrote:
Rebase and ping - thanks.
https://github.com/llvm/llvm-project/pull/135064
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
https://github.com/davemgreen updated
https://github.com/llvm/llvm-project/pull/135064
Rate limit · GitHub
body {
background-color: #f6f8fa;
color: #24292e;
font-family: -apple-system,BlinkMacSystemFont,Segoe
UI,Helvetica,Arial,san
https://github.com/davemgreen commented:
Can you add a release-note that this new CPU has been added?
https://github.com/llvm/llvm-project/pull/139055
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listin
@@ -1262,7 +1262,7 @@ INSTANTIATE_TEST_SUITE_P(
AArch64CPUAliasTestParams::PrintToStringParamName);
// Note: number of CPUs includes aliases.
-static constexpr unsigned NumAArch64CPUArchs = 89;
+static constexpr unsigned NumAArch64CPUArchs = 90;
davemgreen
https://github.com/davemgreen edited
https://github.com/llvm/llvm-project/pull/139055
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
https://github.com/davemgreen commented:
Thanks - this looks sensible to me if these are always present on Grace (I'm
not sure how to check that, I will leave for someone else to review). It
currently uses a bit of a mixture of specifying features individually
(FeatureAES and FeatureSVEAES) an
@@ -944,6 +944,15 @@ def ProcessorFeatures {
list Falkor = [HasV8_0aOps, FeatureCRC, FeatureSHA2,
FeatureAES,
FeatureFPARMv8, FeatureNEON,
FeaturePerfMon,
FeatureRDM];
+ list Grace= [HasV9_0aO
=?utf-8?q?Csan=C3=A1d_Hajd=C3=BA?= ,
=?utf-8?q?Csan=C3=A1d_Hajd=C3=BA?=
Message-ID:
In-Reply-To:
https://github.com/davemgreen approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/125688
___
cfe-commits mailing list
cfe-commits
=?utf-8?q?Csanád_Hajdú?= ,
=?utf-8?q?Csanád_Hajdú?=
Message-ID:
In-Reply-To:
https://github.com/davemgreen closed
https://github.com/llvm/llvm-project/pull/125688
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/
@@ -85,6 +85,9 @@ Changes to the AMDGPU Backend
Changes to the ARM Backend
--
+* The `+nosimd` attribute is now fully supported. Previously, this had no
effect when being used with
+AArch32 targets, however this will now disable NEON instructions being
@@ -334,8 +334,8 @@ ARM_CPU_NAME("cortex-r7", ARMV7R, FK_VFPV3_D16_FP16, false,
(ARM::AEK_MP | ARM::AEK_HWDIVARM))
ARM_CPU_NAME("cortex-r8", ARMV7R, FK_VFPV3_D16_FP16, false,
(ARM::AEK_MP | ARM::AEK_HWDIVARM))
-ARM_CPU_NAME("cortex-r52", ARMV8R, FK_NEO
davemgreen wrote:
It probably needs to not happen with -fno-unaligned-access (or +strict-align),
unless the load / store is known to be 16byte aligned. See
https://github.com/llvm/llvm-project/issues/119732 from recently. (Also I guess
they shouldn't work in BE, but I believe that is not suppo
@@ -0,0 +1,31 @@
+// Ensures that when targeting an ARM target with an Asm file, clang
+// collects the features from the FPU. This is critical in the
+// activation of NEON for supported targets. The Cortex-R52 will be
+// used and tested for VFP and NEON Support
+
+// RUN: %clan
@@ -1,93 +1,93 @@
-// Test of the AArch32 values of -mtp=, checking that each one maps to
-// the right target features.
-
-// RUN: %clang --target=armv7-linux -mtp=cp15 -### -S %s 2>&1 | \
-// RUN: FileCheck -check-prefix=ARMv7_THREAD_POINTER-HARD %s
-// ARMv7_THREAD_POINTER-HARD
https://github.com/davemgreen approved this pull request.
Thanks for the cleanup, LGTM.
(You could probably have just submitted this without review, but that is
getting more rare nowadays).
https://github.com/llvm/llvm-project/pull/134359
___
cfe-com
davemgreen wrote:
The way we tried to mitigate this in the past was to use
-target=aarch64-arm-none-eabi for our downstream compiler, and have downstream
differences gated on the arm vendor. It can help keep the upstream tests the
same if they use -target=aarch64-unknown-linux-gnu, and have do
@@ -1,93 +1,93 @@
-// Test of the AArch32 values of -mtp=, checking that each one maps to
-// the right target features.
-
-// RUN: %clang --target=armv7-linux -mtp=cp15 -### -S %s 2>&1 | \
-// RUN: FileCheck -check-prefix=ARMv7_THREAD_POINTER-HARD %s
-// ARMv7_THREAD_POINTER-HARD
davemgreen wrote:
I was going to suggest in #130623 that we undid this part of the change and
made it an NFC except for +[no]simd. But after looking at it this morning.. I
wasn't sure. It at least it deserved to be its own change :)
I believe that if it used `if (!ForAS || !Generic)` then it
@@ -288,6 +288,7 @@ StringRef sys::detail::getHostCPUNameForARM(StringRef
ProcCpuinfoContent) {
if (Implementer == "0x4e") { // NVIDIA Corporation
return StringSwitch(Part)
.Case("0x004", "carmel")
+.Case("0x10", "olympus")
davemgreen wro
@@ -872,6 +883,16 @@ def ProcessorFeatures {
list Carmel = [HasV8_2aOps, FeatureNEON, FeatureSHA2,
FeatureAES,
FeatureFullFP16, FeatureCRC, FeatureLSE,
FeatureRAS, FeatureRDM,
FeatureFPARMv8];
+ li
@@ -679,20 +679,18 @@ llvm::ARM::FPUKind arm::getARMTargetFeatures(const Driver
&D,
CPUArgFPUKind != llvm::ARM::FK_INVALID ? CPUArgFPUKind :
ArchArgFPUKind;
(void)llvm::ARM::getFPUFeatures(FPUKind, Features);
} else {
-bool Generic = true;
-if (!ForAS) {
https://github.com/davemgreen edited
https://github.com/llvm/llvm-project/pull/130623
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
@@ -38,6 +38,9 @@ Potentially Breaking Changes
- Fix missing diagnostics for uses of declarations when performing typename
access,
such as when performing member access on a '[[deprecated]]' type alias.
(#GH58547)
+- For ARM targets, when using cc1as, the features included
davemgreen wrote:
I didn't believe that the backend supports it properly yet (or was tested
at-all). I'm not sure of the details on why that was deemed OK not to support
it. @sdesmalen-arm and @paulwalker-arm might know more.
https://github.com/llvm/llvm-project/pull/132772
___
davemgreen wrote:
It looks like this came from #122280 / #122716. Sorry about the break, it
should have updated the CPU dependencies correctly too.
LGTM
https://github.com/llvm/llvm-project/pull/139212
___
cfe-commits mailing list
cfe-commits@lists.l
https://github.com/davemgreen edited
https://github.com/llvm/llvm-project/pull/135064
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
@@ -121,7 +121,7 @@ define i32 @test_orr_extract_from_mul_1(i32 %x, i32 %y) {
; CHECK-THUMB-NEXT:orrs r0, r1
; CHECK-THUMB-NEXT:bx lr
entry:
-; CHECk-THUMB: orrs r0, r1
+; CHECK-THUMB: orrs r0, r1
davemgreen wrote:
You can remove this line entirely, th
@@ -22,7 +22,7 @@ define signext i8 @test1(i32 %A) {
; CHECK-V7: @ %bb.0:
; CHECK-V7-NEXT:sbfx r0, r0, #8, #8
; CHECK-V7-NEXT:bx lr
-; CHECk-V7: sbfx r0, r0, #8, #8
+; CHECK-V7: sbfx r0, r0, #8, #8
davemgreen wrote:
Same here.
https://github.com
davemgreen wrote:
These two are failing:
Clang.CodeGen/paren-list-agg-init.cpp
Clang.CodeGenCXX/microsoft-abi-throw.cpp
Can you try and fix them? (or remove them from this review and handle them
separately). The others look OK.
https://github.com/llvm/llvm-project/pull/140373
__
Author: David Green
Date: 2025-05-15T11:51:58+01:00
New Revision: f8f11c541dec9bfc19f80918cf12da71d6ae7b99
URL:
https://github.com/llvm/llvm-project/commit/f8f11c541dec9bfc19f80918cf12da71d6ae7b99
DIFF:
https://github.com/llvm/llvm-project/commit/f8f11c541dec9bfc19f80918cf12da71d6ae7b99.diff
L
https://github.com/davemgreen updated
https://github.com/llvm/llvm-project/pull/135064
>From 9a56ee32712c213b0fa06257bda9c2f31ec44416 Mon Sep 17 00:00:00 2001
From: David Green
Date: Thu, 15 May 2025 20:36:44 +0100
Subject: [PATCH] [AArch64] Change the coercion type of structs with pointer
mem
https://github.com/davemgreen updated
https://github.com/llvm/llvm-project/pull/126945
>From 410d78202cac8221048a83ea466b59cb6e78ea87 Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Wed, 12 Feb 2025 14:31:47 +
Subject: [PATCH 1/2] Add missing Neon Types
The AAPCS64 adds a number of vec
davemgreen wrote:
I was discussing with @tmatheson-arm and he said I could take this over. I've
updated this branch (apparently that does work), trying to address the issues
and clean things up a bit. The new types are not longer a keyword, but that
seems to be OK providing we mark them as imp
https://github.com/davemgreen edited
https://github.com/llvm/llvm-project/pull/126945
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
https://github.com/davemgreen edited
https://github.com/llvm/llvm-project/pull/126945
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
301 - 335 of 335 matches
Mail list logo
