[clang] 690edea - [AArch64] Remove copy/pasted RISC-V extension names from some tests. NFC

Author: Craig Topper Date: 2023-07-31T17:34:38-07:00 New Revision: 690edeab78ba6996a44f6fd9e8fce79cb78e7737 URL: https://github.com/llvm/llvm-project/commit/690edeab78ba6996a44f6fd9e8fce79cb78e7737 DIFF: https://github.com/llvm/llvm-project/commit/690edeab78ba6996a44f6fd9e8fce79cb78e7737.diff

[clang] 244fd4d - [RISCV] Run mem2reg on more scalar C builtin tests to remove allocas and simplify checks. NFC

Author: Craig Topper Date: 2023-08-01T22:10:54-07:00 New Revision: 244fd4dfc56a0d59655c65adac6a7258114b8af2 URL: https://github.com/llvm/llvm-project/commit/244fd4dfc56a0d59655c65adac6a7258114b8af2 DIFF: https://github.com/llvm/llvm-project/commit/244fd4dfc56a0d59655c65adac6a7258114b8af2.diff

[clang] 36ac6ac - [RISCV] Merge rv32 and rv64 Zvb* intrinsic tests. NFC

Author: Craig Topper Date: 2023-08-02T00:08:01-07:00 New Revision: 36ac6ac1dbd0ffd5a4a5de0d6892141f969c130d URL: https://github.com/llvm/llvm-project/commit/36ac6ac1dbd0ffd5a4a5de0d6892141f969c130d DIFF: https://github.com/llvm/llvm-project/commit/36ac6ac1dbd0ffd5a4a5de0d6892141f969c130d.diff

[clang] [AArch64]: Refactor target parser to use BitVector. (PR #65423)

@@ -69,6 +70,24 @@ std::string FormatExtensionFlags(uint64_t Flags) { return llvm::join(Features, ", "); } +std::string SerializeExtensionFlags(Bitset Flags) { + std::string SerializedFlags; + int HexaValue = 0; topperc wrote: Hexa -> Hex. https://githu

[clang] [AArch64]: Refactor target parser to use BitVector. (PR #65423)

@@ -69,6 +70,24 @@ std::string FormatExtensionFlags(uint64_t Flags) { return llvm::join(Features, ", "); } +std::string SerializeExtensionFlags(Bitset Flags) { + std::string SerializedFlags; + int HexaValue = 0; + for(unsigned int i = 0; i < AArch64::AEK_EXTENTIONS_MAX;

[clang] [AArch64]: Refactor target parser to use BitVector. (PR #65423)

@@ -96,64 +97,65 @@ static_assert(FEAT_MAX <= 64, // Arch extension modifiers for CPUs. These are labelled with their Arm ARM // feature name (though the canonical reference for those is AArch64.td) // clang-format off -enum ArchExtKind : uint64_t { - AEK_NONE =1, - A

[clang] [RISCV] Support predefined marcro __riscv_misaligned_{fast,avoid}. (PR #65756)

@@ -1220,3 +1220,15 @@ // RUN: -march=rv64i_zve32x_zvkt1p0 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKT-EXT %s // CHECK-ZVKT-EXT: __riscv_zvkt 100{{$}} + +// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32i -x c -E -dM %s \

[clang] [RISCV] Install sifive_vector.h to riscv-resource-headers (PR #66330)

@@ -623,6 +623,11 @@ install( EXCLUDE_FROM_ALL COMPONENT riscv-resource-headers) +install( topperc wrote: Aren't we also missing `sifive_files` from `add_header_target("riscv-resource-headers" "${riscv_files};${riscv_generated_files}")`? Is there any r

[clang] [Clang] Allow mixed scalar type constraints for inline asm (PR #65465)

@@ -0,0 +1,8 @@ +// RUN: %clang_cc1 %s -emit-llvm -o /dev/null + +unsigned test(float f) topperc wrote: What IR does this generate? https://github.com/llvm/llvm-project/pull/65465 ___ cfe-commits mailing list cfe-commi

[clang] [Clang] Allow mixed scalar type constraints for inline asm (PR #65465)

@@ -0,0 +1,8 @@ +// RUN: %clang_cc1 %s -emit-llvm -o /dev/null + +unsigned test(float f) topperc wrote: This test is using -emit-llvm, but the patch is in SelectionDAG. SelectionDAG doesn't run with -emit-llvm https://github.com/llvm/llvm-project/pull/65465 ___

[clang] [AArch64]: Refactor target parser to use Bitset. (PR #65423)

@@ -96,65 +97,67 @@ static_assert(FEAT_MAX <= 64, // Arch extension modifiers for CPUs. These are labelled with their Arm ARM // feature name (though the canonical reference for those is AArch64.td) // clang-format off -enum ArchExtKind : uint64_t { - AEK_NONE =1, - A

[clang] 51feb1a - [RISCV] Use 'int' for return type for clz_64/clo_64 tests in riscv64-xtheadbb.c. NFC

Author: Craig Topper Date: 2023-07-06T00:25:20-07:00 New Revision: 51feb1a72c5beb8f46d2f5569f3c3398f8902272 URL: https://github.com/llvm/llvm-project/commit/51feb1a72c5beb8f46d2f5569f3c3398f8902272 DIFF: https://github.com/llvm/llvm-project/commit/51feb1a72c5beb8f46d2f5569f3c3398f8902272.diff

[clang] 7c9230c - [RISCV] Add trunc instruction to the __builtin_riscv_ctz_64/__builtin_riscv_clz_64 IR.

Author: Craig Topper Date: 2023-07-06T00:55:16-07:00 New Revision: 7c9230c4f2ad267c716520fb25c4037acd2204fd URL: https://github.com/llvm/llvm-project/commit/7c9230c4f2ad267c716520fb25c4037acd2204fd DIFF: https://github.com/llvm/llvm-project/commit/7c9230c4f2ad267c716520fb25c4037acd2204fd.diff

[clang] ac03e3f - [RISCV] Use 'long' in aes64 Zknd/Zkne builtin tests. NFC

Author: Craig Topper Date: 2023-07-06T01:14:02-07:00 New Revision: ac03e3f51c271b985efeb0fe6b9782cd6928be33 URL: https://github.com/llvm/llvm-project/commit/ac03e3f51c271b985efeb0fe6b9782cd6928be33 DIFF: https://github.com/llvm/llvm-project/commit/ac03e3f51c271b985efeb0fe6b9782cd6928be33.diff

[clang] a8a6a49 - [RISCV] Use 'long' in sha512 builtin tests. NFC

Author: Craig Topper Date: 2023-07-06T07:37:19-07:00 New Revision: a8a6a4947439766355fb7e3dd81947d7f54f687a URL: https://github.com/llvm/llvm-project/commit/a8a6a4947439766355fb7e3dd81947d7f54f687a DIFF: https://github.com/llvm/llvm-project/commit/a8a6a4947439766355fb7e3dd81947d7f54f687a.diff

[clang] 1db5b49 - [RISCV] Use ClangBuiltin in IntrinsicsRISCV.td to map some scalar crypto builtins to IR intrinsic.

Author: Craig Topper Date: 2023-07-06T07:53:31-07:00 New Revision: 1db5b49ae62a7820378d8dfb2d8fd53e1774992d URL: https://github.com/llvm/llvm-project/commit/1db5b49ae62a7820378d8dfb2d8fd53e1774992d DIFF: https://github.com/llvm/llvm-project/commit/1db5b49ae62a7820378d8dfb2d8fd53e1774992d.diff

[clang] a1b7db3 - [RISCV] Split __builtin_riscv_xperm4/8 into separate _32 and _64 builtins.

Author: Craig Topper Date: 2023-07-10T12:18:20-07:00 New Revision: a1b7db3e4ccc30b32fb918f7c6c3ff49233ac03d URL: https://github.com/llvm/llvm-project/commit/a1b7db3e4ccc30b32fb918f7c6c3ff49233ac03d DIFF: https://github.com/llvm/llvm-project/commit/a1b7db3e4ccc30b32fb918f7c6c3ff49233ac03d.diff

[clang] 939f818 - [RISCV] Split __builtin_riscv_brev8 into _32 and _64 builtin.

Author: Craig Topper Date: 2023-07-10T13:01:07-07:00 New Revision: 939f818a662a56a3b118e7e4b0656b6f7038adae URL: https://github.com/llvm/llvm-project/commit/939f818a662a56a3b118e7e4b0656b6f7038adae DIFF: https://github.com/llvm/llvm-project/commit/939f818a662a56a3b118e7e4b0656b6f7038adae.diff

[clang] 2df12f3 - [ARM][AArch64] Make ACLE __clzl/__clzll return unsigned int instead of unsigned long/uint64_t.

Author: Craig Topper Date: 2023-07-11T10:42:25-07:00 New Revision: 2df12f30551e0cb9ecfd49a0cacf929e785c15da URL: https://github.com/llvm/llvm-project/commit/2df12f30551e0cb9ecfd49a0cacf929e785c15da DIFF: https://github.com/llvm/llvm-project/commit/2df12f30551e0cb9ecfd49a0cacf929e785c15da.diff

[clang] 3096226 - [RISCV] Fix name mangling for LMUL!=1 vector types with attribute(rvv_vector_bits)

Author: Craig Topper Date: 2023-07-11T12:01:35-07:00 New Revision: 30962268e7a559d8714cca4d1af742915c9d29b1 URL: https://github.com/llvm/llvm-project/commit/30962268e7a559d8714cca4d1af742915c9d29b1 DIFF: https://github.com/llvm/llvm-project/commit/30962268e7a559d8714cca4d1af742915c9d29b1.diff

[clang] 85b27ac - [ARM][AArch64] Add ARM specific builtin for clz that is not undefined for 0 in ubsan.

Author: Craig Topper Date: 2023-07-12T09:29:18-07:00 New Revision: 85b27ace52560da6f37d58a8460885adcf147c8b URL: https://github.com/llvm/llvm-project/commit/85b27ace52560da6f37d58a8460885adcf147c8b DIFF: https://github.com/llvm/llvm-project/commit/85b27ace52560da6f37d58a8460885adcf147c8b.diff

[clang] d212e99 - [RISCV] Update test after the addition for rounding mode to vfadd intrinsic. NFC

Author: Craig Topper Date: 2023-07-13T10:45:31-07:00 New Revision: d212e99bc5144696f95f09a573da6ed0d85601a0 URL: https://github.com/llvm/llvm-project/commit/d212e99bc5144696f95f09a573da6ed0d85601a0 DIFF: https://github.com/llvm/llvm-project/commit/d212e99bc5144696f95f09a573da6ed0d85601a0.diff

[clang] df71216 - [RISCV] Make __builtin_riscv_clz/ctz return an unsigned int instead of signed int.

Author: Craig Topper Date: 2023-07-14T11:13:47-07:00 New Revision: df71216d0301780de9dfc467745dd10843de4400 URL: https://github.com/llvm/llvm-project/commit/df71216d0301780de9dfc467745dd10843de4400 DIFF: https://github.com/llvm/llvm-project/commit/df71216d0301780de9dfc467745dd10843de4400.diff

[clang] 143e2c2 - [RISCV] Split clmul/clmulh/clmulr builtins into _32 and _64 versions.

Author: Craig Topper Date: 2023-07-14T19:09:15-07:00 New Revision: 143e2c2ac03cbcce290a9f14b0d667bf0f793280 URL: https://github.com/llvm/llvm-project/commit/143e2c2ac03cbcce290a9f14b0d667bf0f793280 DIFF: https://github.com/llvm/llvm-project/commit/143e2c2ac03cbcce290a9f14b0d667bf0f793280.diff

[clang] 599421a - [RISCV] Use unsigned instead of signed types for Zk* and Zb* builtins.

Author: Craig Topper Date: 2023-07-15T11:19:18-07:00 New Revision: 599421ae36c332474c5034b4baaab59833e76418 URL: https://github.com/llvm/llvm-project/commit/599421ae36c332474c5034b4baaab59833e76418 DIFF: https://github.com/llvm/llvm-project/commit/599421ae36c332474c5034b4baaab59833e76418.diff

[clang] e8dc9dc - [IRGen] Remove 'Sve' from the name of some IR names that are shared with RISC-V now.

Author: Craig Topper Date: 2023-07-17T08:43:43-07:00 New Revision: e8dc9dcd7df798039ccf23d74343bf688b1fd648 URL: https://github.com/llvm/llvm-project/commit/e8dc9dcd7df798039ccf23d74343bf688b1fd648 DIFF: https://github.com/llvm/llvm-project/commit/e8dc9dcd7df798039ccf23d74343bf688b1fd648.diff

[clang] a64b3e9 - [RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.

Author: Craig Topper Date: 2023-07-17T08:58:29-07:00 New Revision: a64b3e92c7cb0dd474e0ecbdb9fb86c29487451f URL: https://github.com/llvm/llvm-project/commit/a64b3e92c7cb0dd474e0ecbdb9fb86c29487451f DIFF: https://github.com/llvm/llvm-project/commit/a64b3e92c7cb0dd474e0ecbdb9fb86c29487451f.diff

[clang] c9db799 - [RISCV] Don't add -unaligned-scalar-mem to target features by default.

Author: Craig Topper Date: 2023-08-30T09:52:16-07:00 New Revision: c9db799dda6928d52baad51802c4315a0312e69d URL: https://github.com/llvm/llvm-project/commit/c9db799dda6928d52baad51802c4315a0312e69d DIFF: https://github.com/llvm/llvm-project/commit/c9db799dda6928d52baad51802c4315a0312e69d.diff

[clang] [AArch64]: Refactor target parser to use BitVector. (PR #65423)

topperc wrote: Does this end up creating a global constructor? Could llvm::Bitset be used instead. It has a constexpr constructor. https://github.com/llvm/llvm-project/pull/65423 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.ll

Re: [clang] 4a0267e - Convert a reachable llvm_unreachable into an assert.

If its relatively common for someone making a plugin to mess this up, maybe it should be report_fatal_error instead of only catching it in asserts build? ~Craig On Mon, Mar 23, 2020 at 5:24 AM Aaron Ballman wrote: > On Sun, Mar 22, 2020 at 3:31 PM David Blaikie wrote: > > > > On Sun, Mar 22,

[clang] be0a4fe - [X86] Add -flax-vector-conversions=none to more of the clang CodeGen tests

Author: Craig Topper Date: 2020-04-02T20:39:18-07:00 New Revision: be0a4fef6e789a8f25316af988b2d312d83d0d1c URL: https://github.com/llvm/llvm-project/commit/be0a4fef6e789a8f25316af988b2d312d83d0d1c DIFF: https://github.com/llvm/llvm-project/commit/be0a4fef6e789a8f25316af988b2d312d83d0d1c.diff

[clang] 5b519cf - [X86] Add Indirect Thunk Support to X86 to mitigate Load Value Injection (LVI)

Author: Scott Constable Date: 2020-04-03T00:34:39-07:00 New Revision: 5b519cf1fc6737054cf90b53667e7ddd3a51225f URL: https://github.com/llvm/llvm-project/commit/5b519cf1fc6737054cf90b53667e7ddd3a51225f DIFF: https://github.com/llvm/llvm-project/commit/5b519cf1fc6737054cf90b53667e7ddd3a51225f.dif

[clang] 7273284 - [X86] Add back fmaddsub intrinsics to work towards fixing the strict fp implementation

Author: Craig Topper Date: 2020-02-24T12:07:21-08:00 New Revision: 727328433ad61b8c7acdd4d63e73241303a6beb7 URL: https://github.com/llvm/llvm-project/commit/727328433ad61b8c7acdd4d63e73241303a6beb7 DIFF: https://github.com/llvm/llvm-project/commit/727328433ad61b8c7acdd4d63e73241303a6beb7.diff

[clang] 910718b - [opaque pointer types] Add element type argument to IRBuilder CreatePreserveStructAccessIndex and CreatePreserveArrayAccessIndex

Author: Craig Topper Date: 2019-11-03T10:27:18-08:00 New Revision: 910718bd038cdac1671069594a11f6b26bad9c8b URL: https://github.com/llvm/llvm-project/commit/910718bd038cdac1671069594a11f6b26bad9c8b DIFF: https://github.com/llvm/llvm-project/commit/910718bd038cdac1671069594a11f6b26bad9c8b.diff

[clang] b2b6a54 - [X86] Add support for -mvzeroupper and -mno-vzeroupper to match gcc

Author: Craig Topper Date: 2019-11-04T11:03:54-08:00 New Revision: b2b6a54f847f33f821f41e3e82bf3b86e08817a0 URL: https://github.com/llvm/llvm-project/commit/b2b6a54f847f33f821f41e3e82bf3b86e08817a0 DIFF: https://github.com/llvm/llvm-project/commit/b2b6a54f847f33f821f41e3e82bf3b86e08817a0.diff

[clang] ba73aad - [X86] Add 'mmx' to all CPUs that have a version of 'sse' and weren't already enabling '3dnow'

Author: Craig Topper Date: 2019-11-06T10:02:40-08:00 New Revision: ba73aad4f64f52f2acb5394210ed829355b44383 URL: https://github.com/llvm/llvm-project/commit/ba73aad4f64f52f2acb5394210ed829355b44383 DIFF: https://github.com/llvm/llvm-project/commit/ba73aad4f64f52f2acb5394210ed829355b44383.diff

[clang] a8ccb48 - [X86] Add 'fxsr' feature to -march=pentium2 to match X86.td and gcc.

Author: Craig Topper Date: 2019-11-06T10:27:53-08:00 New Revision: a8ccb48f697d3fbe85c593248ff1053fdf522a6e URL: https://github.com/llvm/llvm-project/commit/a8ccb48f697d3fbe85c593248ff1053fdf522a6e DIFF: https://github.com/llvm/llvm-project/commit/a8ccb48f697d3fbe85c593248ff1053fdf522a6e.diff

[clang] 188d92b - [X86] Don't treat mxcsr as a register name when parsing MS inline assembly.

Author: Craig Topper Date: 2019-11-13T15:26:18-08:00 New Revision: 188d92b9470de71532ec58060cd75f913fd68e59 URL: https://github.com/llvm/llvm-project/commit/188d92b9470de71532ec58060cd75f913fd68e59 DIFF: https://github.com/llvm/llvm-project/commit/188d92b9470de71532ec58060cd75f913fd68e59.diff

[clang] 3cec2a1 - [X86] Fix the implementation of __readcr3/__writecr3 to work in 64-bit mode

Author: Craig Topper Date: 2019-11-14T13:21:36-08:00 New Revision: 3cec2a17de744900401c83aedb442e2acc1f23f8 URL: https://github.com/llvm/llvm-project/commit/3cec2a17de744900401c83aedb442e2acc1f23f8 DIFF: https://github.com/llvm/llvm-project/commit/3cec2a17de744900401c83aedb442e2acc1f23f8.diff

[clang] 890c6ef - [X86] Remove forward declaration of _invpcid from intrin.h. Rely on inline version from immintrin.h

Author: Craig Topper Date: 2019-11-25T16:27:39-08:00 New Revision: 890c6ef1fb1350dd8e6b7b25da411cffbeaf6553 URL: https://github.com/llvm/llvm-project/commit/890c6ef1fb1350dd8e6b7b25da411cffbeaf6553 DIFF: https://github.com/llvm/llvm-project/commit/890c6ef1fb1350dd8e6b7b25da411cffbeaf6553.diff

[clang] e1578fd - [Sema][X86] Consider target attribute into the checks in validateOutputSize and validateInputSize.

Author: Craig Topper Date: 2019-12-06T15:30:59-08:00 New Revision: e1578fd2b79fe5af5f80c0c166a8abd0f816c022 URL: https://github.com/llvm/llvm-project/commit/e1578fd2b79fe5af5f80c0c166a8abd0f816c022 DIFF: https://github.com/llvm/llvm-project/commit/e1578fd2b79fe5af5f80c0c166a8abd0f816c022.diff

[clang] 505aa24 - [Attr] Move ParsedTargetAttr out of the TargetAttr class

Author: Craig Topper Date: 2019-12-09T12:40:41-08:00 New Revision: 505aa2410db6d089279da1a271903ce2633764f6 URL: https://github.com/llvm/llvm-project/commit/505aa2410db6d089279da1a271903ce2633764f6 DIFF: https://github.com/llvm/llvm-project/commit/505aa2410db6d089279da1a271903ce2633764f6.diff

[clang] d35bcbb - [Sema][X86] Consider target attribute into the checks in validateOutputSize and validateInputSize.

Author: Craig Topper Date: 2019-12-23T11:23:30-08:00 New Revision: d35bcbbb5dab0e29b21a586505f5b274377cc41b URL: https://github.com/llvm/llvm-project/commit/d35bcbbb5dab0e29b21a586505f5b274377cc41b DIFF: https://github.com/llvm/llvm-project/commit/d35bcbbb5dab0e29b21a586505f5b274377cc41b.diff

[clang] 9624beb - [docs] Regenerate ClangCommandLineReference.rst

Author: Craig Topper Date: 2020-03-10T11:10:18-07:00 New Revision: 9624beb38a46037f69362650a52e06d8be4fd006 URL: https://github.com/llvm/llvm-project/commit/9624beb38a46037f69362650a52e06d8be4fd006 DIFF: https://github.com/llvm/llvm-project/commit/9624beb38a46037f69362650a52e06d8be4fd006.diff

Re: [clang] ad0e03f - Revert "[FPEnv][X86] Platform-specific builtin constrained FP enablement"

You can't generate assembly from a frontend test unless you also put "REQUIRES: x86-registered-target" in the test ~Craig On Thu, Feb 6, 2020 at 4:17 PM Kevin P. Neal via cfe-commits < cfe-commits@lists.llvm.org> wrote: > > Author: Kevin P. Neal > Date: 2020-02-06T19:17:14-05:00 > New Revision:

[clang] 96400ae - Recommit "[FPEnv][X86] Platform-specific builtin constrained FP enablement"

Author: Craig Topper Date: 2020-02-06T16:54:35-08:00 New Revision: 96400ae2a45c5038ebb4f012f90ffc6dfb30369f URL: https://github.com/llvm/llvm-project/commit/96400ae2a45c5038ebb4f012f90ffc6dfb30369f DIFF: https://github.com/llvm/llvm-project/commit/96400ae2a45c5038ebb4f012f90ffc6dfb30369f.diff

Re: [clang] ad0e03f - Revert "[FPEnv][X86] Platform-specific builtin constrained FP enablement"

Recommitted at 96400ae2a45c5038ebb4f012f90ffc6dfb30369f ~Craig On Thu, Feb 6, 2020 at 4:23 PM Craig Topper wrote: > You can't generate assembly from a frontend test unless you also put > "REQUIRES: x86-registered-target" in the test > > ~Craig > > > On Thu, Feb 6, 2020 at 4:17 PM Kevin P. Neal

[clang] 16b9410 - [X86] Cast to __v4hi instead of __m64 in the implementation of _mm_extract_pi16 and _mm_insert_pi16.

Author: Craig Topper Date: 2020-01-22T16:00:23-06:00 New Revision: 16b9410caa35da976fa5f3cf6dd3d6f3776d51ca URL: https://github.com/llvm/llvm-project/commit/16b9410caa35da976fa5f3cf6dd3d6f3776d51ca DIFF: https://github.com/llvm/llvm-project/commit/16b9410caa35da976fa5f3cf6dd3d6f3776d51ca.diff

[clang] a2137d6 - [X86] Add -flax-vector-conversions=none to all of the x86 vector intrinsic header tests.

Author: Craig Topper Date: 2020-01-23T20:43:50-08:00 New Revision: a2137d6e097c9122c3bb08c4ef70636761aa10b9 URL: https://github.com/llvm/llvm-project/commit/a2137d6e097c9122c3bb08c4ef70636761aa10b9 DIFF: https://github.com/llvm/llvm-project/commit/a2137d6e097c9122c3bb08c4ef70636761aa10b9.diff

r329605 - [X86] Emit native IR for pmuldq/pmuludq builtins.

Author: ctopper Date: Mon Apr 9 12:17:54 2018 New Revision: 329605 URL: http://llvm.org/viewvc/llvm-project?rev=329605&view=rev Log: [X86] Emit native IR for pmuldq/pmuludq builtins. I believe all the pieces are now in place in the backend to make this work correctly. We can either mask the inp

r329738 - [X86] Add test case for llvm change r329734

Author: ctopper Date: Tue Apr 10 11:43:44 2018 New Revision: 329738 URL: http://llvm.org/viewvc/llvm-project?rev=329738&view=rev Log: [X86] Add test case for llvm change r329734 This test ensures the popfd instruction in MS inline assembly can properly find a clobber name for the dirflag registe

r329775 - [X86] Replace 512-bit masked pmaddubsw and pmaddwd intrinsic with unmasked intrinsic and a select.

Author: ctopper Date: Tue Apr 10 21:55:10 2018 New Revision: 329775 URL: http://llvm.org/viewvc/llvm-project?rev=329775&view=rev Log: [X86] Replace 512-bit masked pmaddubsw and pmaddwd intrinsic with unmasked intrinsic and a select. This makes it consistent with the 128/256-bit functions. Somed

r329777 - [X86] Fix typo in intrinsic header file __mask16->__mmask16 from r329775.

Author: ctopper Date: Tue Apr 10 22:17:14 2018 New Revision: 329777 URL: http://llvm.org/viewvc/llvm-project?rev=329777&view=rev Log: [X86] Fix typo in intrinsic header file __mask16->__mmask16 from r329775. Modified: cfe/trunk/lib/Headers/avx512bwintrin.h Modified: cfe/trunk/lib/Headers/avx

r316593 - [X86] Add avx512vpopcntdq to Knights Mill

Author: ctopper Date: Wed Oct 25 10:10:58 2017 New Revision: 316593 URL: http://llvm.org/viewvc/llvm-project?rev=316593&view=rev Log: [X86] Add avx512vpopcntdq to Knights Mill As indicated by Table 1-1 in Intel Architecture Instruction Set Extensions and Future Features Programming Reference fro

r316681 - [X86] Add a target attribute test for no-sse4.

Author: ctopper Date: Thu Oct 26 10:54:22 2017 New Revision: 316681 URL: http://llvm.org/viewvc/llvm-project?rev=316681&view=rev Log: [X86] Add a target attribute test for no-sse4. Modified: cfe/trunk/test/CodeGen/attr-target-x86.c Modified: cfe/trunk/test/CodeGen/attr-target-x86.c URL: htt

r316705 - [X86][Driver] Move all of the X86 feature flags to one spot in the Options.td file and pair them up with their negations.

Author: ctopper Date: Thu Oct 26 14:28:33 2017 New Revision: 316705 URL: http://llvm.org/viewvc/llvm-project?rev=316705&view=rev Log: [X86][Driver] Move all of the X86 feature flags to one spot in the Options.td file and pair them up with their negations. It looks like at one time Options.td was

r316712 - [X86] Make -march=i686 an alias of -march=pentiumpro

Author: ctopper Date: Thu Oct 26 16:06:19 2017 New Revision: 316712 URL: http://llvm.org/viewvc/llvm-project?rev=316712&view=rev Log: [X86] Make -march=i686 an alias of -march=pentiumpro I think the only reason they are different is because we don't set tune_i686 for -march=i686 to match GCC. Bu

r316718 - [X86] Add 'sse4' to X86TargetInfo::isValidFeatureName

Author: ctopper Date: Thu Oct 26 17:18:16 2017 New Revision: 316718 URL: http://llvm.org/viewvc/llvm-project?rev=316718&view=rev Log: [X86] Add 'sse4' to X86TargetInfo::isValidFeatureName sse4 is valid for target attribute and functions as an alias of sse4.2. Modified: cfe/trunk/lib/Basic/Ta

r317069 - [X86] Define i586 and pentium preprocessor defines for -march=lakemont to match GCC

Author: ctopper Date: Tue Oct 31 19:18:49 2017 New Revision: 317069 URL: http://llvm.org/viewvc/llvm-project?rev=317069&view=rev Log: [X86] Define i586 and pentium preprocessor defines for -march=lakemont to match GCC Modified: cfe/trunk/lib/Basic/Targets/X86.cpp cfe/trunk/test/Preproces

r317664 - [X86] Add masked vcvtps2ph builtins to CheckX86BuiltinFunctionCall.

Author: ctopper Date: Tue Nov 7 20:54:26 2017 New Revision: 317664 URL: http://llvm.org/viewvc/llvm-project?rev=317664&view=rev Log: [X86] Add masked vcvtps2ph builtins to CheckX86BuiltinFunctionCall. This ensures that only immediates that fit in 8-bits are used. This matches what we do for the

r317766 - [X86] Rename the VEX scalar fma builtins to end with a '3' to match gcc

Author: ctopper Date: Wed Nov 8 20:10:46 2017 New Revision: 317766 URL: http://llvm.org/viewvc/llvm-project?rev=317766&view=rev Log: [X86] Rename the VEX scalar fma builtins to end with a '3' to match gcc I think we need to use different builtins for the FMA4 instructions since those instructio

r317873 - [X86] Reduce the number of FMA builtins needed by the frontend by adding negates to operands of the fmadd and fmaddsub builtins.

Author: ctopper Date: Thu Nov 9 21:20:32 2017 New Revision: 317873 URL: http://llvm.org/viewvc/llvm-project?rev=317873&view=rev Log: [X86] Reduce the number of FMA builtins needed by the frontend by adding negates to operands of the fmadd and fmaddsub builtins. The backend should be able to com

r318140 - [NewPassManager] Pass the -fdebug-pass-manager flag setting into the Analysis managers to match what we do in opt

Author: ctopper Date: Tue Nov 14 00:48:28 2017 New Revision: 318140 URL: http://llvm.org/viewvc/llvm-project?rev=318140&view=rev Log: [NewPassManager] Pass the -fdebug-pass-manager flag setting into the Analysis managers to match what we do in opt Summary: Currently the -fdebug-pass-manager flag

r318616 - [X86] Set __corei7__ preprocessor defines for skylake server and cannonlake.

Author: ctopper Date: Sat Nov 18 18:55:14 2017 New Revision: 318616 URL: http://llvm.org/viewvc/llvm-project?rev=318616&view=rev Log: [X86] Set __corei7__ preprocessor defines for skylake server and cannonlake. This is the resolution we came to in D38824. Modified: cfe/trunk/lib/Basic/Target

r318617 - [X86] Add icelake CPU support for -march.

Author: ctopper Date: Sat Nov 18 18:55:15 2017 New Revision: 318617 URL: http://llvm.org/viewvc/llvm-project?rev=318617&view=rev Log: [X86] Add icelake CPU support for -march. Modified: cfe/trunk/include/clang/Basic/X86Target.def cfe/trunk/lib/Basic/Targets/X86.cpp cfe/trunk/test/Driv

r318620 - [X86] Make sure 'knm' is accepted by -target-cpu

Author: ctopper Date: Sat Nov 18 20:12:35 2017 New Revision: 318620 URL: http://llvm.org/viewvc/llvm-project?rev=318620&view=rev Log: [X86] Make sure 'knm' is accepted by -target-cpu Modified: cfe/trunk/test/Frontend/x86-target-cpu.c Modified: cfe/trunk/test/Frontend/x86-target-cpu.c URL: h

r318619 - [X86] Make sure 'knm' and 'cannonlake' are accepted by builtin_cpu_is

Author: ctopper Date: Sat Nov 18 20:12:33 2017 New Revision: 318619 URL: http://llvm.org/viewvc/llvm-project?rev=318619&view=rev Log: [X86] Make sure 'knm' and 'cannonlake' are accepted by builtin_cpu_is Modified: cfe/trunk/test/CodeGen/target-builtin-noerror.c Modified: cfe/trunk/test/CodeG

r318662 - [CodeGen] Move Reciprocals option from TargetOptions to CodeGenOptions

Author: ctopper Date: Mon Nov 20 09:09:22 2017 New Revision: 318662 URL: http://llvm.org/viewvc/llvm-project?rev=318662&view=rev Log: [CodeGen] Move Reciprocals option from TargetOptions to CodeGenOptions Diffrential Revision: https://reviews.llvm.org/D40226 Modified: cfe/trunk/include/clang

r318672 - [Docs] Regenerate the command line option reference.

Author: ctopper Date: Mon Nov 20 10:07:43 2017 New Revision: 318672 URL: http://llvm.org/viewvc/llvm-project?rev=318672&view=rev Log: [Docs] Regenerate the command line option reference. Modified: cfe/trunk/docs/ClangCommandLineReference.rst Modified: cfe/trunk/docs/ClangCommandLineReference

r318716 - [X86] Remove 'mm3now' from isValidFeatureName.

Author: ctopper Date: Mon Nov 20 16:33:26 2017 New Revision: 318716 URL: http://llvm.org/viewvc/llvm-project?rev=318716&view=rev Log: [X86] Remove 'mm3now' from isValidFeatureName. The correct spelling is '3dnow' which is already in the list. Modified: cfe/trunk/lib/Basic/Targets/X86.cpp Mo

[clang] 1029747 - [Sema] Fix null pointer dereference handleAlwaysInlineAttr.

Author: Craig Topper Date: 2023-03-16T17:49:34-07:00 New Revision: 10297470e953f4f3968c54c851c8af82b07af00b URL: https://github.com/llvm/llvm-project/commit/10297470e953f4f3968c54c851c8af82b07af00b DIFF: https://github.com/llvm/llvm-project/commit/10297470e953f4f3968c54c851c8af82b07af00b.diff

[clang] e8a632d - Revert "[Sema] Fix null pointer dereference handleAlwaysInlineAttr."

Author: Craig Topper Date: 2023-03-16T20:05:33-07:00 New Revision: e8a632dac2204d66293dd5e0ba92eb65941c4aa3 URL: https://github.com/llvm/llvm-project/commit/e8a632dac2204d66293dd5e0ba92eb65941c4aa3 DIFF: https://github.com/llvm/llvm-project/commit/e8a632dac2204d66293dd5e0ba92eb65941c4aa3.diff

[clang] e82d2e8 - Recommit "[Sema] Fix null pointer dereference handleAlwaysInlineAttr."

Author: Craig Topper Date: 2023-03-16T21:37:35-07:00 New Revision: e82d2e8c9ca34bcccb8fef67a8727543a978 URL: https://github.com/llvm/llvm-project/commit/e82d2e8c9ca34bcccb8fef67a8727543a978 DIFF: https://github.com/llvm/llvm-project/commit/e82d2e8c9ca34bcccb8fef67a8727543a978.diff

Re: [clang] 1029747 - [Sema] Fix null pointer dereference handleAlwaysInlineAttr.

ter this change. Could you take > a look? > > https://lab.llvm.org/buildbot/#/builders/216/builds/18474 > > Thanks, > Matt > >> -Original Message- >> From: cfe-commits On Behalf Of Craig >> Topper via cfe-commits >> Sent: Thursday, March 1

[clang] 4743c03 - [Docs] Add release notes for D146089.

Author: Craig Topper Date: 2023-03-17T09:03:08-07:00 New Revision: 4743c03ca8fcb61b8fa4022c38cf93cf55d7f6fd URL: https://github.com/llvm/llvm-project/commit/4743c03ca8fcb61b8fa4022c38cf93cf55d7f6fd DIFF: https://github.com/llvm/llvm-project/commit/4743c03ca8fcb61b8fa4022c38cf93cf55d7f6fd.diff

[clang] 807d397 - [clang] Fix two unused variable warnings from if statements. NFC

Author: Craig Topper Date: 2023-03-17T09:18:13-07:00 New Revision: 807d397c751355ae02a89cb5178192752b832203 URL: https://github.com/llvm/llvm-project/commit/807d397c751355ae02a89cb5178192752b832203 DIFF: https://github.com/llvm/llvm-project/commit/807d397c751355ae02a89cb5178192752b832203.diff

[clang] 0f4c9c0 - [RISCV] Replace RISCV->RISC-V in strings.

Author: Craig Topper Date: 2023-03-27T09:50:17-07:00 New Revision: 0f4c9c016caf52dc45934e0cbf82b1daabcf1d96 URL: https://github.com/llvm/llvm-project/commit/0f4c9c016caf52dc45934e0cbf82b1daabcf1d96 DIFF: https://github.com/llvm/llvm-project/commit/0f4c9c016caf52dc45934e0cbf82b1daabcf1d96.diff

[clang] 2946361 - [RISCV] Replace RISCV -> RISC-V in comments. NFC

Author: Craig Topper Date: 2023-03-27T09:50:17-07:00 New Revision: 29463612d21b7d630476fcecdc8301ddf5634bf7 URL: https://github.com/llvm/llvm-project/commit/29463612d21b7d630476fcecdc8301ddf5634bf7 DIFF: https://github.com/llvm/llvm-project/commit/29463612d21b7d630476fcecdc8301ddf5634bf7.diff

[clang] 2e73111 - [Sema] Use isSVESizelessBuiltinType instead of isSizelessBuiltinType to prevent crashing on RISC-V.

Author: Craig Topper Date: 2023-02-27T09:19:27-08:00 New Revision: 2e7311170201e07e5e067e397aed8fa482d2fb8b URL: https://github.com/llvm/llvm-project/commit/2e7311170201e07e5e067e397aed8fa482d2fb8b DIFF: https://github.com/llvm/llvm-project/commit/2e7311170201e07e5e067e397aed8fa482d2fb8b.diff

[clang] abafc86 - [AArch64] Use isSVESizelessBuiltinType instead of isSizelessBuiltinType in SVE specific code.

Author: Craig Topper Date: 2023-02-27T17:39:50-08:00 New Revision: abafc869cb656a81ac35a4002627045a6fb37ff2 URL: https://github.com/llvm/llvm-project/commit/abafc869cb656a81ac35a4002627045a6fb37ff2 DIFF: https://github.com/llvm/llvm-project/commit/abafc869cb656a81ac35a4002627045a6fb37ff2.diff

[clang] 8ce6896 - [Sema] Add missing entries to the arrays in GetImplicitConversionName and GetConversionRank.

Author: Craig Topper Date: 2023-02-28T11:16:45-08:00 New Revision: 8ce68969b90288a3dc75c5c15283fc11f97b278a URL: https://github.com/llvm/llvm-project/commit/8ce68969b90288a3dc75c5c15283fc11f97b278a DIFF: https://github.com/llvm/llvm-project/commit/8ce68969b90288a3dc75c5c15283fc11f97b278a.diff

[clang] 90f6a4c - [RISCV] Make D extension imply F extension.

Author: Craig Topper Date: 2023-03-06T19:59:47-08:00 New Revision: 90f6a4cc73d5c40add913e6ed5d34a7a9db58c79 URL: https://github.com/llvm/llvm-project/commit/90f6a4cc73d5c40add913e6ed5d34a7a9db58c79 DIFF: https://github.com/llvm/llvm-project/commit/90f6a4cc73d5c40add913e6ed5d34a7a9db58c79.diff

[clang] 2800d57 - [RISCV] Error if F and Zfinx extensions are specified together.

Author: Craig Topper Date: 2023-03-10T11:26:00-08:00 New Revision: 2800d57e124a605c069a4d4024e73089b2783250 URL: https://github.com/llvm/llvm-project/commit/2800d57e124a605c069a4d4024e73089b2783250 DIFF: https://github.com/llvm/llvm-project/commit/2800d57e124a605c069a4d4024e73089b2783250.diff

[clang] de76c01 - [RISCV] Consistently place single quotes around extension names in error messages.

Author: Craig Topper Date: 2023-03-10T12:36:37-08:00 New Revision: de76c016f722fb27a2b966e860a99966e91c3216 URL: https://github.com/llvm/llvm-project/commit/de76c016f722fb27a2b966e860a99966e91c3216 DIFF: https://github.com/llvm/llvm-project/commit/de76c016f722fb27a2b966e860a99966e91c3216.diff

[clang] 08f1aa8 - [RISCV] Move Zca/Zcb/Zcd/Zcf/Zcmp/Zcmt out of experimental status.

Author: Craig Topper Date: 2023-06-22T09:22:58-07:00 New Revision: 08f1aa87281f969bb5a46a780385819079067826 URL: https://github.com/llvm/llvm-project/commit/08f1aa87281f969bb5a46a780385819079067826 DIFF: https://github.com/llvm/llvm-project/commit/08f1aa87281f969bb5a46a780385819079067826.diff

[clang] e4a93d8 - [RISCV] Sort the extensions in SupportedExtensions and SupportedExperimentalExtensions.

Author: Craig Topper Date: 2023-06-22T11:25:47-07:00 New Revision: e4a93d80f425114e4d943ba176b34590c8d0fece URL: https://github.com/llvm/llvm-project/commit/e4a93d80f425114e4d943ba176b34590c8d0fece DIFF: https://github.com/llvm/llvm-project/commit/e4a93d80f425114e4d943ba176b34590c8d0fece.diff

[clang] f67dfb3 - [RISCV] Use unsigned types for orc_b builtins.

Author: Craig Topper Date: 2023-06-25T22:54:07-07:00 New Revision: f67dfb3cdb4b980103e262fb4c575e6310032dd4 URL: https://github.com/llvm/llvm-project/commit/f67dfb3cdb4b980103e262fb4c575e6310032dd4 DIFF: https://github.com/llvm/llvm-project/commit/f67dfb3cdb4b980103e262fb4c575e6310032dd4.diff

[clang] 4c37d30 - [RISCV] Add support for custom instructions for Sifive S76.

Author: Garvit Gupta Date: 2023-06-26T11:36:00-07:00 New Revision: 4c37d30e22ae655394c8b3a7e292c06d393b9b44 URL: https://github.com/llvm/llvm-project/commit/4c37d30e22ae655394c8b3a7e292c06d393b9b44 DIFF: https://github.com/llvm/llvm-project/commit/4c37d30e22ae655394c8b3a7e292c06d393b9b44.diff

[clang] b4609b4 - [RISCV] Mark zvkn* and zvks* extensions as enabled when all their subextensions are.

Author: Craig Topper Date: 2023-06-29T20:58:55-07:00 New Revision: b4609b4106f3f12882434ac26d8c1c12f57d8dc7 URL: https://github.com/llvm/llvm-project/commit/b4609b4106f3f12882434ac26d8c1c12f57d8dc7 DIFF: https://github.com/llvm/llvm-project/commit/b4609b4106f3f12882434ac26d8c1c12f57d8dc7.diff

[clang] 96a7e05 - [RISCV] Add Zicsr and Zifencei to CPUs in RISCVProcessors.td.

Author: Craig Topper Date: 2023-03-30T15:55:38-07:00 New Revision: 96a7e057567d37e7c65cfce00430ad383a1b URL: https://github.com/llvm/llvm-project/commit/96a7e057567d37e7c65cfce00430ad383a1b DIFF: https://github.com/llvm/llvm-project/commit/96a7e057567d37e7c65cfce00430ad383a1b.diff

[clang] 0109f8d - [AArch64] Use fneg instead of fsub -0.0, X Cin IR expansion of __builtin_neon_vfmsh_f16.

Author: Craig Topper Date: 2023-04-04T09:01:24-07:00 New Revision: 0109f8d1e3bf64e4b23db6e2f284185207e46541 URL: https://github.com/llvm/llvm-project/commit/0109f8d1e3bf64e4b23db6e2f284185207e46541 DIFF: https://github.com/llvm/llvm-project/commit/0109f8d1e3bf64e4b23db6e2f284185207e46541.diff

[clang] 5e2d8a3 - [RISCV] Remove getCPUFeaturesExceptStdExt.

Author: Craig Topper Date: 2023-04-11T10:41:46-07:00 New Revision: 5e2d8a35288802f94df8c60513e7a835b27e621d URL: https://github.com/llvm/llvm-project/commit/5e2d8a35288802f94df8c60513e7a835b27e621d DIFF: https://github.com/llvm/llvm-project/commit/5e2d8a35288802f94df8c60513e7a835b27e621d.diff

[clang] 88d6311 - [RISCV] Print a better error message when a rv32 CPU is used on rv64 and vice versa.

Author: Craig Topper Date: 2023-04-11T10:41:50-07:00 New Revision: 88d6311982557acf2dd04ce101aca077ac311012 URL: https://github.com/llvm/llvm-project/commit/88d6311982557acf2dd04ce101aca077ac311012 DIFF: https://github.com/llvm/llvm-project/commit/88d6311982557acf2dd04ce101aca077ac311012.diff

[clang] 6006d43 - LLVM_FALLTHROUGH => [[fallthrough]]. NFC

Author: Craig Topper Date: 2023-05-24T12:40:10-07:00 New Revision: 6006d43e2d7dda56844f1c3867baa981cfefb8ea URL: https://github.com/llvm/llvm-project/commit/6006d43e2d7dda56844f1c3867baa981cfefb8ea DIFF: https://github.com/llvm/llvm-project/commit/6006d43e2d7dda56844f1c3867baa981cfefb8ea.diff

[clang] 93f8554 - [RISCV] Correct capitalization of SiFive in a comment. NFC

Author: Craig Topper Date: 2023-05-30T09:51:49-07:00 New Revision: 93f8554e65449903a4de4bae4b2f6a09b4129fb6 URL: https://github.com/llvm/llvm-project/commit/93f8554e65449903a4de4bae4b2f6a09b4129fb6 DIFF: https://github.com/llvm/llvm-project/commit/93f8554e65449903a4de4bae4b2f6a09b4129fb6.diff

[clang] a5e5eea - Revert "[RISCV] Add Zvfhmin extension for clang."

Author: Craig Topper Date: 2023-05-31T10:17:11-07:00 New Revision: a5e5eea29ca9e5b5d191b0316ecd8434a6c5afe1 URL: https://github.com/llvm/llvm-project/commit/a5e5eea29ca9e5b5d191b0316ecd8434a6c5afe1 DIFF: https://github.com/llvm/llvm-project/commit/a5e5eea29ca9e5b5d191b0316ecd8434a6c5afe1.diff

[clang] 18ccca4 - [UBSan] Consider zero input to __builtin_clz/ctz to be undefined independent of the target.

Author: Craig Topper Date: 2023-06-02T13:01:05-07:00 New Revision: 18ccca4da8dec5fbfd1072a1c1544ce25f528627 URL: https://github.com/llvm/llvm-project/commit/18ccca4da8dec5fbfd1072a1c1544ce25f528627 DIFF: https://github.com/llvm/llvm-project/commit/18ccca4da8dec5fbfd1072a1c1544ce25f528627.diff

Re: [clang] d05e1e9 - [clang][test][RISCV] Check for __riscv_i in riscv-target-features.c

How does this interact with the CHECK-NOTs above it. Does it check that they don't appear before the __riscv_i but would be allowed after it? ~Craig On Tue, Feb 14, 2023 at 9:03 AM Alex Bradbury via cfe-commits < cfe-commits@lists.llvm.org> wrote: > > Author: Alex Bradbury > Date: 2023-02-14T17

Re: [clang] d05e1e9 - [clang][test][RISCV] Check for __riscv_i in riscv-target-features.c

I don't have a better idea. ~Craig On Tue, Feb 14, 2023 at 12:32 PM Alex Bradbury wrote: > On 2023-02-14 19:56, Craig Topper wrote: > > How does this interact with the CHECK-NOTs above it. Does it check > > that they don't appear before the __riscv_i but would be allowed after > > it? > > Than

[clang] 437727d - [AST] Add 'break; ' to the last case in two switches. NFC

Author: Craig Topper Date: 2023-02-22T13:42:40-08:00 New Revision: 437727d5865af01cf1c901eff931f5113008831c URL: https://github.com/llvm/llvm-project/commit/437727d5865af01cf1c901eff931f5113008831c DIFF: https://github.com/llvm/llvm-project/commit/437727d5865af01cf1c901eff931f5113008831c.diff

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