[llvm] [clang] riscv vector cc (PR #77560)

@@ -0,0 +1,19 @@ +// REQUIRES: riscv-registered-target topperc wrote: Does this test really require `riscv-registered-target`? It doesn't include any headers and doesn't run any IR passes https://github.com/llvm/llvm-project/pull/77560 _

[llvm] [clang] riscv vector cc (PR #77560)

@@ -563,6 +615,10 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF, // directives. for (const auto &Entry : CSI) { int FrameIdx = Entry.getFrameIdx(); +if (FrameIdx >=0 && topperc wrote: space between `>=` and `0` https://github.com/ll

[clang] [RISCV] Overwrite cpu target features for full arch string in target attribute (PR #77426)

@@ -281,10 +248,27 @@ bool RISCVTargetInfo::initFeatureMap( Features["32bit"] = true; } - std::vector NewFeaturesVec = - resolveTargetAttrOverride(FeaturesVec, XLen); + // If a target attribute specified a full arch string, override all the ISA + // extension tar

[clang] [RISCV] Overwrite cpu target features for full arch string in target attribute (PR #77426)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/77426 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Overwrite cpu target features for full arch string in target attribute (PR #77426)

@@ -413,7 +385,9 @@ static void handleFullArchString(StringRef FullArchStr, // Forward the invalid FullArchStr. Features.push_back("+" + FullArchStr.str()); } else { -std::vector FeatStrings = (*RII)->toFeatures(); +// Append a full list of features, including

[clang] [RISCV] Change required features for Zvfhmin intrinsics from ZvfhminOrZvfh to Zvfhmin (PR #77866)

topperc wrote: > I think this was discussed in > https://reviews.llvm.org/D150253?id=523696#inline-1464348 ? I think the its been clarified since then. https://github.com/llvm/llvm-project/pull/77866 ___ cfe-commits mailing list cfe-commits@lists.llv

[clang] [IRGen][AArch64][RISCV] Generalize bitcast between i1 predicate vector and i8 fixed vector. (PR #76548)

topperc wrote: Ping https://github.com/llvm/llvm-project/pull/76548 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Change required features for Zvfhmin intrinsics from ZvfhminOrZvfh to Zvfhmin (PR #77866)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/77866 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Support __riscv_v_fixed_vlen for vbool types. (PR #76551)

topperc wrote: Ping https://github.com/llvm/llvm-project/pull/76551 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [RISCV] Bump Zfbfmin, Zvfbfmin, and Zvfbfwma to 1.0. (PR #78021)

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/78021 None >From 9081bb6aa1e461893680f0ab91048a5ca1cd680a Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Fri, 12 Jan 2024 22:01:03 -0800 Subject: [PATCH] [RISCV] Bump Zfbfmin, Zvfbfmin, and Zvfbfwma to 1.0. --- .

[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)

@@ -416,8 +416,10 @@ class RVVIntrinsic { RVVTypePtr getOutputType() const { return OutputType; } const RVVTypes &getInputTypes() const { return InputTypes; } llvm::StringRef getBuiltinName() const { return BuiltinName; } - llvm::StringRef getName() const { return Name;

[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)

@@ -463,7 +464,7 @@ void RISCVIntrinsicManagerImpl::CreateRVVIntrinsicDecl(LookupResult &LR, bool RISCVIntrinsicManagerImpl::CreateIntrinsicIfFound(LookupResult &LR, IdentifierInfo *II,

[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)

@@ -463,7 +464,7 @@ void RISCVIntrinsicManagerImpl::CreateRVVIntrinsicDecl(LookupResult &LR, bool RISCVIntrinsicManagerImpl::CreateIntrinsicIfFound(LookupResult &LR, IdentifierInfo *II,

[clang] [RISCV] Support __riscv_v_fixed_vlen for vbool types. (PR #76551)

@@ -2415,7 +2415,10 @@ only be a power of 2 between 64 and 65536. For types where LMUL!=1, ``__riscv_v_fixed_vlen`` needs to be scaled by the LMUL of the type before passing to the attribute. -``vbool*_t`` types are not supported at this time. +For ``vbool*_t`` types, ``__ris

[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)

@@ -463,7 +464,7 @@ void RISCVIntrinsicManagerImpl::CreateRVVIntrinsicDecl(LookupResult &LR, bool RISCVIntrinsicManagerImpl::CreateIntrinsicIfFound(LookupResult &LR, IdentifierInfo *II,

[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)

@@ -416,8 +416,10 @@ class RVVIntrinsic { RVVTypePtr getOutputType() const { return OutputType; } const RVVTypes &getInputTypes() const { return InputTypes; } llvm::StringRef getBuiltinName() const { return BuiltinName; } - llvm::StringRef getName() const { return Name;

[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)

https://github.com/topperc deleted https://github.com/llvm/llvm-project/pull/77487 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)

@@ -416,8 +416,10 @@ class RVVIntrinsic { RVVTypePtr getOutputType() const { return OutputType; } const RVVTypes &getInputTypes() const { return InputTypes; } llvm::StringRef getBuiltinName() const { return BuiltinName; } - llvm::StringRef getName() const { return Name;

[clang] [RISCV] Support __riscv_v_fixed_vlen for vbool types. (PR #76551)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/76551 >From 4e651e382ef68ae3f9ff7c9f9059ea1a1bddf892 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 28 Dec 2023 16:14:32 -0800 Subject: [PATCH 1/3] [RISCV] Support __riscv_v_fixed_vlen for vbool types. This ad

[clang] [AST] Use APIntStorage to fix memory leak in EnumConstantDecl. (PR #78311)

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/78311 EnumConstantDecl is allocated by the ASTContext allocator so the destructor is never called. This patch takes a similar approach to IntegerLiteral by using APIntStorage to allocate large APSInts using the ASTCo

[clang] [llvm] [RISCV] Bump Zfbfmin, Zvfbfmin, and Zvfbfwma to 1.0. (PR #78021)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/78021 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [AST] Use APIntStorage to fix memory leak in EnumConstantDecl. (PR #78311)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/78311 >From a8345976354bff4a05a7e0ff28bae152039f5458 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 15 Jan 2024 22:43:55 -0800 Subject: [PATCH 1/2] [AST] Use APIntStorage to fix memory leak in EnumConstantDecl

[clang] [AST] Use APIntStorage to fix memory leak in EnumConstantDecl. (PR #78311)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/78311 >From a8345976354bff4a05a7e0ff28bae152039f5458 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 15 Jan 2024 22:43:55 -0800 Subject: [PATCH 1/3] [AST] Use APIntStorage to fix memory leak in EnumConstantDecl

[clang] [AST] Use APIntStorage to fix memory leak in EnumConstantDecl. (PR #78311)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/78311 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] f3d534c - Revert "[AST] Use APIntStorage to fix memory leak in EnumConstantDecl. (#78311)"

Author: Craig Topper Date: 2024-01-16T12:39:47-08:00 New Revision: f3d534c4251bb08ee210a49fcf721cefff7ded11 URL: https://github.com/llvm/llvm-project/commit/f3d534c4251bb08ee210a49fcf721cefff7ded11 DIFF: https://github.com/llvm/llvm-project/commit/f3d534c4251bb08ee210a49fcf721cefff7ded11.diff

[clang] 142f270 - Recommit "[AST] Use APIntStorage to fix memory leak in EnumConstantDecl. (#78311)"

Author: Craig Topper Date: 2024-01-16T13:52:17-08:00 New Revision: 142f270c279f2576e4618fc0d1121181c7531fdf URL: https://github.com/llvm/llvm-project/commit/142f270c279f2576e4618fc0d1121181c7531fdf DIFF: https://github.com/llvm/llvm-project/commit/142f270c279f2576e4618fc0d1121181c7531fdf.diff

[clang] [llvm] [RISCV] Add Zicfiss support to the shadow call stack implementation. (PR #68075)

@@ -57,11 +57,16 @@ compiled application or the operating system. Integrating the runtime into the operating system should be preferred since otherwise all thread creation and destruction would need to be intercepted by the application. -The instrumentation makes use of the p

[clang] [Headers][X86] Add more descriptions to ia32intrin.h and immintrin.h (PR #77686)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/77686 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Headers][X86] Add more descriptions to ia32intrin.h and immintrin.h (PR #77686)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/77686 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Headers][X86] Add more descriptions to ia32intrin.h and immintrin.h (PR #77686)

@@ -173,25 +183,59 @@ __popcntq(unsigned long long __A) #endif /* __x86_64__ */ #ifdef __x86_64__ +/// Returns the program status and control \c RFLAGS register with the \c VM +///and \c RF flags cleared. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \

[clang] [RISCV] Overwrite cpu target features for full arch string in target attribute (PR #77426)

@@ -281,10 +248,28 @@ bool RISCVTargetInfo::initFeatureMap( Features["32bit"] = true; } - std::vector NewFeaturesVec = - resolveTargetAttrOverride(FeaturesVec, XLen); + // If a target attribute specified a full arch string, override all the ISA + // extension tar

[clang] [RISCV] Overwrite cpu target features for full arch string in target attribute (PR #77426)

@@ -281,10 +248,28 @@ bool RISCVTargetInfo::initFeatureMap( Features["32bit"] = true; } - std::vector NewFeaturesVec = - resolveTargetAttrOverride(FeaturesVec, XLen); + // If a target attribute specified a full arch string, override all the ISA + // extension tar

[clang] [RISCV] Overwrite cpu target features for full arch string in target attribute (PR #77426)

@@ -281,10 +248,28 @@ bool RISCVTargetInfo::initFeatureMap( Features["32bit"] = true; } - std::vector NewFeaturesVec = - resolveTargetAttrOverride(FeaturesVec, XLen); + // If a target attribute specified a full arch string, override all the ISA + // extension tar

[clang] [RISCV] Overwrite cpu target features for full arch string in target attribute (PR #77426)

@@ -281,10 +248,27 @@ bool RISCVTargetInfo::initFeatureMap( Features["32bit"] = true; } - std::vector NewFeaturesVec = - resolveTargetAttrOverride(FeaturesVec, XLen); + // If a target attribute specified a full arch string, override all the ISA + // extension tar

[clang] [RISCV] Overwrite cpu target features for full arch string in target attribute (PR #77426)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/77426 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Headers][X86] Add more descriptions to ia32intrin.h and immintrin.h (PR #77686)

@@ -173,25 +183,59 @@ __popcntq(unsigned long long __A) #endif /* __x86_64__ */ #ifdef __x86_64__ +/// Returns the program status and control \c RFLAGS register with the \c VM +///and \c RF flags cleared. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \

[clang] [llvm] [RISCV] Update TargetAttr target-cpu override rule (PR #75804)

@@ -482,5 +482,35 @@ ParsedTargetAttr RISCVTargetInfo::parseTargetAttr(StringRef Features) const { Ret.Tune = AttrString; } } + + StringRef MCPU = this->getTargetOpts().CPU; + StringRef MTune = this->getTargetOpts().TuneCPU; + + // attr-cpu override march only i

[clang] [llvm] [RISCV] Add support for Smepmp 1.0 (PR #78489)

@@ -56,6 +56,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = { {"smaia", {1, 0}}, {"ssaia", {1, 0}}, +{"smepmp", {1, 0}}, topperc wrote: This is required to be alphabetized. It won't pass lit tests if it isn't. Might even fail w

[llvm] [clang] [RISCV] Add support for Smepmp 1.0 (PR #78489)

@@ -92,6 +92,7 @@ on support follow. ``M``Supported ``Smaia``Supported ``Ssaia``Supported + ``Smepmp`` Supported topperc wrote: I think this list is aphabetized. https://github.com/llvm/llvm-project/pull/78

[clang] [llvm] [RISCV] Update TargetAttr target-cpu override rule (PR #75804)

@@ -482,5 +482,35 @@ ParsedTargetAttr RISCVTargetInfo::parseTargetAttr(StringRef Features) const { Ret.Tune = AttrString; } } + + StringRef MCPU = this->getTargetOpts().CPU; + StringRef MTune = this->getTargetOpts().TuneCPU; + + // attr-cpu override march only i

[clang] [llvm] [RISCV] Add experimental support of Zaamo and Zalrsc (PR #77424)

topperc wrote: > > I guess Zaamo + Zacas is technically a way one could implement atomics > > without LR/SC? > > The Zacas extension depends upon the A extension. I filed an issue asking about that https://github.com/riscv/riscv-zaamo-zalrsc/issues/5 https://github.com/llvm/llvm-project/pull

[llvm] [clang] [RISCV] Add experimental support of Zaamo and Zalrsc (PR #77424)

topperc wrote: Can we split the CodeGen part out of this patch? https://github.com/llvm/llvm-project/pull/77424 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang-tools-extra] [clang] [llvm] [X86] Use RORX over SHR imm (PR #77964)

@@ -4212,6 +4213,89 @@ MachineSDNode *X86DAGToDAGISel::emitPCMPESTR(unsigned ROpc, unsigned MOpc, return CNode; } +// When the consumer of a right shift (arithmetic or logical) wouldn't +// notice the difference if the instruction was a rotate right instead +// (because the

[clang] [llvm] [RISCV] Add support for Smepmp 1.0 (PR #78489)

@@ -1047,6 +1048,14 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-SSAIA-EXT %s // CHECK-SSAIA-EXT: __riscv_ssaia 100{{$}} +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32ismepmp1p0 -x c -E -dM %s \ +// RUN: -o - | FileCheck --che

[llvm] [clang] [RISCV] Add support for Smepmp 1.0 (PR #78489)

@@ -116,6 +116,7 @@ // CHECK-NOT: __riscv_smaia {{.*$}} // CHECK-NOT: __riscv_ssaia {{.*$}} +// CHECK-NOT: __riscv_smepmp {{.*$}} topperc wrote: This is the experimental extension section according to the comment on 115. I guess we're bad at moving things ou

[clang] [RISCV] Re-order riscv-target-features.c to put non-experimental extensions together. (PR #78675)

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/78675 This file has sections for non-experimental and experimental extensions, but we keep forgetting to move things when we change the extension status. >From 55bd10f35b217161cfeb13b8798e584ece0b6bee Mon Sep 17 00:00

[clang] [RISCV] Re-order riscv-target-features.c to put non-experimental extensions together. (PR #78675)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/78675 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Re-order riscv-target-features.c to put non-experimental extensions together. (PR #78675)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/78675 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [RISCV] Add support for Smepmp 1.0 (PR #78489)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/78489 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] 5ffe777 - [RISCV] Add Zvkb test to riscv-target-features.c. NFC

Author: Craig Topper Date: 2024-01-21T21:18:43-08:00 New Revision: 5ffe777c4acd1051c4cebc8464c7e1ae5ca2f689 URL: https://github.com/llvm/llvm-project/commit/5ffe777c4acd1051c4cebc8464c7e1ae5ca2f689 DIFF: https://github.com/llvm/llvm-project/commit/5ffe777c4acd1051c4cebc8464c7e1ae5ca2f689.diff

[clang] 25063be - [RISCV] Replace Zvbb with Zvkb in the Zvk* combine tests in riscv-target-features.c. NFC

Author: Craig Topper Date: 2024-01-21T21:18:43-08:00 New Revision: 25063bedb596943e546994a45710c79fdd6539e8 URL: https://github.com/llvm/llvm-project/commit/25063bedb596943e546994a45710c79fdd6539e8 DIFF: https://github.com/llvm/llvm-project/commit/25063bedb596943e546994a45710c79fdd6539e8.diff

[llvm] [clang] [RISCV] Add sifive-p670 processor (PR #79015)

@@ -237,6 +237,43 @@ def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", SiFiveP400Model, TuneLUIADDIFusion, TuneAUIPCADDIFusion]>; +def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", NoSchedMode

[clang] [llvm] [RISCV] Add sifive-p670 processor (PR #79015)

@@ -2000,6 +2000,14 @@ bool RISCVTargetLowering::shouldSinkOperands( if (!I->getType()->isVectorTy() || !Subtarget.hasVInstructions()) return false; + // Don't sink splat operands if the target prefers it. Some targets requires topperc wrote: This chan

[llvm] [clang] [RISCV] Add sifive-p670 processor (PR #79015)

topperc wrote: Need to update docs/ReleaseNotes.rst https://github.com/llvm/llvm-project/pull/79015 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [RISCV] Add Zic64b, Ziccamoa, Ziccif, Zicclsm, Ziccrse, and Za64rs to sifive-p450. (PR #79030)

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/79030 None >From a3f43ca1e5bc1ab4fd9c41f86d1904a54242a281 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 22 Jan 2024 10:33:39 -0800 Subject: [PATCH] [RISCV] Add Zic64b, Ziccamoa, Ziccif, Zicclsm, Ziccrse, and

[clang] [llvm] [RISCV] Add experimental support of Zaamo and Zalrsc (PR #78970)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/78970 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [RISCV] Add experimental support of Zaamo and Zalrsc (PR #78970)

https://github.com/topperc requested changes to this pull request. https://github.com/llvm/llvm-project/pull/78970 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add experimental support of Zaamo and Zalrsc (PR #78970)

@@ -1105,7 +1129,7 @@ def FeatureForcedAtomics : SubtargetFeature< "forced-atomics", "HasForcedAtomics", "true", "Assume that lock-free native-width atomics are available">; def HasAtomicLdSt -: Predicate<"Subtarget->hasStdExtA() || Subtarget->hasForcedAtomics()">;

[llvm] [clang] [RISCV] Add experimental support of Zaamo and Zalrsc (PR #78970)

@@ -100,6 +100,8 @@ on support follow. ``V``Supported ``Za128rs`` Supported (`See note <#riscv-profiles-extensions-note>`__) ``Za64rs`` Supported (`See note <#riscv-profiles-extensions-note>`__) + ``Zaamo``Supported --

[llvm] [clang] [RISCV] Add experimental support of Zaamo and Zalrsc (PR #78970)

@@ -0,0 +1,11 @@ +# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zaamo < %s 2>&1 | FileCheck %s topperc wrote: Is this duplicating existing A test cases? If so can we split the A extension tests into 2 files as a pre-commit and add these the new Zaamo

[llvm] [clang] [RISCV] Add experimental support of Zaamo and Zalrsc (PR #78970)

topperc wrote: Please add "MC" to the title to distinquish from the other patch. https://github.com/llvm/llvm-project/pull/78970 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add FeatureFastUnalignedAccess to sifive-p450. (PR #79075)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/79075 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] RISCV vector calling convention (1/2) (PR #77560)

@@ -0,0 +1,27 @@ +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM %s + +#include + +// CHECK-LLVM: call riscv_vector_cc @bar +vint32m1_t __attribute__((riscv_vector_c

[clang] [llvm] [RISCV] RISCV vector calling convention (1/2) (PR #77560)

@@ -1006,15 +1077,24 @@ RISCVFrameLowering::assignRVVStackObjectOffsets(MachineFunction &MF) const { MachineFrameInfo &MFI = MF.getFrameInfo(); // Create a buffer of RVV objects to allocate. SmallVector ObjectsToAllocate; - for (int I = 0, E = MFI.getObjectIndexEnd(); I

[llvm] [clang] [RISCV] RISCV vector calling convention (1/2) (PR #77560)

@@ -0,0 +1,27 @@ +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM %s + +#include + +// CHECK-LLVM: call riscv_vector_cc @bar +vint32m1_t __attribute__((riscv_vector_c

[llvm] [clang] [RISCV] RISCV vector calling convention (1/2) (PR #77560)

@@ -24,6 +24,19 @@ def CSR_ILP32D_LP64D : CalleeSavedRegs<(add CSR_ILP32_LP64, F8_D, F9_D, (sequence "F%u_D", 18, 27))>; +defvar CSR_V = (add (sequence "V%u", 1, 7), (sequence "V%u", 24, 31), + V2M2, V4M2, V6M2, V24M2, V26M2, V28M

[clang] [llvm] [RISCV] RISCV vector calling convention (1/2) (PR #77560)

@@ -692,8 +692,71 @@ define <16 x i64> @fshr_v16i64(<16 x i64> %a, <16 x i64> %b, <16 x i64> %c, <16 ; CHECK-NEXT:csrr a0, vlenb ; CHECK-NEXT:slli a0, a0, 3 ; CHECK-NEXT:add sp, sp, a0 +; CHECK-NEXT:.cfi_def_cfa sp, 16 ; CHECK-NEXT:addi sp, sp, 16 ; CHECK

[llvm] [clang] [RISCV] Relax march string order constraint (PR #78120)

@@ -695,6 +695,106 @@ RISCVISAInfo::parseNormalizedArchString(StringRef Arch) { return std::move(ISAInfo); } +static Error splitExtsByUnderscore(StringRef Exts, + std::vector &SplitedExts) { topperc wrote: `SplitExts` Spli

[clang] [llvm] [RISCV] Relax march string order constraint (PR #78120)

@@ -715,6 +815,8 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension, unsigned XLen = HasRV64 ? 64 : 32; std::unique_ptr ISAInfo(new RISCVISAInfo(XLen)); + SmallVector SeenExts; topperc wrote: Maybe SeenExts should be a Set

[clang] [Clang][RISCV][RVV Intrinsic] Fix codegen redundant intrinsic names (PR #77889)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/77889 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][RISCV][RVV Intrinsic] Fix codegen redundant intrinsic names (PR #77889)

topperc wrote: @circYuan do you need me to commit this for you? https://github.com/llvm/llvm-project/pull/77889 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Update TargetAttr target-cpu override rule (PR #75804)

topperc wrote: Is this still needed after #77426 https://github.com/llvm/llvm-project/pull/75804 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Support Xsfvqmaccdod and Xsfvqmaccqoq extensions (PR #68295)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/68295 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Convert all floating point vector type operands to integer vector type (PR #69559)

@@ -450,6 +474,18 @@ multiclass VPatVC_XVV; + // Add another patterns for float type return value. + if !ne(wti.SEW, 8) then { +defvar wfti = !cast("VF"#wti.SEW#wti.LMul.MX); topperc wrote: Do we need new tests for this? https://github.com/llvm/llvm-projec

[clang] [RISCV] Convert all floating point vector type operands to integer vector type (PR #69559)

@@ -450,6 +474,18 @@ multiclass VPatVC_XVV; + // Add another patterns for float type return value. + if !ne(wti.SEW, 8) then { +defvar wfti = !cast("VF"#wti.SEW#wti.LMul.MX); topperc wrote: some mix is probably good enough https://github.com/llvm/llvm-proj

[clang] [Clang][RISCV] Support CSRs in clobbered registers of inline assembly (PR #67646)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/67646 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Add sched model for XiangShan-NanHu (PR #70232)

@@ -936,7 +936,9 @@ def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; +def : ReadAdvance; topperc wrote: Please make FMA16 consistent https://github.com/llvm/llvm-project/pull/70232 ___ cfe

[clang] [RISCV] Support predefined marcro __riscv_misaligned_{fast,avoid}. (PR #65756)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/65756 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Support predefined macro __riscv_misaligned_[fast,avoid]. (PR #65756)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/65756 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][RISCV] Add vcreate intrinsics for RVV non-tuple types (PR #70355)

@@ -345,6 +345,54 @@ class VString { !eq(nf, 8): !if(signed, "", "UvUvUvUvUvUvUvUv")); } + +class FixedVString { + string V = "(LFixedLog2LMUL:" # fixed_lmul # ")" # !if(signed, "v", "Uv"); topperc wrote: Why not pass "v" or "Uv" i

[clang] [Clang][RISCV] Add vcreate intrinsics for RVV non-tuple types (PR #70355)

@@ -345,6 +345,54 @@ class VString { !eq(nf, 8): !if(signed, "", "UvUvUvUvUvUvUvUv")); } + +class FixedVString { + string V = "(LFixedLog2LMUL:" # fixed_lmul # ")" # !if(signed, "v", "Uv"); + string S = !cond(!eq(num, 1): V, topper

[clang] [Clang][RISCV] Add vcreate intrinsics for RVV non-tuple types (PR #70355)

@@ -345,6 +345,54 @@ class VString { !eq(nf, 8): !if(signed, "", "UvUvUvUvUvUvUvUv")); } + +class FixedVString { + string V = "(LFixedLog2LMUL:" # fixed_lmul # ")" # !if(signed, "v", "Uv"); + string S = !cond(!eq(num, 1): V, + !eq

[clang] 56183cf - [RISCV] Disable lax vector conversions between RVVBuiltin types and RVVFixedLengthDataVector.

Author: Craig Topper Date: 2023-10-26T12:20:01-07:00 New Revision: 56183cf608f308ff441b69dcc3ef626acbb014d4 URL: https://github.com/llvm/llvm-project/commit/56183cf608f308ff441b69dcc3ef626acbb014d4 DIFF: https://github.com/llvm/llvm-project/commit/56183cf608f308ff441b69dcc3ef626acbb014d4.diff

[clang] [RISCV] Fix wrong implication for zvknhb. (PR #66860)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/66860 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Support Xsfvfwmaccqqq extensions (PR #68296)

@@ -813,6 +813,14 @@ def HasVendorXSfcie : Predicate<"Subtarget->hasVendorXSfcie()">, AssemblerPredicate<(all_of FeatureVendorXSfcie), "'XSfcie' (SiFive Custom Instruction Extension SCIE.)">; +def FeatureVendorXSfvfwmaccqqq +

[clang] [RISCV] Support Xsfvfwmaccqqq extensions (PR #68296)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/68296 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Support Xsfvfwmaccqqq extensions (PR #68296)

@@ -991,6 +992,7 @@ static const char *ImpliedExtsF[] = {"zicsr"}; static const char *ImpliedExtsV[] = {"zvl128b", "zve64d"}; static const char *ImpliedExtsXTHeadVdot[] = {"v"}; static const char *ImpliedExtsXsfvcp[] = {"zve32x"}; +static const char *ImpliedExtsXsfvfwmaccqqq[]

[clang] [RISCV] Support Xsfvfnrclipxfqf extensions (PR #68297)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/68297 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

r370393 - [X86] Remove what little support we had for MPX

Author: ctopper Date: Thu Aug 29 11:09:02 2019 New Revision: 370393 URL: http://llvm.org/viewvc/llvm-project?rev=370393&view=rev Log: [X86] Remove what little support we had for MPX -Deprecate -mmpx and -mno-mpx command line options -Remove CPUID detection of mpx for -march=native -Remove MPX fro

r370915 - [X86] Add support for avx512bf16 for __builtin_cpu_supports and compiler-rt's cpu indicator.

Author: ctopper Date: Wed Sep 4 09:01:43 2019 New Revision: 370915 URL: http://llvm.org/viewvc/llvm-project?rev=370915&view=rev Log: [X86] Add support for avx512bf16 for __builtin_cpu_supports and compiler-rt's cpu indicator. Modified: cfe/trunk/test/CodeGen/target-builtin-noerror.c Modifi

r371169 - [X86] Prevent passing vectors of __int128 as in llvm IR

Author: ctopper Date: Thu Sep 5 23:02:13 2019 New Revision: 371169 URL: http://llvm.org/viewvc/llvm-project?rev=371169&view=rev Log: [X86] Prevent passing vectors of __int128 as in llvm IR As far as I can tell, gcc passes 256/512 bit vectors __int128 in memory. And passes a vector of 1 _int128

r371168 - [X86] Pre-commit vector of __int128 test cases for D64672.

Author: ctopper Date: Thu Sep 5 23:02:06 2019 New Revision: 371168 URL: http://llvm.org/viewvc/llvm-project?rev=371168&view=rev Log: [X86] Pre-commit vector of __int128 test cases for D64672. Added: cfe/trunk/test/CodeGen/x86-vec-i128.c Added: cfe/trunk/test/CodeGen/x86-vec-i128.c URL: htt

r371430 - [X86] Allow _MM_FROUND_CUR_DIRECTION and _MM_FROUND_NO_EXC to be used together on instructions that only support SAE and not embedded rounding.

Author: ctopper Date: Mon Sep 9 10:48:05 2019 New Revision: 371430 URL: http://llvm.org/viewvc/llvm-project?rev=371430&view=rev Log: [X86] Allow _MM_FROUND_CUR_DIRECTION and _MM_FROUND_NO_EXC to be used together on instructions that only support SAE and not embedded rounding. Current for SAE in

Re: r309488 - [X86][AVX] Ensure vector non-temporal load/store intrinsics force pointer alignment (PR33830)

We can merge all three patches to 5.0. ~Craig On Mon, Jul 31, 2017 at 9:59 AM, Hans Wennborg wrote: > Craig, Simon asked for this to be merged to 5.0 together with r309382 > and r309383 for PR33830. What do you think? > > On Sat, Jul 29, 2017 at 8:33 AM, Simon Pilgrim via cfe-commits > wrote:

r309616 - [X86] Remove -O3 from tbm-builtins.c test file.

Author: ctopper Date: Mon Jul 31 13:21:53 2017 New Revision: 309616 URL: http://llvm.org/viewvc/llvm-project?rev=309616&view=rev Log: [X86] Remove -O3 from tbm-builtins.c test file. A change to InstCombine broke this test, but we generally frown on running optimizations clang tests anyway. So I'

r310191 - [X86] Enable isel to use the PAUSE instruction even when SSE2 is disabled. Clang part

Author: ctopper Date: Sat Aug 5 16:35:54 2017 New Revision: 310191 URL: http://llvm.org/viewvc/llvm-project?rev=310191&view=rev Log: [X86] Enable isel to use the PAUSE instruction even when SSE2 is disabled. Clang part Summary: On older processors this instruction encoding is treated as a NOP.

r310386 - [X86] Support 'avx5124vnniw' and 'avx5124fmaps' for __builtin_cpu_supports.

Author: ctopper Date: Tue Aug 8 10:43:44 2017 New Revision: 310386 URL: http://llvm.org/viewvc/llvm-project?rev=310386&view=rev Log: [X86] Support 'avx5124vnniw' and 'avx5124fmaps' for __builtin_cpu_supports. They still need to be implemented in the intrinsics, the command line, and the backend

r310657 - [X86] Implement __builtin_cpu_is

Author: ctopper Date: Thu Aug 10 13:28:30 2017 New Revision: 310657 URL: http://llvm.org/viewvc/llvm-project?rev=310657&view=rev Log: [X86] Implement __builtin_cpu_is This patch adds support for __builtin_cpu_is. I've tried to match the strings supported to the latest version of gcc. Differenti

[clang] 8b23b2b - [CodeGen] Use CreateFNeg in buildFMulAdd

Author: Craig Topper Date: 2019-12-30T13:24:11-08:00 New Revision: 8b23b2bbd9622c5f079a71c7078d167052f6a70c URL: https://github.com/llvm/llvm-project/commit/8b23b2bbd9622c5f079a71c7078d167052f6a70c DIFF: https://github.com/llvm/llvm-project/commit/8b23b2bbd9622c5f079a71c7078d167052f6a70c.diff

[clang] 70f8dd4 - [CodeGen] Use IRBuilder::CreateFNeg for __builtin_conj

Author: Craig Topper Date: 2019-12-30T13:25:23-08:00 New Revision: 70f8dd4cf604b2be3488895ef0d261154c1c1124 URL: https://github.com/llvm/llvm-project/commit/70f8dd4cf604b2be3488895ef0d261154c1c1124 DIFF: https://github.com/llvm/llvm-project/commit/70f8dd4cf604b2be3488895ef0d261154c1c1124.diff

<    3   4   5   6   7   8   9   10   11   12   >